Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23099

1

T1

2

T2

12

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3795

1

T2

16

T4

25

T5

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20705

1

T2

12

T3

2

T5

21

auto[1]

6189

1

T1

2

T2

16

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T3	1		T142	14		-	-
values[0]	42	1			T149	16		T301	1		T309	12
values[1]	638	1			T150	1		T221	1		T242	5
values[2]	619	1			T3	1		T4	25		T5	12
values[3]	609	1			T36	1		T30	8		T142	13
values[4]	831	1			T13	1		T15	15		T139	28
values[5]	611	1			T5	9		T14	2		T137	5
values[6]	758	1			T13	32		T28	34		T30	24
values[7]	852	1			T2	16		T141	15		T150	1
values[8]	668	1			T144	15		T16	9		T17	4
values[9]	3519	1			T1	2		T2	12		T3	1
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	854	1			T3	1		T4	25		T183	15
values[1]	552	1			T5	12		T36	1		T25	30
values[2]	670	1			T13	1		T142	13		T15	15
values[3]	768	1			T5	9		T141	9		T240	13
values[4]	766	1			T13	32		T14	2		T30	24
values[5]	840	1			T28	34		T41	15		T144	10
values[6]	2929	1			T1	2		T2	16		T8	11
values[7]	626	1			T4	30		T36	1		T30	9
values[8]	938	1			T2	12		T3	2		T12	1
values[9]	206	1			T36	1		T210	10		T177	11
minimum	17745	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	1		T149	11		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T4	13		T183	11		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T36	1		T25	13		T30	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	8		T136	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T145	1		T140	19		T175	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	1		T142	13		T15	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	9		T193	18		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T141	9		T240	13		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	16		T142	12		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	1		T30	3		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T41	15		T144	1		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T28	14		T281	15		T270	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1618	1			T1	2		T8	1		T10	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	16		T144	1		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	12		T30	5		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T36	1		T17	4		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T2	12		T3	2		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T26	1		T137	1		T140	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T36	1		T310	13		T305	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T210	1		T177	2		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T311	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T149	14		T248	1		T151	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	12		T183	4		T242	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T25	17		T30	4		T146	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	4		T137	14		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T175	2		T92	6		T257	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	6		T183	9		T139	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T176	16		T92	2		T45	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T147	2		T175	6		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	16		T137	4		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	1		T30	21		T184	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T144	9		T18	4		T242	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	20		T270	16		T159	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T8	10		T249	33		T186	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T144	14		T16	4		T199	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T4	18		T30	4		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	3		T241	1		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T146	9		T18	1		T198	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T26	14		T146	13		T243	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T305	13		T312	11		T255	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T210	9		T177	9		T288	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T3	1		T142	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T149	8		T309	2		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T301	1		T313	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T221	1		T151	1		T98	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T150	1		T242	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T25	13		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	13		T5	8		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	1		T30	4		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	13		T136	1		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T140	3		T193	18		T176	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	1		T15	9		T139	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	9		T137	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	1		T184	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	16		T41	15		T142	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	14		T30	3		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T150	1		T175	1		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	16		T141	15		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T198	3		T281	7		T277	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T144	1		T16	5		T17	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1889	1			T1	2		T2	12		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T36	1		T26	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T149	8		T309	10		T102	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T313	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T151	6		T98	2		T168	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T242	4		T151	8		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T25	17		T146	4		T149	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	12		T5	4		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	4		T194	8		T175	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T183	9		T147	2		T149	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T176	16		T92	2		T45	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T15	6		T139	16		T175	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T137	4		T251	4		T235	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	1		T184	10		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	16		T144	9		T18	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T28	20		T30	21		T19	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T175	1		T242	15		T215	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T199	11		T270	16		T287	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T198	2		T252	2		T263	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T144	14		T16	4		T241	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T4	18		T8	10		T30	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T26	14		T146	13		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T149	16		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T4	13		T183	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	1		T25	18		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	5		T136	1		T137	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T145	1		T140	1		T175	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T142	1		T15	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T193	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T141	1		T240	1		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	17		T142	1		T137	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T14	2		T30	22		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T41	1		T144	10		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T28	21		T281	1		T270	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T1	2		T8	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	1		T144	15		T16	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	19		T30	5		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T36	1		T17	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	1		T3	2		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T26	15		T137	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T36	1		T310	1		T305	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T210	10		T177	11		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T311	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T149	9		T98	4		T168	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	12		T183	10		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T25	12		T30	3		T222	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T5	7		T263	4		T314	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T140	18		T175	9		T92	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T142	12		T15	4		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	8		T193	17		T176	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T141	8		T240	12		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	15		T142	11		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	2		T136	8		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	14		T18	2		T187	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T28	13		T281	14		T270	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T10	17		T24	20		T143	41
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	15		T16	2		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T4	11		T30	4		T193	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	1		T281	10		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T2	11		T142	13		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T140	8		T141	13		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T310	12		T305	21		T312	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T268	11		T288	11		T264	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T311	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T3	1		T142	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T149	9		T309	11		T102	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T301	1		T313	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T221	1		T151	7		T98	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T150	1		T242	5		T151	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	1		T25	18		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	13		T5	5		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	1		T30	5		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T142	1		T136	1		T183	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T140	1		T193	1		T176	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	1		T15	11		T139	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T137	5		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	2		T184	11		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	17		T41	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	21		T30	22		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T150	1		T175	2		T242	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	1		T141	1		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T198	3		T281	1		T277	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T144	15		T16	7		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T1	2		T2	1		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T36	1		T26	15		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T142	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T149	7		T309	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T313	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T98	4		T168	11		T304	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T38	3		T98	4		T168	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T25	12		T149	2		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	12		T5	7		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	3		T140	18		T175	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T142	12		T183	10		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T140	2		T193	17		T176	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	4		T139	11		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	8		T202	8		T309	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	2		T141	8		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	15		T41	14		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T28	13		T30	2		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T215	17		T217	24		T250	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	15		T141	14		T281	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T198	2		T281	6		T277	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	2		T17	1		T75	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T2	11		T4	11		T10	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T140	8		T141	13		T152	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15