Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21010

1

T2

12

T3

2

T4

30

auto[ADC_CTRL_FILTER_COND_OUT]

5884

1

T1

2

T2

16

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20991

1

T2

12

T3

2

T4

30

auto[1]

5903

1

T1

2

T2

16

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T315	1		-	-		-	-
values[0]	128	1			T5	12		T149	9		T168	24
values[1]	650	1			T28	34		T142	13		T140	22
values[2]	812	1			T3	1		T4	30		T14	2
values[3]	471	1			T36	1		T25	30		T184	11
values[4]	629	1			T3	1		T30	9		T142	26
values[5]	720	1			T41	15		T136	9		T144	15
values[6]	687	1			T2	12		T4	25		T13	32
values[7]	936	1			T2	16		T5	9		T30	8
values[8]	772	1			T36	1		T15	15		T136	1
values[9]	3356	1			T1	2		T3	1		T8	11
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	883	1			T4	30		T5	12		T28	34
values[1]	2952	1			T1	2		T3	1		T8	11
values[2]	499	1			T36	1		T25	30		T142	12
values[3]	674	1			T3	1		T30	9		T142	14
values[4]	666	1			T26	15		T41	15		T144	15
values[5]	803	1			T2	28		T4	25		T13	32
values[6]	863	1			T5	9		T30	8		T136	14
values[7]	708	1			T12	1		T13	1		T36	1
values[8]	842	1			T3	1		T36	1		T144	10
values[9]	234	1			T175	11		T251	5		T98	17
minimum	17770	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	12		T28	14		T142	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	8		T140	19		T147	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T141	15		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1693	1			T1	2		T8	1		T10	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T184	1		T141	9		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T36	1		T25	13		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T136	9		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T30	5		T142	14		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T26	1		T145	1		T141	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T41	15		T144	1		T240	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	12		T146	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	16		T4	13		T13	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T136	14		T137	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	9		T30	4		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T15	9		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T36	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T144	1		T183	11		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T36	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T251	1		T153	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T175	5		T98	9		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17595	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T215	12		T317	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	18		T28	20		T149	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	4		T147	11		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T241	1		T168	9		T20	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	930	1			T8	10		T14	1		T30	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T184	10		T98	2		T252	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T25	17		T35	11		T271	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T18	1		T270	16		T159	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	4		T139	16		T260	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T26	14		T243	11		T296	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	14		T34	3		T151	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T146	13		T176	11		T19	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	12		T13	16		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T137	14		T199	11		T98	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	4		T137	4		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	6		T198	2		T175	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T146	4		T37	12		T177	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T144	9		T183	9		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	2		T18	4		T159	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T251	4		T309	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T175	6		T98	8		T263	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T215	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T315	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T149	3		T162	1		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T5	8		T168	16		T181	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T28	14		T142	13		T140	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T140	19		T147	2		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T4	12		T141	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	1		T30	3		T183	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T184	1		T150	1		T281	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	1		T25	13		T281	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T140	9		T141	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T30	5		T142	26		T139	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T136	9		T145	1		T141	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T41	15		T144	1		T240	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	12		T26	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	13		T13	16		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T136	14		T138	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	16		T5	9		T30	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	9		T136	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T36	1		T146	1		T37	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T12	1		T183	11		T16	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1764	1			T1	2		T3	1		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T149	6		T162	4		T318	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T5	4		T168	8		T181	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T28	20		T248	1		T151	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T147	11		T247	14		T242	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	18		T241	1		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	1		T30	21		T183	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T184	10		T98	2		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T25	17		T210	9		T271	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T270	16		T159	9		T245	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T30	4		T139	16		T260	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T18	1		T243	11		T296	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T144	14		T151	6		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T26	14		T176	11		T19	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	12		T13	16		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T146	13		T199	11		T98	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T30	4		T137	4		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	6		T137	14		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	4		T37	12		T250	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T183	9		T16	4		T146	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1027	1			T8	10		T249	33		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	19		T28	21		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	5		T140	1		T147	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	1		T141	1		T241	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1263	1			T1	2		T8	11		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T184	11		T141	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	1		T25	18		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T136	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T30	5		T142	1		T139	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T26	15		T145	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T41	1		T144	15		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	1		T146	14		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	1		T4	13		T13	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T136	1		T137	15		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	1		T30	5		T137	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T15	11		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T36	1		T146	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T144	10		T183	10		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T36	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T251	5		T153	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T175	7		T98	9		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17738	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T215	10		T317	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	11		T28	13		T142	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	7		T140	18		T168	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T141	14		T168	11		T21	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1360	1			T10	17		T24	20		T30	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T141	8		T281	14		T187	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T25	12		T142	11		T281	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T136	8		T140	8		T193	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	4		T142	13		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T141	13		T243	10		T296	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	14		T240	12		T193	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	11		T176	17		T19	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	15		T4	12		T13	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T136	13		T277	9		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	8		T30	3		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	4		T198	2		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	15		T262	10		T219	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T183	10		T16	2		T149	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	2		T18	2		T211	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T309	14		T179	16		T319	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T175	4		T98	8		T263	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T192	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T215	11		T317	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T315	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T149	7		T162	5		T318	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T5	5		T168	9		T181	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T28	21		T142	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T140	1		T147	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	1		T4	19		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	2		T30	22		T183	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T184	11		T150	1		T281	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	1		T25	18		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	1		T140	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	5		T142	2		T139	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T136	1		T145	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T41	1		T144	15		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	1		T26	15		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	13		T13	17		T198	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T136	1		T138	1		T146	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T5	1		T30	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T15	11		T136	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T36	1		T146	5		T37	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T12	1		T183	10		T16	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1386	1			T1	2		T3	1		T8	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T149	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T5	7		T168	15		T181	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	13		T142	12		T140	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	18		T215	11		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	11		T141	14		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	2		T183	10		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T281	14		T187	14		T93	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T25	12		T281	6		T268	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T140	8		T141	8		T193	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T30	4		T142	24		T139	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T136	8		T141	13		T243	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	14		T240	12		T19	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	11		T176	17		T19	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	12		T13	15		T270	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T136	13		T277	9		T98	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	15		T5	8		T30	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	4		T38	3		T176	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	15		T262	10		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T183	10		T16	2		T149	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1405	1			T10	17		T24	20		T143	41

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15