Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23311

1

T1

2

T3

2

T4

30

auto[ADC_CTRL_FILTER_COND_OUT]

3583

1

T2

28

T3

1

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20979

1

T2

16

T3

2

T4

25

auto[1]

5915

1

T1

2

T2

12

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T137	1		T183	20		T16	9
values[0]	39	1			T242	5		T285	2		T320	10
values[1]	531	1			T4	25		T30	33		T15	15
values[2]	798	1			T25	30		T137	5		T144	15
values[3]	727	1			T5	12		T13	1		T30	8
values[4]	695	1			T3	1		T4	30		T36	1
values[5]	824	1			T13	32		T142	12		T137	15
values[6]	815	1			T5	9		T36	1		T142	13
values[7]	694	1			T2	12		T36	1		T136	9
values[8]	2752	1			T1	2		T8	11		T10	18
values[9]	1057	1			T2	16		T3	2		T14	2
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	530	1			T4	25		T25	30		T30	24
values[1]	821	1			T137	5		T138	7		T140	22
values[2]	744	1			T5	12		T13	1		T30	8
values[3]	644	1			T3	1		T4	30		T36	1
values[4]	835	1			T13	32		T142	25		T137	15
values[5]	866	1			T5	9		T36	1		T240	13
values[6]	2806	1			T1	2		T2	12		T8	11
values[7]	658	1			T2	16		T26	15		T184	11
values[8]	910	1			T3	2		T14	2		T41	15
values[9]	132	1			T137	1		T144	10		T16	9
minimum	17948	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T25	13		T15	9		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	13		T30	3		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T137	1		T138	2		T140	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	1		T239	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	8		T30	4		T140	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T142	14		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	1		T4	12		T183	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	1		T28	14		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T142	13		T146	1		T175	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T13	16		T142	12		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T36	1		T240	13		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	9		T199	1		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T1	2		T8	1		T10	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	12		T12	1		T18	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T184	1		T146	1		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	16		T26	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	1		T41	15		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	1		T14	1		T183	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T137	1		T144	1		T16	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T149	8		T271	1		T23	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17667	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T30	5		T218	1		T280	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T25	17		T15	6		T242	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	12		T30	21		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T137	4		T138	5		T175	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T96	10		T168	9		T287	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	4		T30	4		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	2		T147	9		T149	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	18		T183	4		T139	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T28	20		T263	5		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	13		T175	6		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	16		T137	14		T175	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T151	8		T270	16		T177	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	3		T176	27		T96	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	820	1			T8	10		T249	33		T186	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	4		T151	6		T19	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T184	10		T146	9		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	14		T250	13		T288	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T146	4		T147	2		T149	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	1		T183	9		T198	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T144	9		T16	4		T270	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T149	8		T271	12		T23	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T30	4		T218	8		T280	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T137	1		T16	5		T248	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T183	11		T149	8		T298	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T242	1		T285	1		T320	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	9		T152	11		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	13		T30	8		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T25	13		T137	1		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T144	1		T17	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	8		T30	4		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	1		T142	14		T136	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T4	12		T17	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T36	1		T28	14		T141	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T183	11		T139	12		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T13	16		T142	12		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T36	1		T142	13		T240	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	9		T199	1		T175	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	1		T136	9		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	12		T18	8		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T1	2		T8	1		T10	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	1		T218	1		T250	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T3	1		T41	15		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	16		T3	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T16	4		T248	1		T222	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T183	9		T149	8		T298	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T242	4		T285	1		T320	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T15	6		T152	10		T210	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	12		T30	25		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T25	17		T137	4		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	14		T194	8		T96	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	4		T30	4		T199	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T16	2		T251	4		T210	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	18		T18	1		T98	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T28	20		T147	9		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T183	4		T139	16		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	16		T137	14		T98	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T151	8		T37	12		T243	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T175	2		T34	3		T241	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T247	14		T215	9		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T18	4		T151	6		T19	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	872	1			T8	10		T249	33		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T218	12		T250	13		T293	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T144	9		T184	10		T146	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T26	14		T198	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T25	18		T15	11		T242	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	13		T30	22		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T137	5		T138	7		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T17	1		T239	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	5		T30	5		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T142	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T4	19		T183	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	1		T28	21		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T142	1		T146	14		T175	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	17		T142	1		T137	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T36	1		T240	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	1		T199	1		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T1	2		T8	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	1		T12	1		T18	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T184	11		T146	10		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T26	15		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T41	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	1		T14	2		T183	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T137	1		T144	10		T16	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T149	9		T271	13		T23	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17784	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T30	5		T218	9		T280	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T25	12		T15	4		T294	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	12		T30	2		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T140	20		T240	9		T92	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T277	9		T19	3		T96	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	7		T30	3		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T142	13		T136	13		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	11		T183	10		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T28	13		T141	14		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T142	12		T175	4		T281	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	15		T142	11		T141	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T240	12		T270	10		T219	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	8		T176	27		T96	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T10	17		T24	20		T136	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	11		T18	2		T19	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T198	2		T260	7		T256	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	15		T250	8		T288	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T41	14		T149	11		T193	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T183	10		T268	15		T298	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T16	2		T270	10		T21	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	7		T23	1		T160	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T152	10		T321	13		T322	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T30	4		T280	5		T323	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T137	1		T16	7		T248	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T183	10		T149	9		T298	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T242	5		T285	2		T320	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	11		T152	11		T210	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	13		T30	27		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T25	18		T137	5		T138	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T144	15		T17	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	5		T30	5		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	1		T142	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T4	19		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	1		T28	21		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T183	5		T139	17		T146	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	17		T142	1		T137	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T36	1		T142	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T199	1		T175	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	1		T136	1		T247	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T18	10		T151	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T1	2		T8	11		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T218	13		T250	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T3	1		T41	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	1		T3	1		T14	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T16	2		T222	2		T264	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T183	10		T149	7		T298	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T320	6		T192	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T15	4		T152	10		T294	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	12		T30	6		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T25	12		T140	20		T240	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T19	3		T96	9		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	7		T30	3		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T142	13		T136	13		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	11		T17	1		T98	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	13		T141	14		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T183	10		T139	11		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	15		T142	11		T141	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T142	12		T240	12		T281	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	8		T175	9		T176	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T136	8		T262	12		T215	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	11		T18	2		T19	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T10	17		T24	20		T143	41
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T250	8		T293	4		T297	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T41	14		T149	11		T193	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	15		T268	15		T288	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15