Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23363

1

T1

2

T2

12

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3531

1

T2

16

T3

2

T4

55

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20327

1

T2

28

T3

2

T5

12

auto[1]

6567

1

T1

2

T3

1

T4

55

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	733	1			T11	6		T14	17		T25	5
values[0]	6	1			T137	5		T324	1		-	-
values[1]	762	1			T3	2		T41	15		T136	9
values[2]	2767	1			T1	2		T8	11		T10	18
values[3]	597	1			T12	1		T36	1		T137	15
values[4]	768	1			T4	30		T5	9		T36	1
values[5]	792	1			T2	16		T3	1		T4	25
values[6]	694	1			T2	12		T13	1		T36	1
values[7]	834	1			T26	15		T15	15		T136	1
values[8]	849	1			T5	12		T14	2		T25	30
values[9]	795	1			T28	34		T30	24		T142	14
minimum	17297	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	805	1			T3	1		T41	15		T240	10
values[1]	2764	1			T1	2		T8	11		T10	18
values[2]	578	1			T5	9		T12	1		T36	1
values[3]	804	1			T4	30		T36	1		T30	8
values[4]	754	1			T2	28		T3	1		T4	25
values[5]	727	1			T13	1		T26	15		T15	15
values[6]	786	1			T5	12		T14	2		T136	1
values[7]	827	1			T25	30		T30	9		T142	12
values[8]	810	1			T28	34		T30	24		T142	14
values[9]	174	1			T138	1		T176	29		T210	11
minimum	17865	1			T3	1		T6	18		T7	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T240	10		T149	3		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	1		T41	15		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T1	2		T8	1		T10	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T137	1		T146	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T146	1		T198	3		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	9		T12	1		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T36	1		T140	28		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	12		T30	4		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	12		T3	1		T13	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	16		T4	13		T183	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T149	12		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	1		T15	9		T149	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T136	1		T199	1		T281	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T5	8		T14	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T25	13		T30	5		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T142	12		T184	1		T18	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T30	3		T142	14		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T28	14		T137	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T138	1		T210	1		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T176	18		T279	10		T325	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17625	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T3	1		T137	1		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T149	6		T175	6		T241	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	12		T217	6		T271	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	832	1			T8	10		T249	33		T186	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T137	14		T146	13		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T146	4		T198	2		T251	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T183	4		T16	2		T21	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T242	4		T98	2		T287	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	18		T30	4		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	16		T151	8		T92	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	12		T183	9		T45	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T149	15		T19	5		T98	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	14		T15	6		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T305	12		T314	1		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	4		T14	1		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T25	17		T30	4		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T184	10		T18	5		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	21		T175	2		T248	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	20		T199	11		T175	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T210	10		T283	11		T326	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T176	11		T279	12		T302	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T137	4		T144	14		T250	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	539	1			T11	6		T14	17		T25	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T199	1		T252	1		T279	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T324	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T137	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T136	9		T240	10		T150	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	2		T41	15		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T1	2		T8	1		T10	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	1		T221	1		T187	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T146	1		T147	1		T198	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	1		T36	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T36	1		T140	28		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	12		T5	9		T30	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T13	16		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	16		T4	13		T183	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	12		T13	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T152	11		T38	4		T19	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T136	1		T149	12		T281	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T26	1		T15	9		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T25	13		T30	5		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	8		T14	1		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T30	3		T142	14		T136	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T28	14		T137	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17154	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T215	9		T327	8		T328	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T199	11		T252	7		T279	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T137	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T175	6		T241	1		T270	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T144	14		T37	12		T217	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	824	1			T8	10		T249	33		T186	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T146	13		T151	6		T271	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	4		T147	9		T198	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T137	14		T183	4		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T242	4		T98	2		T287	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	18		T30	4		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	16		T151	8		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	12		T183	9		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T19	5		T98	8		T210	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T152	10		T38	1		T98	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T149	15		T177	4		T305	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T26	14		T15	6		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T25	17		T30	4		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	4		T14	1		T184	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T30	21		T175	2		T248	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	20		T18	1		T175	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T240	1		T149	7		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	1		T41	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T1	2		T8	11		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T137	15		T146	14		T151	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	5		T198	3		T251	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	1		T12	1		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T36	1		T140	2		T242	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	19		T30	5		T198	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	1		T3	1		T13	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	1		T4	13		T183	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	1		T149	16		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T26	15		T15	11		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	1		T199	1		T281	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T5	5		T14	2		T138	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T25	18		T30	5		T144	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T142	1		T184	11		T18	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T30	22		T142	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T28	21		T137	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T138	1		T210	11		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T176	12		T279	13		T325	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17761	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T3	1		T137	5		T144	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T240	9		T149	2		T193	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	14		T187	14		T37	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T10	17		T24	20		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T329	9		T304	3		T298	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T198	2		T215	6		T75	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	8		T183	10		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T140	26		T281	10		T98	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T4	11		T30	3		T243	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	11		T13	15		T92	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	15		T4	12		T183	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T149	11		T19	7		T98	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T15	4		T149	7		T152	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T281	6		T268	11		T305	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	7		T139	11		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T25	12		T30	4		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T142	11		T18	2		T306	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T30	2		T142	13		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T28	13		T92	13		T168	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T294	2		T283	10		T326	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T176	17		T279	9		T307	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T136	8		T330	3		T331	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	489	1			T11	6		T14	17		T25	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T199	12		T252	8		T279	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T324	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T137	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	1		T240	1		T150	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	2		T41	1		T144	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T1	2		T8	11		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T146	14		T221	1		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T146	5		T147	10		T198	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T36	1		T137	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T36	1		T140	2		T242	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	19		T5	1		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T13	17		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	1		T4	13		T183	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	1		T13	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T152	11		T38	2		T19	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	1		T149	16		T281	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T26	15		T15	11		T138	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T25	18		T30	5		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	5		T14	2		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T30	22		T142	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	21		T137	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17297	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T240	12		T277	9		T215	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T279	9		T181	11		T332	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	8		T240	9		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T41	14		T37	15		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T10	17		T24	20		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T187	14		T273	11		T265	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T198	2		T281	10		T215	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T183	10		T16	2		T141	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T140	26		T98	4		T287	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	11		T5	8		T30	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	15		T92	8		T296	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	15		T4	12		T183	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	11		T19	7		T98	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T152	10		T38	3		T19	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T149	11		T281	6		T305	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	4		T139	11		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T25	12		T30	4		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	7		T142	11		T18	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T30	2		T142	13		T136	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	13		T176	17		T92	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15