Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23016

1

T1

2

T4

30

T5

9

auto[ADC_CTRL_FILTER_COND_OUT]

3878

1

T2

28

T3

3

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21074

1

T3

2

T4

55

T5

9

auto[1]

5820

1

T1

2

T2

28

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T333	10		T191	6		-	-
values[0]	70	1			T38	1		T262	3		T210	10
values[1]	655	1			T14	2		T144	10		T184	11
values[2]	739	1			T13	1		T25	30		T26	15
values[3]	623	1			T142	14		T140	9		T240	13
values[4]	540	1			T3	1		T30	8		T136	23
values[5]	2783	1			T1	2		T3	1		T8	11
values[6]	669	1			T2	28		T4	25		T144	15
values[7]	654	1			T36	1		T30	24		T142	25
values[8]	1076	1			T4	30		T36	1		T136	1
values[9]	1337	1			T3	1		T5	21		T13	32
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	910	1			T14	2		T25	30		T26	15
values[1]	760	1			T28	34		T140	9		T141	9
values[2]	521	1			T13	1		T142	14		T240	13
values[3]	2705	1			T1	2		T3	1		T8	11
values[4]	695	1			T2	16		T3	1		T4	25
values[5]	637	1			T2	12		T30	24		T144	15
values[6]	823	1			T36	2		T142	25		T137	1
values[7]	796	1			T3	1		T136	1		T137	15
values[8]	1079	1			T4	30		T5	21		T13	32
values[9]	228	1			T40	1		T263	20		T235	18
minimum	17740	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T144	1		T145	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T14	1		T25	13		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	14		T140	9		T141	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T17	1		T174	1		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T142	14		T240	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T193	24		T199	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T1	2		T8	1		T10	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	1		T36	1		T30	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	9		T140	19		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	16		T3	1		T4	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T30	3		T144	1		T183	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	12		T16	5		T141	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T36	1		T18	2		T175	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T36	1		T142	25		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T137	1		T141	14		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T136	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T4	12		T5	9		T13	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T5	8		T137	1		T183	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T40	1		T304	1		T256	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T263	9		T235	2		T78	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T246	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T144	9		T147	2		T151	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T14	1		T25	17		T26	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	20		T92	6		T210	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T247	14		T270	11		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T198	9		T252	16		T21	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T199	11		T151	6		T177	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T8	10		T249	33		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T30	4		T149	6		T92	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	6		T248	1		T241	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	12		T19	5		T98	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	21		T144	14		T183	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	4		T260	3		T96	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T18	1		T175	2		T38	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T139	16		T149	23		T175	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T137	14		T198	2		T168	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	4		T243	11		T263	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	18		T13	16		T30	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	4		T137	4		T183	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T256	8		T334	13		T283	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T263	11		T235	16		T273	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T246	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T191	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T333	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T262	3		T210	1		T335	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T38	1		T336	1		T284	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T144	1		T145	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T184	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	1		T28	14		T141	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T25	13		T26	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T142	14		T140	9		T240	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T193	24		T199	1		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T136	14		T138	1		T18	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	1		T30	4		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T1	2		T8	1		T10	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T36	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T144	1		T183	11		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	28		T4	13		T260	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	3		T141	14		T17	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T36	1		T142	25		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T4	12		T36	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T136	1		T137	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T5	9		T13	16		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	462	1			T3	1		T5	8		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T191	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T210	9		T335	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T336	6		T284	4		T318	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	9		T151	8		T98	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	1		T184	10		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	20		T147	2		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T25	17		T26	14		T211	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T147	9		T198	9		T242	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T199	11		T247	14		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T138	5		T18	4		T242	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T30	4		T149	6		T92	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T8	10		T249	33		T15	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T19	5		T212	4		T337	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	14		T183	4		T202	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	12		T260	3		T96	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T30	21		T18	1		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	16		T16	4		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T4	18		T137	14		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T146	4		T149	23		T37	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	16		T30	4		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T5	4		T137	4		T183	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T144	10		T145	1		T147	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T14	2		T25	18		T26	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	21		T140	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	1		T174	1		T247	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	1		T142	1		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T193	2		T199	12		T151	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T1	2		T8	11		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T36	1		T30	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	11		T140	1		T248	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T3	1		T4	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	22		T144	15		T183	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T16	7		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T36	1		T18	3		T175	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T36	1		T142	2		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T137	15		T141	1		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	1		T136	1		T146	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T4	19		T5	1		T13	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	5		T137	5		T183	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T40	1		T304	1		T256	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T263	12		T235	18		T78	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T246	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T98	4		T262	14		T211	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	12		T16	2		T98	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	13		T140	8		T141	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T270	10		T168	11		T298	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T142	13		T240	12		T281	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T193	22		T277	9		T19	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T10	17		T24	20		T136	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T30	3		T149	2		T92	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	4		T140	18		T176	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	15		T4	12		T136	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T30	2		T183	10		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	11		T16	2		T141	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T175	9		T38	3		T176	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T142	23		T139	11		T149	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T141	13		T198	2		T168	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T243	10		T263	4		T22	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	11		T5	8		T13	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	7		T183	10		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T256	8		T283	12		T338	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T263	8		T333	9		T273	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T191	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T333	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T262	1		T210	10		T335	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T38	1		T336	7		T284	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T144	10		T145	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T14	2		T184	11		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	1		T28	21		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	18		T26	15		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T142	1		T140	1		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T193	2		T199	12		T247	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	1		T138	6		T18	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	1		T30	5		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T1	2		T8	11		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T36	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	15		T183	5		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	2		T4	13		T260	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	22		T141	1		T17	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T36	1		T142	2		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T4	19		T36	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T136	1		T137	1		T146	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T5	1		T13	17		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T3	1		T5	5		T137	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T191	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T333	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T262	2		T335	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T284	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T98	4		T262	12		T211	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	2		T98	4		T268	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	13		T141	8		T92	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T25	12		T277	9		T211	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T142	13		T140	8		T240	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T193	22		T270	10		T19	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T136	13		T18	2		T281	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T30	3		T136	8		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T10	17		T24	20		T15	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T19	7		T268	15		T282	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T183	10		T202	8		T339	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	26		T4	12		T260	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T30	2		T141	13		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T142	23		T139	11		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T4	11		T175	9		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T149	18		T37	15		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	8		T13	15		T30	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T5	7		T183	10		T240	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15