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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.29


Total test records in report: 919
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T797 /workspace/coverage/default/39.adc_ctrl_filters_both.2486743534 Apr 21 01:59:19 PM PDT 24 Apr 21 02:11:01 PM PDT 24 326291062424 ps
T798 /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2884248046 Apr 21 01:58:41 PM PDT 24 Apr 21 01:58:58 PM PDT 24 26929802789 ps
T799 /workspace/coverage/default/40.adc_ctrl_stress_all.77797658 Apr 21 01:59:35 PM PDT 24 Apr 21 02:07:09 PM PDT 24 255332806586 ps
T800 /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2276058666 Apr 21 01:56:49 PM PDT 24 Apr 21 02:00:39 PM PDT 24 332247002782 ps
T80 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.36361456 Apr 21 12:45:02 PM PDT 24 Apr 21 12:45:04 PM PDT 24 456359824 ps
T801 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3858285497 Apr 21 12:45:15 PM PDT 24 Apr 21 12:45:16 PM PDT 24 497631734 ps
T52 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3404192248 Apr 21 12:45:09 PM PDT 24 Apr 21 12:45:12 PM PDT 24 2050416580 ps
T91 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1723354288 Apr 21 12:44:55 PM PDT 24 Apr 21 12:44:57 PM PDT 24 411844919 ps
T46 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2495286747 Apr 21 12:45:09 PM PDT 24 Apr 21 12:45:22 PM PDT 24 4682303676 ps
T802 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1630493046 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:06 PM PDT 24 368561501 ps
T49 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.320518229 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:08 PM PDT 24 6044951416 ps
T110 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3288145831 Apr 21 12:44:52 PM PDT 24 Apr 21 12:44:54 PM PDT 24 403806284 ps
T53 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2529111457 Apr 21 12:45:02 PM PDT 24 Apr 21 12:45:04 PM PDT 24 591934695 ps
T58 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1900010176 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:10 PM PDT 24 398655334 ps
T59 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.863941680 Apr 21 12:45:17 PM PDT 24 Apr 21 12:45:22 PM PDT 24 440894118 ps
T47 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2023656211 Apr 21 12:44:58 PM PDT 24 Apr 21 12:45:03 PM PDT 24 2346061783 ps
T64 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2371241392 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:07 PM PDT 24 574614292 ps
T131 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.833041613 Apr 21 12:44:55 PM PDT 24 Apr 21 12:44:56 PM PDT 24 800469404 ps
T48 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.366886603 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:22 PM PDT 24 26737001736 ps
T803 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.61785203 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:03 PM PDT 24 310546582 ps
T60 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3175032511 Apr 21 12:44:57 PM PDT 24 Apr 21 12:44:59 PM PDT 24 1044945826 ps
T124 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3641903791 Apr 21 12:45:10 PM PDT 24 Apr 21 12:45:12 PM PDT 24 501138838 ps
T81 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2056433854 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:07 PM PDT 24 453606544 ps
T50 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1426367644 Apr 21 12:45:06 PM PDT 24 Apr 21 12:45:14 PM PDT 24 8250098629 ps
T804 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1645712607 Apr 21 12:45:21 PM PDT 24 Apr 21 12:45:23 PM PDT 24 430114345 ps
T805 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2112107257 Apr 21 12:45:17 PM PDT 24 Apr 21 12:45:19 PM PDT 24 403769164 ps
T125 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2917245568 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:14 PM PDT 24 488492053 ps
T51 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2734123573 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:21 PM PDT 24 4583257196 ps
T111 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.475002779 Apr 21 12:45:28 PM PDT 24 Apr 21 12:45:30 PM PDT 24 1101827646 ps
T806 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2386619105 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:03 PM PDT 24 415970724 ps
T368 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2443229580 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:13 PM PDT 24 4482128049 ps
T807 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.780307689 Apr 21 12:45:08 PM PDT 24 Apr 21 12:45:10 PM PDT 24 382447993 ps
T54 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.62964230 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:12 PM PDT 24 8559236382 ps
T808 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3785945007 Apr 21 12:45:11 PM PDT 24 Apr 21 12:45:13 PM PDT 24 364095580 ps
T62 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3115124368 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:07 PM PDT 24 370236050 ps
T63 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3569453304 Apr 21 12:44:50 PM PDT 24 Apr 21 12:44:53 PM PDT 24 364070808 ps
T809 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4003016928 Apr 21 12:45:08 PM PDT 24 Apr 21 12:45:10 PM PDT 24 452343891 ps
T810 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.137376588 Apr 21 12:45:03 PM PDT 24 Apr 21 12:45:05 PM PDT 24 451742461 ps
T369 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3094840705 Apr 21 12:44:57 PM PDT 24 Apr 21 12:45:05 PM PDT 24 8626046032 ps
T811 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3818961328 Apr 21 12:45:11 PM PDT 24 Apr 21 12:45:15 PM PDT 24 548077462 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2247285024 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:02 PM PDT 24 299089317 ps
T813 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.666499295 Apr 21 12:45:03 PM PDT 24 Apr 21 12:45:05 PM PDT 24 448306769 ps
T814 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1915810900 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:10 PM PDT 24 524544395 ps
T815 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.188357288 Apr 21 12:45:03 PM PDT 24 Apr 21 12:45:04 PM PDT 24 528795890 ps
T816 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3503129610 Apr 21 12:44:55 PM PDT 24 Apr 21 12:44:57 PM PDT 24 400246394 ps
T126 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.695401649 Apr 21 12:44:55 PM PDT 24 Apr 21 12:44:57 PM PDT 24 2744205689 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.322206364 Apr 21 12:45:09 PM PDT 24 Apr 21 12:45:13 PM PDT 24 530887884 ps
T818 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3333036313 Apr 21 12:44:56 PM PDT 24 Apr 21 12:45:00 PM PDT 24 448577846 ps
T819 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3116752893 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:08 PM PDT 24 534929592 ps
T820 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1714556129 Apr 21 12:45:17 PM PDT 24 Apr 21 12:45:20 PM PDT 24 474128827 ps
T112 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3934663952 Apr 21 12:44:56 PM PDT 24 Apr 21 12:45:02 PM PDT 24 1074685287 ps
T821 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2654704577 Apr 21 12:45:06 PM PDT 24 Apr 21 12:45:09 PM PDT 24 1149870718 ps
T127 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.160249332 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:01 PM PDT 24 569358280 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.544722149 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:02 PM PDT 24 328365220 ps
T113 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3852565287 Apr 21 12:44:56 PM PDT 24 Apr 21 12:44:58 PM PDT 24 459575999 ps
T823 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3461819979 Apr 21 12:45:24 PM PDT 24 Apr 21 12:45:34 PM PDT 24 8809902058 ps
T824 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3909847606 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:15 PM PDT 24 3866288782 ps
T825 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1250894962 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:07 PM PDT 24 335892859 ps
T826 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2711722852 Apr 21 12:45:16 PM PDT 24 Apr 21 12:45:18 PM PDT 24 378972061 ps
T128 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1351631186 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:01 PM PDT 24 355256739 ps
T114 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1033499991 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:07 PM PDT 24 379172212 ps
T827 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3640433068 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:06 PM PDT 24 483800557 ps
T828 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2282563675 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:03 PM PDT 24 433913767 ps
T829 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1882700568 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:14 PM PDT 24 408052120 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3946633686 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:02 PM PDT 24 452260244 ps
T130 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.311610150 Apr 21 12:45:25 PM PDT 24 Apr 21 12:45:29 PM PDT 24 4019308908 ps
T120 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3729620960 Apr 21 12:45:06 PM PDT 24 Apr 21 12:45:09 PM PDT 24 375873970 ps
T830 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.103706624 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:14 PM PDT 24 514544844 ps
T831 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.503883441 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:06 PM PDT 24 633817674 ps
T832 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3260709619 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:10 PM PDT 24 429824712 ps
T833 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4094437542 Apr 21 12:44:56 PM PDT 24 Apr 21 12:44:58 PM PDT 24 585356752 ps
T834 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4247835588 Apr 21 12:45:10 PM PDT 24 Apr 21 12:45:12 PM PDT 24 553316731 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3212491894 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:12 PM PDT 24 26862949538 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1699451479 Apr 21 12:45:14 PM PDT 24 Apr 21 12:45:43 PM PDT 24 18370329965 ps
T836 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1592263570 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:07 PM PDT 24 513068811 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3304864482 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:10 PM PDT 24 693938636 ps
T838 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3983029908 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:07 PM PDT 24 548572598 ps
T839 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3144427823 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:08 PM PDT 24 343588820 ps
T840 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.952219761 Apr 21 12:44:56 PM PDT 24 Apr 21 12:45:01 PM PDT 24 4982953303 ps
T841 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2266068575 Apr 21 12:45:16 PM PDT 24 Apr 21 12:45:17 PM PDT 24 285302860 ps
T116 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3974618732 Apr 21 12:45:10 PM PDT 24 Apr 21 12:45:14 PM PDT 24 1267006998 ps
T842 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3963408162 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:08 PM PDT 24 467549521 ps
T843 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2098198788 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:04 PM PDT 24 511592436 ps
T844 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.821464384 Apr 21 12:45:10 PM PDT 24 Apr 21 12:45:14 PM PDT 24 2554174076 ps
T845 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1900802947 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:01 PM PDT 24 537342019 ps
T846 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1733849621 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:06 PM PDT 24 4320381943 ps
T847 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3769481062 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:01 PM PDT 24 294273124 ps
T848 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3908698690 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:09 PM PDT 24 487249695 ps
T849 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.615476384 Apr 21 12:45:38 PM PDT 24 Apr 21 12:45:51 PM PDT 24 2611795940 ps
T850 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4179020126 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:18 PM PDT 24 4190185640 ps
T851 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.262449345 Apr 21 12:45:10 PM PDT 24 Apr 21 12:45:14 PM PDT 24 463176061 ps
T852 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3897503899 Apr 21 12:44:49 PM PDT 24 Apr 21 12:44:57 PM PDT 24 2782615827 ps
T853 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.560781539 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:06 PM PDT 24 418168460 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3441075910 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:06 PM PDT 24 1063542960 ps
T854 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4067120708 Apr 21 12:45:13 PM PDT 24 Apr 21 12:45:20 PM PDT 24 2733794119 ps
T855 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3956163012 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:14 PM PDT 24 412471669 ps
T856 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3139526791 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:09 PM PDT 24 584349262 ps
T65 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1749355923 Apr 21 12:45:13 PM PDT 24 Apr 21 12:45:16 PM PDT 24 4567432179 ps
T857 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2079072821 Apr 21 12:45:03 PM PDT 24 Apr 21 12:45:05 PM PDT 24 404522535 ps
T858 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4062878962 Apr 21 12:45:15 PM PDT 24 Apr 21 12:45:16 PM PDT 24 425398262 ps
T859 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.177803172 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:03 PM PDT 24 2629387323 ps
T860 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2702645433 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:13 PM PDT 24 4976501264 ps
T861 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1969108320 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:08 PM PDT 24 417255475 ps
T862 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1260554875 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:06 PM PDT 24 328521280 ps
T863 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4173757686 Apr 21 12:44:56 PM PDT 24 Apr 21 12:44:58 PM PDT 24 1838462835 ps
T864 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.636541173 Apr 21 12:45:11 PM PDT 24 Apr 21 12:45:17 PM PDT 24 1271176062 ps
T66 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3499868761 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:19 PM PDT 24 8420783616 ps
T865 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1083904050 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:03 PM PDT 24 298798981 ps
T866 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2324252259 Apr 21 12:45:16 PM PDT 24 Apr 21 12:45:18 PM PDT 24 319600570 ps
T867 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.210926943 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:10 PM PDT 24 430049681 ps
T868 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.923659950 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:01 PM PDT 24 324082769 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2135540218 Apr 21 12:45:09 PM PDT 24 Apr 21 12:45:22 PM PDT 24 8726530526 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3807608992 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:06 PM PDT 24 1415168174 ps
T871 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2058759567 Apr 21 12:45:02 PM PDT 24 Apr 21 12:45:05 PM PDT 24 4949037473 ps
T872 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4162979400 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:10 PM PDT 24 5316984290 ps
T873 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1311894587 Apr 21 12:44:56 PM PDT 24 Apr 21 12:44:58 PM PDT 24 461140631 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1221993671 Apr 21 12:45:18 PM PDT 24 Apr 21 12:45:25 PM PDT 24 4545131803 ps
T875 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2998873387 Apr 21 12:44:53 PM PDT 24 Apr 21 12:44:55 PM PDT 24 449030023 ps
T876 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1637825278 Apr 21 12:44:53 PM PDT 24 Apr 21 12:44:55 PM PDT 24 1784424553 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2768325786 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:08 PM PDT 24 535933615 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3156790108 Apr 21 12:44:55 PM PDT 24 Apr 21 12:44:57 PM PDT 24 368072508 ps
T878 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.40412398 Apr 21 12:45:11 PM PDT 24 Apr 21 12:45:13 PM PDT 24 303193875 ps
T879 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.195753057 Apr 21 12:44:54 PM PDT 24 Apr 21 12:44:56 PM PDT 24 318174465 ps
T880 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1123284341 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:07 PM PDT 24 386160836 ps
T881 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1417045284 Apr 21 12:44:55 PM PDT 24 Apr 21 12:44:57 PM PDT 24 345876648 ps
T882 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2573085828 Apr 21 12:45:02 PM PDT 24 Apr 21 12:45:04 PM PDT 24 511336851 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2464878431 Apr 21 12:44:58 PM PDT 24 Apr 21 12:45:00 PM PDT 24 1134041711 ps
T883 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.453934051 Apr 21 12:45:03 PM PDT 24 Apr 21 12:45:06 PM PDT 24 531636748 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2856561920 Apr 21 12:44:50 PM PDT 24 Apr 21 12:45:04 PM PDT 24 8770629444 ps
T885 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.238201500 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:13 PM PDT 24 464702222 ps
T886 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.757509612 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:02 PM PDT 24 566321650 ps
T887 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.601907722 Apr 21 12:45:04 PM PDT 24 Apr 21 12:45:07 PM PDT 24 406353057 ps
T888 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.986408309 Apr 21 12:45:20 PM PDT 24 Apr 21 12:45:22 PM PDT 24 4222652304 ps
T121 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3661454782 Apr 21 12:45:07 PM PDT 24 Apr 21 12:45:10 PM PDT 24 328448588 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.915915616 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:08 PM PDT 24 587445456 ps
T890 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2130916531 Apr 21 12:44:56 PM PDT 24 Apr 21 12:45:02 PM PDT 24 4388793636 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.663265621 Apr 21 12:44:58 PM PDT 24 Apr 21 12:45:10 PM PDT 24 4346685011 ps
T892 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3952379595 Apr 21 12:45:15 PM PDT 24 Apr 21 12:45:17 PM PDT 24 435565369 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.35142760 Apr 21 12:45:02 PM PDT 24 Apr 21 12:45:04 PM PDT 24 596715419 ps
T894 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3505356061 Apr 21 12:45:17 PM PDT 24 Apr 21 12:45:21 PM PDT 24 2401695635 ps
T122 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.5049112 Apr 21 12:44:51 PM PDT 24 Apr 21 12:44:55 PM PDT 24 940945485 ps
T895 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.181466372 Apr 21 12:45:10 PM PDT 24 Apr 21 12:45:14 PM PDT 24 484673082 ps
T123 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4197902240 Apr 21 12:45:06 PM PDT 24 Apr 21 12:45:09 PM PDT 24 512378178 ps
T896 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3434399192 Apr 21 12:45:10 PM PDT 24 Apr 21 12:45:12 PM PDT 24 600841219 ps
T370 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.837476467 Apr 21 12:44:52 PM PDT 24 Apr 21 12:45:00 PM PDT 24 8527325504 ps
T897 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1513795055 Apr 21 12:45:03 PM PDT 24 Apr 21 12:45:08 PM PDT 24 4676381774 ps
T898 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2241394164 Apr 21 12:44:55 PM PDT 24 Apr 21 12:45:14 PM PDT 24 4448216260 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3008196081 Apr 21 12:45:06 PM PDT 24 Apr 21 12:45:08 PM PDT 24 393332461 ps
T900 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.998142885 Apr 21 12:45:18 PM PDT 24 Apr 21 12:45:19 PM PDT 24 497115015 ps
T901 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1135601642 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:13 PM PDT 24 384365216 ps
T67 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2084409524 Apr 21 12:44:52 PM PDT 24 Apr 21 12:45:12 PM PDT 24 8196729356 ps
T902 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1091242227 Apr 21 12:45:14 PM PDT 24 Apr 21 12:45:21 PM PDT 24 460827825 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1509588337 Apr 21 12:45:15 PM PDT 24 Apr 21 12:45:28 PM PDT 24 8825551761 ps
T904 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2005356522 Apr 21 12:44:54 PM PDT 24 Apr 21 12:44:55 PM PDT 24 513668052 ps
T905 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.655669125 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:02 PM PDT 24 458515713 ps
T906 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.885497379 Apr 21 12:45:08 PM PDT 24 Apr 21 12:45:10 PM PDT 24 480694042 ps
T907 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3645012642 Apr 21 12:45:06 PM PDT 24 Apr 21 12:45:08 PM PDT 24 483592459 ps
T908 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4203908526 Apr 21 12:45:18 PM PDT 24 Apr 21 12:45:20 PM PDT 24 405368138 ps
T909 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1816028786 Apr 21 12:45:02 PM PDT 24 Apr 21 12:45:05 PM PDT 24 325212623 ps
T910 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1777157554 Apr 21 12:44:58 PM PDT 24 Apr 21 12:45:01 PM PDT 24 433649192 ps
T911 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.374773673 Apr 21 12:45:01 PM PDT 24 Apr 21 12:45:05 PM PDT 24 667400217 ps
T912 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1583722009 Apr 21 12:44:57 PM PDT 24 Apr 21 12:44:59 PM PDT 24 552466899 ps
T913 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1532579506 Apr 21 12:45:06 PM PDT 24 Apr 21 12:45:11 PM PDT 24 1529262635 ps
T914 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.890826504 Apr 21 12:45:12 PM PDT 24 Apr 21 12:45:15 PM PDT 24 494585273 ps
T915 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4234442231 Apr 21 12:45:27 PM PDT 24 Apr 21 12:45:28 PM PDT 24 539750801 ps
T916 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3233392344 Apr 21 12:44:59 PM PDT 24 Apr 21 12:45:01 PM PDT 24 355642454 ps
T917 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3497551043 Apr 21 12:45:05 PM PDT 24 Apr 21 12:45:09 PM PDT 24 724810984 ps
T918 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3047010095 Apr 21 12:45:17 PM PDT 24 Apr 21 12:45:18 PM PDT 24 363672499 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2345996289 Apr 21 12:45:00 PM PDT 24 Apr 21 12:45:03 PM PDT 24 1245512805 ps

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1580910866
Short name T5
Test name
Test status
Simulation time 345453674595 ps
CPU time 223.94 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 01:59:15 PM PDT 24
Peak memory 202292 kb
Host smart-a9680fbb-64b1-4790-a802-a4d46c716861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580910866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1580910866
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4123672541
Short name T25
Test name
Test status
Simulation time 380638546362 ps
CPU time 729.75 seconds
Started Apr 21 01:52:29 PM PDT 24
Finished Apr 21 02:04:39 PM PDT 24
Peak memory 202616 kb
Host smart-5a5316ce-17b0-42ac-9920-4b39396f4451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123672541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4123672541
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3182094141
Short name T19
Test name
Test status
Simulation time 253982317174 ps
CPU time 499.42 seconds
Started Apr 21 01:53:05 PM PDT 24
Finished Apr 21 02:01:25 PM PDT 24
Peak memory 211232 kb
Host smart-26eeb176-8267-4704-9759-5084854feaa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182094141 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3182094141
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2485602988
Short name T4
Test name
Test status
Simulation time 359175951147 ps
CPU time 629.41 seconds
Started Apr 21 02:00:36 PM PDT 24
Finished Apr 21 02:11:05 PM PDT 24
Peak memory 202268 kb
Host smart-193b5279-605f-488e-a1e9-5afa926026f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485602988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2485602988
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1548118537
Short name T149
Test name
Test status
Simulation time 494369018560 ps
CPU time 279.61 seconds
Started Apr 21 01:59:29 PM PDT 24
Finished Apr 21 02:04:09 PM PDT 24
Peak memory 202292 kb
Host smart-8510bc3d-91c1-46f8-9be5-8c6d3119456d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548118537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1548118537
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1606474583
Short name T175
Test name
Test status
Simulation time 596182628886 ps
CPU time 889.86 seconds
Started Apr 21 01:59:42 PM PDT 24
Finished Apr 21 02:14:32 PM PDT 24
Peak memory 202304 kb
Host smart-e4ea8cba-da6b-43bf-9562-76646538f54c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606474583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1606474583
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3882977228
Short name T15
Test name
Test status
Simulation time 108868620434 ps
CPU time 117.4 seconds
Started Apr 21 01:52:49 PM PDT 24
Finished Apr 21 01:54:47 PM PDT 24
Peak memory 218340 kb
Host smart-b280ef85-9887-48ad-b3e9-0bb04f97a820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882977228 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3882977228
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.773811234
Short name T142
Test name
Test status
Simulation time 561266576263 ps
CPU time 1379.88 seconds
Started Apr 21 01:57:08 PM PDT 24
Finished Apr 21 02:20:09 PM PDT 24
Peak memory 202276 kb
Host smart-30465111-0ebb-4dc8-97c7-a37d25a21491
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773811234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.773811234
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3205490417
Short name T75
Test name
Test status
Simulation time 531463981471 ps
CPU time 1129.04 seconds
Started Apr 21 02:00:01 PM PDT 24
Finished Apr 21 02:18:50 PM PDT 24
Peak memory 202276 kb
Host smart-3f6bb509-57b0-4dd3-96c4-ddb29a5dca17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205490417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3205490417
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1401448662
Short name T45
Test name
Test status
Simulation time 254925228170 ps
CPU time 680.13 seconds
Started Apr 21 01:53:08 PM PDT 24
Finished Apr 21 02:04:28 PM PDT 24
Peak memory 202484 kb
Host smart-760d954f-ee4d-4e20-877b-a5542c0b1c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401448662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1401448662
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3877231678
Short name T210
Test name
Test status
Simulation time 481926092992 ps
CPU time 281.58 seconds
Started Apr 21 01:57:22 PM PDT 24
Finished Apr 21 02:02:04 PM PDT 24
Peak memory 202264 kb
Host smart-a84c111a-f603-4ad1-b96a-73cbc5531438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877231678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3877231678
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1782625022
Short name T55
Test name
Test status
Simulation time 3697987189 ps
CPU time 9.83 seconds
Started Apr 21 01:52:10 PM PDT 24
Finished Apr 21 01:52:20 PM PDT 24
Peak memory 217796 kb
Host smart-4f93d940-6c37-466e-9f2c-34ed0ff994d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782625022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1782625022
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3404192248
Short name T52
Test name
Test status
Simulation time 2050416580 ps
CPU time 2.25 seconds
Started Apr 21 12:45:09 PM PDT 24
Finished Apr 21 12:45:12 PM PDT 24
Peak memory 201360 kb
Host smart-aeaa213a-d767-42f0-a7f9-2637e7358a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404192248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3404192248
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.541057091
Short name T263
Test name
Test status
Simulation time 534700465339 ps
CPU time 529.58 seconds
Started Apr 21 01:58:19 PM PDT 24
Finished Apr 21 02:07:09 PM PDT 24
Peak memory 202252 kb
Host smart-32a53152-b2ad-417d-8559-0feec99b43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541057091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.541057091
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3067758963
Short name T98
Test name
Test status
Simulation time 511402955518 ps
CPU time 603.64 seconds
Started Apr 21 01:59:53 PM PDT 24
Finished Apr 21 02:09:57 PM PDT 24
Peak memory 202252 kb
Host smart-12ac5f0f-4fa7-4664-9371-0bae7974eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067758963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3067758963
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2639320009
Short name T8
Test name
Test status
Simulation time 165240349516 ps
CPU time 390.97 seconds
Started Apr 21 01:56:49 PM PDT 24
Finished Apr 21 02:03:20 PM PDT 24
Peak memory 202184 kb
Host smart-a6b5fca9-7e82-4fb1-9d99-a97259a8ef56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639320009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2639320009
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1842989456
Short name T270
Test name
Test status
Simulation time 349831149819 ps
CPU time 217.65 seconds
Started Apr 21 01:55:48 PM PDT 24
Finished Apr 21 01:59:26 PM PDT 24
Peak memory 202272 kb
Host smart-8a659454-193a-44cc-a490-dc70cd15ccd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842989456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1842989456
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2792308438
Short name T250
Test name
Test status
Simulation time 333879276122 ps
CPU time 371.4 seconds
Started Apr 21 01:59:26 PM PDT 24
Finished Apr 21 02:05:38 PM PDT 24
Peak memory 202348 kb
Host smart-a7ca7277-849e-40b2-8421-24db5d536ae0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792308438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2792308438
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3934663952
Short name T112
Test name
Test status
Simulation time 1074685287 ps
CPU time 5.58 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:45:02 PM PDT 24
Peak memory 201224 kb
Host smart-7c0b7ed5-af9e-4877-a8c0-e208479ed84f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934663952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3934663952
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3886663847
Short name T141
Test name
Test status
Simulation time 528169853441 ps
CPU time 561.7 seconds
Started Apr 21 01:59:04 PM PDT 24
Finished Apr 21 02:08:26 PM PDT 24
Peak memory 202260 kb
Host smart-00070aef-8536-40ee-90fb-576d51bdea7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886663847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3886663847
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.48816007
Short name T198
Test name
Test status
Simulation time 332436447672 ps
CPU time 123.49 seconds
Started Apr 21 01:57:15 PM PDT 24
Finished Apr 21 01:59:19 PM PDT 24
Peak memory 202240 kb
Host smart-c2957618-067f-4730-8f0d-7fba2c72920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48816007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.48816007
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1662211585
Short name T92
Test name
Test status
Simulation time 445655133485 ps
CPU time 1079.89 seconds
Started Apr 21 01:59:11 PM PDT 24
Finished Apr 21 02:17:11 PM PDT 24
Peak memory 202260 kb
Host smart-c5a9f229-cb90-4ff6-a175-3e901e6e1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662211585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1662211585
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2801386439
Short name T162
Test name
Test status
Simulation time 490282917828 ps
CPU time 163.71 seconds
Started Apr 21 01:54:16 PM PDT 24
Finished Apr 21 01:57:00 PM PDT 24
Peak memory 202236 kb
Host smart-e088bc76-f89f-4f98-87dc-a23f047ebb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801386439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2801386439
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.511294370
Short name T137
Test name
Test status
Simulation time 488935522792 ps
CPU time 1114.77 seconds
Started Apr 21 01:55:54 PM PDT 24
Finished Apr 21 02:14:29 PM PDT 24
Peak memory 202384 kb
Host smart-0e2b8ab0-0b29-4971-8dbb-631c4a5598bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511294370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.511294370
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1389824794
Short name T256
Test name
Test status
Simulation time 521345280948 ps
CPU time 1257.56 seconds
Started Apr 21 01:59:45 PM PDT 24
Finished Apr 21 02:20:43 PM PDT 24
Peak memory 202248 kb
Host smart-f25ded0d-5b6a-4c94-8913-53f2e5e1ac27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389824794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1389824794
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.714310809
Short name T163
Test name
Test status
Simulation time 354180995025 ps
CPU time 64.32 seconds
Started Apr 21 01:58:02 PM PDT 24
Finished Apr 21 01:59:07 PM PDT 24
Peak memory 202276 kb
Host smart-831be7df-53b7-4b93-80a4-638092e87947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714310809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.714310809
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3079137648
Short name T215
Test name
Test status
Simulation time 353512093727 ps
CPU time 845.7 seconds
Started Apr 21 01:56:35 PM PDT 24
Finished Apr 21 02:10:41 PM PDT 24
Peak memory 202324 kb
Host smart-b48d8572-5cc8-4189-bda5-cc9b634b6cd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079137648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3079137648
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1861025116
Short name T296
Test name
Test status
Simulation time 157355462349 ps
CPU time 357.59 seconds
Started Apr 21 01:52:47 PM PDT 24
Finished Apr 21 01:58:45 PM PDT 24
Peak memory 202264 kb
Host smart-50818f39-f1b2-4f11-879d-bfeb983adab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861025116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1861025116
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1652369266
Short name T307
Test name
Test status
Simulation time 336535006486 ps
CPU time 215.81 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 01:59:49 PM PDT 24
Peak memory 202220 kb
Host smart-50bdec9a-d0f0-48ce-9a1e-190c26192b82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652369266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1652369266
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4048903274
Short name T242
Test name
Test status
Simulation time 324164525388 ps
CPU time 371.66 seconds
Started Apr 21 01:56:40 PM PDT 24
Finished Apr 21 02:02:52 PM PDT 24
Peak memory 202268 kb
Host smart-a245dd85-9a45-4944-82ec-09e36884b817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048903274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4048903274
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3613043857
Short name T31
Test name
Test status
Simulation time 287470396 ps
CPU time 1.23 seconds
Started Apr 21 01:55:41 PM PDT 24
Finished Apr 21 01:55:43 PM PDT 24
Peak memory 201984 kb
Host smart-d4b2363c-006f-492d-9b52-18e3a8d72227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613043857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3613043857
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1749355923
Short name T65
Test name
Test status
Simulation time 4567432179 ps
CPU time 2.36 seconds
Started Apr 21 12:45:13 PM PDT 24
Finished Apr 21 12:45:16 PM PDT 24
Peak memory 201500 kb
Host smart-82d03c43-13bc-4ff6-ab13-e028341c4f21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749355923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1749355923
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3963689913
Short name T165
Test name
Test status
Simulation time 864459292853 ps
CPU time 1050.52 seconds
Started Apr 21 01:58:06 PM PDT 24
Finished Apr 21 02:15:36 PM PDT 24
Peak memory 210836 kb
Host smart-ef066afa-b17b-44b2-989a-a9a6b09239dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963689913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3963689913
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3443409206
Short name T16
Test name
Test status
Simulation time 232215740260 ps
CPU time 83.53 seconds
Started Apr 21 01:52:11 PM PDT 24
Finished Apr 21 01:53:35 PM PDT 24
Peak memory 210656 kb
Host smart-b460992c-1710-4d83-848d-668ba09c341a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443409206 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3443409206
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3504665797
Short name T269
Test name
Test status
Simulation time 508121228932 ps
CPU time 1236.11 seconds
Started Apr 21 01:52:07 PM PDT 24
Finished Apr 21 02:12:44 PM PDT 24
Peak memory 202272 kb
Host smart-aa144bbc-85f1-4759-9915-a6dccdf3d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504665797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3504665797
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1880644494
Short name T309
Test name
Test status
Simulation time 525740982101 ps
CPU time 1202.46 seconds
Started Apr 21 01:56:27 PM PDT 24
Finished Apr 21 02:16:30 PM PDT 24
Peak memory 202328 kb
Host smart-9a1f7187-1af7-4550-a700-4dd33078b545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880644494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1880644494
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3572200539
Short name T24
Test name
Test status
Simulation time 395852454585 ps
CPU time 212.14 seconds
Started Apr 21 01:57:37 PM PDT 24
Finished Apr 21 02:01:10 PM PDT 24
Peak memory 202212 kb
Host smart-41dce2aa-36a7-487b-928e-6e50145d18de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572200539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3572200539
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.429986775
Short name T336
Test name
Test status
Simulation time 323662923271 ps
CPU time 220.31 seconds
Started Apr 21 02:00:52 PM PDT 24
Finished Apr 21 02:04:33 PM PDT 24
Peak memory 202272 kb
Host smart-60035a54-843d-4e17-8d16-2925c911fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429986775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.429986775
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4171879867
Short name T191
Test name
Test status
Simulation time 605918129969 ps
CPU time 140.94 seconds
Started Apr 21 01:56:52 PM PDT 24
Finished Apr 21 01:59:13 PM PDT 24
Peak memory 202268 kb
Host smart-1aec4fb0-736d-4306-89c0-f5bc75148549
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171879867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4171879867
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2086190228
Short name T313
Test name
Test status
Simulation time 575016973087 ps
CPU time 662.74 seconds
Started Apr 21 01:55:51 PM PDT 24
Finished Apr 21 02:06:55 PM PDT 24
Peak memory 210932 kb
Host smart-f94bc94f-8727-46f6-aee1-8d63a381ebad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086190228 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2086190228
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.909221242
Short name T221
Test name
Test status
Simulation time 490442448628 ps
CPU time 211.82 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 01:59:45 PM PDT 24
Peak memory 202304 kb
Host smart-cc20a089-2835-4166-ab3d-0573dcab1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909221242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.909221242
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.214808726
Short name T283
Test name
Test status
Simulation time 492778488435 ps
CPU time 233.25 seconds
Started Apr 21 01:56:25 PM PDT 24
Finished Apr 21 02:00:18 PM PDT 24
Peak memory 202240 kb
Host smart-719bb73d-60ac-41e8-8051-1a48b2976e91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214808726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.214808726
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.724578378
Short name T339
Test name
Test status
Simulation time 27504291155 ps
CPU time 87.2 seconds
Started Apr 21 01:57:44 PM PDT 24
Finished Apr 21 01:59:12 PM PDT 24
Peak memory 210876 kb
Host smart-bf1d6615-6a96-488c-b95f-b4b05dc5ff91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724578378 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.724578378
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.717317745
Short name T340
Test name
Test status
Simulation time 494700146421 ps
CPU time 307.29 seconds
Started Apr 21 01:59:15 PM PDT 24
Finished Apr 21 02:04:23 PM PDT 24
Peak memory 202276 kb
Host smart-602f454a-2254-49d7-bd11-fadacf794879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717317745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.717317745
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3680111676
Short name T155
Test name
Test status
Simulation time 337063127167 ps
CPU time 630.04 seconds
Started Apr 21 01:55:56 PM PDT 24
Finished Apr 21 02:06:26 PM PDT 24
Peak memory 202260 kb
Host smart-96bff199-9b67-417d-8191-3c24c5d209e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680111676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3680111676
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3627938004
Short name T305
Test name
Test status
Simulation time 391323889480 ps
CPU time 229.42 seconds
Started Apr 21 01:57:52 PM PDT 24
Finished Apr 21 02:01:42 PM PDT 24
Peak memory 202276 kb
Host smart-bd9c48bc-1d37-4e86-b575-6d5c50a85a9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627938004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3627938004
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3839705044
Short name T192
Test name
Test status
Simulation time 498899029362 ps
CPU time 69.44 seconds
Started Apr 21 01:58:54 PM PDT 24
Finished Apr 21 02:00:04 PM PDT 24
Peak memory 202272 kb
Host smart-4a06588f-000e-40e8-9d2d-05e7332d8aea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839705044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3839705044
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3641903791
Short name T124
Test name
Test status
Simulation time 501138838 ps
CPU time 0.77 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:12 PM PDT 24
Peak memory 201276 kb
Host smart-d98f43b8-f315-4899-8c8e-032d6afe1947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641903791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3641903791
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3982579772
Short name T23
Test name
Test status
Simulation time 38749577623 ps
CPU time 181.13 seconds
Started Apr 21 01:55:25 PM PDT 24
Finished Apr 21 01:58:26 PM PDT 24
Peak memory 210964 kb
Host smart-374fba50-a803-44c9-bbbc-be55619a4bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982579772 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3982579772
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3039269168
Short name T355
Test name
Test status
Simulation time 160550473316 ps
CPU time 84.64 seconds
Started Apr 21 01:56:06 PM PDT 24
Finished Apr 21 01:57:31 PM PDT 24
Peak memory 202224 kb
Host smart-15c3249a-4a7b-438b-82aa-580b9029a516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039269168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3039269168
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1528804747
Short name T79
Test name
Test status
Simulation time 168125785306 ps
CPU time 307.33 seconds
Started Apr 21 01:57:27 PM PDT 24
Finished Apr 21 02:02:34 PM PDT 24
Peak memory 211112 kb
Host smart-0d97b1d7-8deb-4d8c-899a-c7349a0de02d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528804747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1528804747
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3037976342
Short name T320
Test name
Test status
Simulation time 327017782383 ps
CPU time 729.33 seconds
Started Apr 21 01:57:04 PM PDT 24
Finished Apr 21 02:09:13 PM PDT 24
Peak memory 202248 kb
Host smart-f3bf3b61-b55c-41a9-a3c8-97fb8a1b2b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037976342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3037976342
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2445854400
Short name T231
Test name
Test status
Simulation time 102543641022 ps
CPU time 414.19 seconds
Started Apr 21 02:01:16 PM PDT 24
Finished Apr 21 02:08:11 PM PDT 24
Peak memory 202616 kb
Host smart-f245797b-508b-4cac-9247-a8a870e74aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445854400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2445854400
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2155263805
Short name T262
Test name
Test status
Simulation time 545693868183 ps
CPU time 164.38 seconds
Started Apr 21 01:55:14 PM PDT 24
Finished Apr 21 01:57:59 PM PDT 24
Peak memory 202372 kb
Host smart-7c143aed-498f-465b-bfd2-21fd8afa99fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155263805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2155263805
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.273793668
Short name T299
Test name
Test status
Simulation time 637539016421 ps
CPU time 694.07 seconds
Started Apr 21 01:56:35 PM PDT 24
Finished Apr 21 02:08:10 PM PDT 24
Peak memory 202276 kb
Host smart-05ab1f27-53ae-401f-b62d-ac3fb8b0df44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273793668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.273793668
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.21391708
Short name T290
Test name
Test status
Simulation time 169876923884 ps
CPU time 179.24 seconds
Started Apr 21 01:59:53 PM PDT 24
Finished Apr 21 02:02:52 PM PDT 24
Peak memory 202240 kb
Host smart-c26c7f78-0d0f-4753-843b-46cb1b6c920f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21391708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gatin
g.21391708
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2108775976
Short name T258
Test name
Test status
Simulation time 164726017138 ps
CPU time 71.07 seconds
Started Apr 21 02:00:18 PM PDT 24
Finished Apr 21 02:01:29 PM PDT 24
Peak memory 202264 kb
Host smart-f1ef181e-e7ed-499f-bfd3-f0643304aaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108775976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2108775976
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3896840743
Short name T333
Test name
Test status
Simulation time 543128714628 ps
CPU time 1268.45 seconds
Started Apr 21 01:52:07 PM PDT 24
Finished Apr 21 02:13:16 PM PDT 24
Peak memory 202272 kb
Host smart-8907665e-52e6-4218-aefe-4c5438b7ad01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896840743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3896840743
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1756948134
Short name T315
Test name
Test status
Simulation time 330806279201 ps
CPU time 389.36 seconds
Started Apr 21 01:55:28 PM PDT 24
Finished Apr 21 02:01:57 PM PDT 24
Peak memory 202232 kb
Host smart-53589958-c8ef-4a66-ada2-366b63af0d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756948134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1756948134
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.565843833
Short name T168
Test name
Test status
Simulation time 517565617763 ps
CPU time 144.11 seconds
Started Apr 21 01:55:55 PM PDT 24
Finished Apr 21 01:58:19 PM PDT 24
Peak memory 202268 kb
Host smart-5af3ce88-7851-4af1-a2c9-f76b42711f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565843833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.565843833
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1168758964
Short name T345
Test name
Test status
Simulation time 341066484490 ps
CPU time 400.9 seconds
Started Apr 21 01:56:24 PM PDT 24
Finished Apr 21 02:03:06 PM PDT 24
Peak memory 202356 kb
Host smart-67c5ee4f-b239-4cc1-a1f3-2b664c5f0f0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168758964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1168758964
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3304724273
Short name T344
Test name
Test status
Simulation time 20079279647 ps
CPU time 74.2 seconds
Started Apr 21 01:52:30 PM PDT 24
Finished Apr 21 01:53:45 PM PDT 24
Peak memory 210876 kb
Host smart-37d3ccd1-df31-486c-97b0-4b6c37a77064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304724273 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3304724273
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1623018478
Short name T265
Test name
Test status
Simulation time 350745737570 ps
CPU time 829.41 seconds
Started Apr 21 01:57:52 PM PDT 24
Finished Apr 21 02:11:42 PM PDT 24
Peak memory 202252 kb
Host smart-f825f134-fec0-46d4-a836-5cddff6891e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623018478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1623018478
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3390801837
Short name T240
Test name
Test status
Simulation time 370447199015 ps
CPU time 878.96 seconds
Started Apr 21 01:58:01 PM PDT 24
Finished Apr 21 02:12:40 PM PDT 24
Peak memory 202300 kb
Host smart-e8d3202b-870a-46e2-99ae-3e059671f489
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390801837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3390801837
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1216499647
Short name T95
Test name
Test status
Simulation time 158936918835 ps
CPU time 556.37 seconds
Started Apr 21 02:00:51 PM PDT 24
Finished Apr 21 02:10:07 PM PDT 24
Peak memory 210768 kb
Host smart-d890e81e-c9e1-4add-80a7-f0d69b12a8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216499647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1216499647
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1717322719
Short name T311
Test name
Test status
Simulation time 349466085598 ps
CPU time 211.33 seconds
Started Apr 21 01:53:14 PM PDT 24
Finished Apr 21 01:56:45 PM PDT 24
Peak memory 202352 kb
Host smart-d6de51de-97ce-4835-881d-9ce0be519a19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717322719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1717322719
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1561607754
Short name T246
Test name
Test status
Simulation time 346131122683 ps
CPU time 444.46 seconds
Started Apr 21 01:54:10 PM PDT 24
Finished Apr 21 02:01:35 PM PDT 24
Peak memory 202300 kb
Host smart-af61df58-6ad4-4af9-be7b-f229583e21a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561607754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1561607754
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.280603851
Short name T267
Test name
Test status
Simulation time 509885853766 ps
CPU time 313.03 seconds
Started Apr 21 01:56:09 PM PDT 24
Finished Apr 21 02:01:22 PM PDT 24
Peak memory 202268 kb
Host smart-a056a52f-e3e9-4758-85cc-34d4d8e95bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280603851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.280603851
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2019755256
Short name T101
Test name
Test status
Simulation time 106836179903 ps
CPU time 459.13 seconds
Started Apr 21 01:56:20 PM PDT 24
Finished Apr 21 02:04:00 PM PDT 24
Peak memory 202632 kb
Host smart-d3ba9ad2-029f-4df1-bee9-f56646de5ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019755256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2019755256
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.663427214
Short name T136
Test name
Test status
Simulation time 543708782667 ps
CPU time 302.71 seconds
Started Apr 21 01:59:51 PM PDT 24
Finished Apr 21 02:04:54 PM PDT 24
Peak memory 202268 kb
Host smart-c2cd8354-d833-43bb-903d-a26f3826ab38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663427214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.663427214
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.878130085
Short name T303
Test name
Test status
Simulation time 166599242577 ps
CPU time 379.14 seconds
Started Apr 21 02:00:19 PM PDT 24
Finished Apr 21 02:06:38 PM PDT 24
Peak memory 202296 kb
Host smart-5421c6d0-5e90-41d8-b904-6f68b82a9b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878130085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
878130085
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1270862915
Short name T324
Test name
Test status
Simulation time 164327916871 ps
CPU time 184.57 seconds
Started Apr 21 01:53:11 PM PDT 24
Finished Apr 21 01:56:15 PM PDT 24
Peak memory 202340 kb
Host smart-4177d518-c736-4157-9902-fbc761b399fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270862915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1270862915
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3333036313
Short name T818
Test name
Test status
Simulation time 448577846 ps
CPU time 2.88 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:45:00 PM PDT 24
Peak memory 201472 kb
Host smart-4e240425-957f-4100-9a3d-9ba64326e3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333036313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3333036313
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.837476467
Short name T370
Test name
Test status
Simulation time 8527325504 ps
CPU time 7.57 seconds
Started Apr 21 12:44:52 PM PDT 24
Finished Apr 21 12:45:00 PM PDT 24
Peak memory 201460 kb
Host smart-faea39bd-c58f-480a-a303-977cf5a1c6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837476467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.837476467
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1748684058
Short name T152
Test name
Test status
Simulation time 167658641582 ps
CPU time 173.25 seconds
Started Apr 21 01:55:25 PM PDT 24
Finished Apr 21 01:58:18 PM PDT 24
Peak memory 202292 kb
Host smart-fe776aa5-73f4-4e60-9313-f1cdaaac7810
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748684058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1748684058
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2657645088
Short name T229
Test name
Test status
Simulation time 121395006578 ps
CPU time 378.09 seconds
Started Apr 21 01:55:37 PM PDT 24
Finished Apr 21 02:01:55 PM PDT 24
Peak memory 202680 kb
Host smart-8803dd5a-62e4-43f4-87da-51b2d4138f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657645088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2657645088
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4092476742
Short name T140
Test name
Test status
Simulation time 516694627327 ps
CPU time 604.72 seconds
Started Apr 21 01:55:54 PM PDT 24
Finished Apr 21 02:05:59 PM PDT 24
Peak memory 202536 kb
Host smart-b7cb54cb-6f2f-4efa-9ade-9ce995330dc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092476742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4092476742
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.654042038
Short name T201
Test name
Test status
Simulation time 116821968158 ps
CPU time 476.42 seconds
Started Apr 21 01:56:04 PM PDT 24
Finished Apr 21 02:04:01 PM PDT 24
Peak memory 202608 kb
Host smart-d40ba9cd-67e5-4748-ab4a-1dacc8d56957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654042038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.654042038
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3420360662
Short name T284
Test name
Test status
Simulation time 294893733023 ps
CPU time 139.3 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 01:58:32 PM PDT 24
Peak memory 210576 kb
Host smart-81a1a98f-2512-49db-a090-ffba60b0b357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420360662 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3420360662
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1006198521
Short name T282
Test name
Test status
Simulation time 417893526124 ps
CPU time 908.72 seconds
Started Apr 21 01:52:15 PM PDT 24
Finished Apr 21 02:07:24 PM PDT 24
Peak memory 202368 kb
Host smart-2883bf47-03ee-4e76-9995-05445483ff4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006198521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1006198521
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1557545155
Short name T179
Test name
Test status
Simulation time 554293753155 ps
CPU time 331.14 seconds
Started Apr 21 01:56:16 PM PDT 24
Finished Apr 21 02:01:47 PM PDT 24
Peak memory 202324 kb
Host smart-c26c255f-bb3d-48dc-9a07-6558cd25eefc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557545155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1557545155
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2870639191
Short name T373
Test name
Test status
Simulation time 75457709943 ps
CPU time 196.68 seconds
Started Apr 21 01:56:39 PM PDT 24
Finished Apr 21 01:59:56 PM PDT 24
Peak memory 202572 kb
Host smart-5e6c720e-bff4-420e-9c7d-737eb86e52ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870639191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2870639191
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3898367589
Short name T343
Test name
Test status
Simulation time 326706679818 ps
CPU time 184.57 seconds
Started Apr 21 01:54:08 PM PDT 24
Finished Apr 21 01:57:12 PM PDT 24
Peak memory 202264 kb
Host smart-87b30c57-bddc-4b0b-bed7-041ca9df3cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898367589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3898367589
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.374773673
Short name T911
Test name
Test status
Simulation time 667400217 ps
CPU time 2.96 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:05 PM PDT 24
Peak memory 200892 kb
Host smart-eb920941-bc30-45ae-96ad-4258ea76dd01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374773673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.374773673
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.833041613
Short name T131
Test name
Test status
Simulation time 800469404 ps
CPU time 1.23 seconds
Started Apr 21 12:44:55 PM PDT 24
Finished Apr 21 12:44:56 PM PDT 24
Peak memory 201216 kb
Host smart-41f7ff28-a151-4fc8-8c61-efac8631e00d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833041613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.833041613
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1311894587
Short name T873
Test name
Test status
Simulation time 461140631 ps
CPU time 1.81 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:44:58 PM PDT 24
Peak memory 201256 kb
Host smart-f0620e4a-dab0-4ed8-a472-5b36bb811fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311894587 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1311894587
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3769481062
Short name T847
Test name
Test status
Simulation time 294273124 ps
CPU time 1.27 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 201124 kb
Host smart-e57750dc-2eb4-422b-8381-6bab79890ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769481062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3769481062
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2495286747
Short name T46
Test name
Test status
Simulation time 4682303676 ps
CPU time 11.76 seconds
Started Apr 21 12:45:09 PM PDT 24
Finished Apr 21 12:45:22 PM PDT 24
Peak memory 201464 kb
Host smart-f030a19e-589e-42ed-8b7a-1fd0eaf4c434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495286747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2495286747
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2443229580
Short name T368
Test name
Test status
Simulation time 4482128049 ps
CPU time 11.76 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:13 PM PDT 24
Peak memory 201400 kb
Host smart-37f158dd-fe4c-4267-85a8-2d9698d6dd6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443229580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2443229580
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3807608992
Short name T870
Test name
Test status
Simulation time 1415168174 ps
CPU time 2.94 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201328 kb
Host smart-2b5f2620-7459-4b50-acc5-b413bba79bc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807608992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3807608992
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.366886603
Short name T48
Test name
Test status
Simulation time 26737001736 ps
CPU time 20.45 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:22 PM PDT 24
Peak memory 201528 kb
Host smart-90510cff-f6fd-46ae-98c8-65c82a51651f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366886603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.366886603
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2345996289
Short name T919
Test name
Test status
Simulation time 1245512805 ps
CPU time 1.53 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:03 PM PDT 24
Peak memory 201104 kb
Host smart-f17042b1-0440-4540-9ab4-7c8ee70bfe78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345996289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2345996289
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3116752893
Short name T819
Test name
Test status
Simulation time 534929592 ps
CPU time 2.32 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201276 kb
Host smart-2764ee03-8b3e-46cb-b1a3-9b1b95945953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116752893 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3116752893
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4197902240
Short name T123
Test name
Test status
Simulation time 512378178 ps
CPU time 2.07 seconds
Started Apr 21 12:45:06 PM PDT 24
Finished Apr 21 12:45:09 PM PDT 24
Peak memory 201220 kb
Host smart-b3dd14e0-2ca5-4b48-8505-bca26085f11a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197902240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4197902240
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2573085828
Short name T882
Test name
Test status
Simulation time 511336851 ps
CPU time 1.08 seconds
Started Apr 21 12:45:02 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 201216 kb
Host smart-4f39706e-993a-4b76-a47b-a3d13573b7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573085828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2573085828
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3897503899
Short name T852
Test name
Test status
Simulation time 2782615827 ps
CPU time 7.36 seconds
Started Apr 21 12:44:49 PM PDT 24
Finished Apr 21 12:44:57 PM PDT 24
Peak memory 201268 kb
Host smart-d0adf74a-9fdb-49fd-b5d3-b632d7ce29f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897503899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3897503899
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3640433068
Short name T827
Test name
Test status
Simulation time 483800557 ps
CPU time 2.95 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201376 kb
Host smart-e47d8fb7-4cf1-490e-ac67-fbbb0138a786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640433068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3640433068
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2084409524
Short name T67
Test name
Test status
Simulation time 8196729356 ps
CPU time 19.99 seconds
Started Apr 21 12:44:52 PM PDT 24
Finished Apr 21 12:45:12 PM PDT 24
Peak memory 201460 kb
Host smart-5b09a59e-3dec-4983-bfe9-c7289a8d7a5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084409524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2084409524
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1723354288
Short name T91
Test name
Test status
Simulation time 411844919 ps
CPU time 1.01 seconds
Started Apr 21 12:44:55 PM PDT 24
Finished Apr 21 12:44:57 PM PDT 24
Peak memory 201304 kb
Host smart-7bcd74a5-0b4c-4d53-b5e6-d016a9353e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723354288 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1723354288
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.160249332
Short name T127
Test name
Test status
Simulation time 569358280 ps
CPU time 0.97 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 201212 kb
Host smart-cd598a40-2cf9-4bd0-a83f-f9de9eb541ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160249332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.160249332
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2112107257
Short name T805
Test name
Test status
Simulation time 403769164 ps
CPU time 0.96 seconds
Started Apr 21 12:45:17 PM PDT 24
Finished Apr 21 12:45:19 PM PDT 24
Peak memory 201136 kb
Host smart-d40882f5-b85f-4bde-9ed2-46ea4ec97713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112107257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2112107257
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.615476384
Short name T849
Test name
Test status
Simulation time 2611795940 ps
CPU time 11.61 seconds
Started Apr 21 12:45:38 PM PDT 24
Finished Apr 21 12:45:51 PM PDT 24
Peak memory 201180 kb
Host smart-132665b3-f95a-4653-a8d4-ef9c8884c734
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615476384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.615476384
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3497551043
Short name T917
Test name
Test status
Simulation time 724810984 ps
CPU time 2.93 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:09 PM PDT 24
Peak memory 201488 kb
Host smart-81a2a8b1-aabe-4fb6-9f1f-08a37037d1c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497551043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3497551043
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1260554875
Short name T862
Test name
Test status
Simulation time 328521280 ps
CPU time 1.55 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201284 kb
Host smart-7e3ecd99-96d9-4f97-8bef-a5e7b3011408
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260554875 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1260554875
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4247835588
Short name T834
Test name
Test status
Simulation time 553316731 ps
CPU time 0.95 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:12 PM PDT 24
Peak memory 201252 kb
Host smart-665e3a30-99dd-46ae-879c-13ae20864b14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247835588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4247835588
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3047010095
Short name T918
Test name
Test status
Simulation time 363672499 ps
CPU time 0.72 seconds
Started Apr 21 12:45:17 PM PDT 24
Finished Apr 21 12:45:18 PM PDT 24
Peak memory 201204 kb
Host smart-48e0f853-14c6-46ce-b7ed-b63890900964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047010095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3047010095
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.695401649
Short name T126
Test name
Test status
Simulation time 2744205689 ps
CPU time 2.3 seconds
Started Apr 21 12:44:55 PM PDT 24
Finished Apr 21 12:44:57 PM PDT 24
Peak memory 201272 kb
Host smart-7c9a8e05-454d-4ebd-a336-768850fbee7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695401649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.695401649
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.453934051
Short name T883
Test name
Test status
Simulation time 531636748 ps
CPU time 2.69 seconds
Started Apr 21 12:45:03 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201436 kb
Host smart-43bcca78-3272-41eb-b430-9e68d7823e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453934051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.453934051
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3461819979
Short name T823
Test name
Test status
Simulation time 8809902058 ps
CPU time 9.94 seconds
Started Apr 21 12:45:24 PM PDT 24
Finished Apr 21 12:45:34 PM PDT 24
Peak memory 201480 kb
Host smart-042f31d7-d365-44b6-87cf-863af501cf60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461819979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3461819979
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2998873387
Short name T875
Test name
Test status
Simulation time 449030023 ps
CPU time 1.5 seconds
Started Apr 21 12:44:53 PM PDT 24
Finished Apr 21 12:44:55 PM PDT 24
Peak memory 201188 kb
Host smart-c1bbd3a3-8781-4c5b-ab39-28b3dd082964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998873387 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2998873387
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3661454782
Short name T121
Test name
Test status
Simulation time 328448588 ps
CPU time 1.45 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201128 kb
Host smart-0aef3b57-bb73-4c72-bdde-4e07c4761564
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661454782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3661454782
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2247285024
Short name T812
Test name
Test status
Simulation time 299089317 ps
CPU time 1.04 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:02 PM PDT 24
Peak memory 201228 kb
Host smart-0a8970cb-7cae-4ebe-8650-16444ac1b000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247285024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2247285024
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.821464384
Short name T844
Test name
Test status
Simulation time 2554174076 ps
CPU time 3.63 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201276 kb
Host smart-ee9d90fb-5631-4ef0-b15a-c6825ba9fbe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821464384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.821464384
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3139526791
Short name T856
Test name
Test status
Simulation time 584349262 ps
CPU time 3.72 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:09 PM PDT 24
Peak memory 201452 kb
Host smart-e5136296-a31d-4c43-b7b5-cedc8daccebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139526791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3139526791
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1733849621
Short name T846
Test name
Test status
Simulation time 4320381943 ps
CPU time 3.85 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201396 kb
Host smart-e947a6a2-e7f9-4ce3-9255-668ed4f26833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733849621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1733849621
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2056433854
Short name T81
Test name
Test status
Simulation time 453606544 ps
CPU time 1.21 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201308 kb
Host smart-f99fb5c7-8fa2-41ff-92b9-8436d05018c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056433854 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2056433854
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1033499991
Short name T114
Test name
Test status
Simulation time 379172212 ps
CPU time 1.18 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201120 kb
Host smart-6870cdf0-0541-41d4-be0b-a9c6ed094b16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033499991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1033499991
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1900802947
Short name T845
Test name
Test status
Simulation time 537342019 ps
CPU time 1.25 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 201276 kb
Host smart-b606925b-f848-4972-a0ab-e38ceea7a47d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900802947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1900802947
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1221993671
Short name T874
Test name
Test status
Simulation time 4545131803 ps
CPU time 5.91 seconds
Started Apr 21 12:45:18 PM PDT 24
Finished Apr 21 12:45:25 PM PDT 24
Peak memory 201368 kb
Host smart-9190291c-0344-414e-be72-c08bd1569e86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221993671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1221993671
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.262449345
Short name T851
Test name
Test status
Simulation time 463176061 ps
CPU time 3.36 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201384 kb
Host smart-efefbe19-7118-4d22-ab1f-df4ebb0a6c41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262449345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.262449345
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3499868761
Short name T66
Test name
Test status
Simulation time 8420783616 ps
CPU time 5.78 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:19 PM PDT 24
Peak memory 201368 kb
Host smart-36c80c41-8672-4897-91b1-8dd1f7bec643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499868761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3499868761
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.655669125
Short name T905
Test name
Test status
Simulation time 458515713 ps
CPU time 1.94 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:02 PM PDT 24
Peak memory 201164 kb
Host smart-decd060d-20dd-4634-aaed-5755ed2f18ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655669125 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.655669125
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.210926943
Short name T867
Test name
Test status
Simulation time 430049681 ps
CPU time 1.75 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201244 kb
Host smart-99079bbe-d0ce-479e-a648-d0d7d17e50a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210926943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.210926943
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3645012642
Short name T907
Test name
Test status
Simulation time 483592459 ps
CPU time 1.2 seconds
Started Apr 21 12:45:06 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201204 kb
Host smart-106b3e59-da5b-4b71-b34b-5269175072c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645012642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3645012642
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1637825278
Short name T876
Test name
Test status
Simulation time 1784424553 ps
CPU time 1.79 seconds
Started Apr 21 12:44:53 PM PDT 24
Finished Apr 21 12:44:55 PM PDT 24
Peak memory 201220 kb
Host smart-5f4a3455-b997-444d-84b7-9251cce960af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637825278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1637825278
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.322206364
Short name T817
Test name
Test status
Simulation time 530887884 ps
CPU time 2.97 seconds
Started Apr 21 12:45:09 PM PDT 24
Finished Apr 21 12:45:13 PM PDT 24
Peak memory 201500 kb
Host smart-70370270-a13b-4a5f-b913-1e4531276bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322206364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.322206364
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2734123573
Short name T51
Test name
Test status
Simulation time 4583257196 ps
CPU time 12.78 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:21 PM PDT 24
Peak memory 201372 kb
Host smart-73cb0f61-c399-4174-8983-cd87d1deb2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734123573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2734123573
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2711722852
Short name T826
Test name
Test status
Simulation time 378972061 ps
CPU time 1.14 seconds
Started Apr 21 12:45:16 PM PDT 24
Finished Apr 21 12:45:18 PM PDT 24
Peak memory 201276 kb
Host smart-3301dfc9-825d-40d7-af80-187e51ac4d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711722852 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2711722852
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3260709619
Short name T832
Test name
Test status
Simulation time 429824712 ps
CPU time 1.73 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201244 kb
Host smart-e4e604f5-8083-463b-81ca-8cade49c5cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260709619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3260709619
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1250894962
Short name T825
Test name
Test status
Simulation time 335892859 ps
CPU time 0.85 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201112 kb
Host smart-918d0720-9fb6-479f-8f56-d943d453e70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250894962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1250894962
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.986408309
Short name T888
Test name
Test status
Simulation time 4222652304 ps
CPU time 2.02 seconds
Started Apr 21 12:45:20 PM PDT 24
Finished Apr 21 12:45:22 PM PDT 24
Peak memory 201424 kb
Host smart-83b2122b-a876-4c62-a0cd-4c71c7289716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986408309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.986408309
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.863941680
Short name T59
Test name
Test status
Simulation time 440894118 ps
CPU time 3.61 seconds
Started Apr 21 12:45:17 PM PDT 24
Finished Apr 21 12:45:22 PM PDT 24
Peak memory 201456 kb
Host smart-f4715d24-2331-4b02-ae22-cda0096d58a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863941680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.863941680
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.320518229
Short name T49
Test name
Test status
Simulation time 6044951416 ps
CPU time 2.22 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201484 kb
Host smart-c1f70a5c-a8e4-4b3a-bc8e-e554111bc764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320518229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.320518229
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2371241392
Short name T64
Test name
Test status
Simulation time 574614292 ps
CPU time 1.83 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201256 kb
Host smart-feca3976-0ebf-4e88-868b-b646e9d82224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371241392 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2371241392
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3852565287
Short name T113
Test name
Test status
Simulation time 459575999 ps
CPU time 1.8 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:44:58 PM PDT 24
Peak memory 201116 kb
Host smart-46987250-0793-48ab-ab07-f30e942ee72c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852565287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3852565287
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.544722149
Short name T822
Test name
Test status
Simulation time 328365220 ps
CPU time 1.38 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:02 PM PDT 24
Peak memory 201232 kb
Host smart-9ac54cb1-56f7-4cac-9394-2e0fac7c5422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544722149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.544722149
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3505356061
Short name T894
Test name
Test status
Simulation time 2401695635 ps
CPU time 3 seconds
Started Apr 21 12:45:17 PM PDT 24
Finished Apr 21 12:45:21 PM PDT 24
Peak memory 201292 kb
Host smart-b4359746-15ce-4899-8d7a-dc2ac9403fa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505356061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3505356061
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.503883441
Short name T831
Test name
Test status
Simulation time 633817674 ps
CPU time 3.97 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 217084 kb
Host smart-3407cf4b-5517-479e-89f7-79cda849c4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503883441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.503883441
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.663265621
Short name T891
Test name
Test status
Simulation time 4346685011 ps
CPU time 11.34 seconds
Started Apr 21 12:44:58 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201496 kb
Host smart-89ab0c2d-03bb-46c7-9fda-260aa20a46ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663265621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.663265621
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1816028786
Short name T909
Test name
Test status
Simulation time 325212623 ps
CPU time 1.58 seconds
Started Apr 21 12:45:02 PM PDT 24
Finished Apr 21 12:45:05 PM PDT 24
Peak memory 201320 kb
Host smart-764137d5-b04a-469d-a4c7-84c996d9019a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816028786 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1816028786
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1351631186
Short name T128
Test name
Test status
Simulation time 355256739 ps
CPU time 1.09 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 201176 kb
Host smart-4218d156-1ed9-482f-9f04-f5b904f05b14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351631186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1351631186
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2079072821
Short name T857
Test name
Test status
Simulation time 404522535 ps
CPU time 1.11 seconds
Started Apr 21 12:45:03 PM PDT 24
Finished Apr 21 12:45:05 PM PDT 24
Peak memory 201192 kb
Host smart-45032fec-aed4-4db8-9868-32278da0e930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079072821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2079072821
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4067120708
Short name T854
Test name
Test status
Simulation time 2733794119 ps
CPU time 6.5 seconds
Started Apr 21 12:45:13 PM PDT 24
Finished Apr 21 12:45:20 PM PDT 24
Peak memory 201196 kb
Host smart-f8410448-71b3-443b-9558-051c39e2f10f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067120708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4067120708
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3304864482
Short name T837
Test name
Test status
Simulation time 693938636 ps
CPU time 2.03 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201552 kb
Host smart-18a4650e-3956-4254-b3a6-784597b882a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304864482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3304864482
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.62964230
Short name T54
Test name
Test status
Simulation time 8559236382 ps
CPU time 7.41 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:12 PM PDT 24
Peak memory 201464 kb
Host smart-38bc5382-0943-43cd-9f17-9f39fbc2c8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62964230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_int
g_err.62964230
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.36361456
Short name T80
Test name
Test status
Simulation time 456359824 ps
CPU time 1.11 seconds
Started Apr 21 12:45:02 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 201156 kb
Host smart-c88ecf3b-d017-4aba-bbef-b54266cbda79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36361456 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.36361456
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2917245568
Short name T125
Test name
Test status
Simulation time 488492053 ps
CPU time 1 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201244 kb
Host smart-efbd215e-82c4-4022-a9d7-bf200ae744d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917245568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2917245568
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.998142885
Short name T900
Test name
Test status
Simulation time 497115015 ps
CPU time 0.69 seconds
Started Apr 21 12:45:18 PM PDT 24
Finished Apr 21 12:45:19 PM PDT 24
Peak memory 201228 kb
Host smart-3bafd291-26e3-4cb8-8bae-f921cb92bdf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998142885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.998142885
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.311610150
Short name T130
Test name
Test status
Simulation time 4019308908 ps
CPU time 3.63 seconds
Started Apr 21 12:45:25 PM PDT 24
Finished Apr 21 12:45:29 PM PDT 24
Peak memory 201480 kb
Host smart-fa6cfedd-862d-4304-b054-795166926c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311610150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.311610150
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1915810900
Short name T814
Test name
Test status
Simulation time 524544395 ps
CPU time 1.65 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201368 kb
Host smart-7b5fa0d0-453d-4dd3-81a2-c5514bc8cf42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915810900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1915810900
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1426367644
Short name T50
Test name
Test status
Simulation time 8250098629 ps
CPU time 7.08 seconds
Started Apr 21 12:45:06 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201368 kb
Host smart-dfc40d96-f5ef-4159-ba7a-182249093dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426367644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1426367644
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1900010176
Short name T58
Test name
Test status
Simulation time 398655334 ps
CPU time 1.74 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201320 kb
Host smart-f05e4b9e-e461-4680-85b9-f41b1c507637
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900010176 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1900010176
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3434399192
Short name T896
Test name
Test status
Simulation time 600841219 ps
CPU time 1.15 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:12 PM PDT 24
Peak memory 201116 kb
Host smart-308471b8-e352-4718-9e3e-b36e3cda4fc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434399192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3434399192
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1592263570
Short name T836
Test name
Test status
Simulation time 513068811 ps
CPU time 0.92 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201188 kb
Host smart-52e8fcde-c6c5-4d14-9aff-ac7df9a8c456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592263570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1592263570
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4179020126
Short name T850
Test name
Test status
Simulation time 4190185640 ps
CPU time 9.89 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:18 PM PDT 24
Peak memory 201452 kb
Host smart-1a33b15e-0794-4bda-8643-013db848e3a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179020126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4179020126
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.5049112
Short name T122
Test name
Test status
Simulation time 940945485 ps
CPU time 4.23 seconds
Started Apr 21 12:44:51 PM PDT 24
Finished Apr 21 12:44:55 PM PDT 24
Peak memory 201304 kb
Host smart-9b6ba67d-8fd9-4932-9748-7383023afc51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5049112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasin
g.5049112
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3441075910
Short name T117
Test name
Test status
Simulation time 1063542960 ps
CPU time 5.62 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201336 kb
Host smart-74a88261-a3c1-461d-88ee-2f8caf56c542
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441075910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3441075910
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.475002779
Short name T111
Test name
Test status
Simulation time 1101827646 ps
CPU time 1.33 seconds
Started Apr 21 12:45:28 PM PDT 24
Finished Apr 21 12:45:30 PM PDT 24
Peak memory 201132 kb
Host smart-ca12a3e4-4e4d-4ae0-9478-6c422959d1b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475002779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.475002779
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.35142760
Short name T893
Test name
Test status
Simulation time 596715419 ps
CPU time 1.38 seconds
Started Apr 21 12:45:02 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 201232 kb
Host smart-f3ab860c-c5b7-4a4c-b87f-8b64cbf664d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35142760 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.35142760
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3946633686
Short name T129
Test name
Test status
Simulation time 452260244 ps
CPU time 1.16 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:02 PM PDT 24
Peak memory 201128 kb
Host smart-f8e5353d-a05d-4a20-aa9b-3642199dfdb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946633686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3946633686
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.61785203
Short name T803
Test name
Test status
Simulation time 310546582 ps
CPU time 0.84 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:03 PM PDT 24
Peak memory 201400 kb
Host smart-feb6a369-5cf3-4d38-b4bd-687a043dfee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61785203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.61785203
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1532579506
Short name T913
Test name
Test status
Simulation time 1529262635 ps
CPU time 4.39 seconds
Started Apr 21 12:45:06 PM PDT 24
Finished Apr 21 12:45:11 PM PDT 24
Peak memory 201116 kb
Host smart-7355ddf8-f162-4a39-9c91-f02904bf1070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532579506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1532579506
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1777157554
Short name T910
Test name
Test status
Simulation time 433649192 ps
CPU time 2.49 seconds
Started Apr 21 12:44:58 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 209688 kb
Host smart-8290ac17-a8fe-4a7a-ab5b-b6c9fe824ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777157554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1777157554
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3909847606
Short name T824
Test name
Test status
Simulation time 3866288782 ps
CPU time 10.38 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:15 PM PDT 24
Peak memory 201464 kb
Host smart-21cc4058-1aca-4e9c-9554-26c912ca763c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909847606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3909847606
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2098198788
Short name T843
Test name
Test status
Simulation time 511592436 ps
CPU time 1.91 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 201172 kb
Host smart-133e0fac-da38-45c8-89af-8605fd76caa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098198788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2098198788
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.885497379
Short name T906
Test name
Test status
Simulation time 480694042 ps
CPU time 1.69 seconds
Started Apr 21 12:45:08 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201228 kb
Host smart-2be280d6-bcae-4feb-81b3-8c7f56cf9ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885497379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.885497379
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.40412398
Short name T878
Test name
Test status
Simulation time 303193875 ps
CPU time 0.99 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:45:13 PM PDT 24
Peak memory 201236 kb
Host smart-1fc05579-b8db-40dd-b4e0-5d5d946149a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40412398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.40412398
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1091242227
Short name T902
Test name
Test status
Simulation time 460827825 ps
CPU time 1.75 seconds
Started Apr 21 12:45:14 PM PDT 24
Finished Apr 21 12:45:21 PM PDT 24
Peak memory 201248 kb
Host smart-d1f7d519-2fef-4c29-a2a0-8f9c17fb9641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091242227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1091242227
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1135601642
Short name T901
Test name
Test status
Simulation time 384365216 ps
CPU time 0.91 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:13 PM PDT 24
Peak memory 201244 kb
Host smart-ac471605-8e9d-48fe-b828-2479505352e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135601642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1135601642
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1417045284
Short name T881
Test name
Test status
Simulation time 345876648 ps
CPU time 0.75 seconds
Started Apr 21 12:44:55 PM PDT 24
Finished Apr 21 12:44:57 PM PDT 24
Peak memory 201204 kb
Host smart-5937b27f-97b0-4a69-984f-6f5d83a3191b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417045284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1417045284
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.780307689
Short name T807
Test name
Test status
Simulation time 382447993 ps
CPU time 1.07 seconds
Started Apr 21 12:45:08 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201228 kb
Host smart-51ac740e-16b5-4bc9-aca7-24d3b78b1e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780307689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.780307689
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3503129610
Short name T816
Test name
Test status
Simulation time 400246394 ps
CPU time 1.46 seconds
Started Apr 21 12:44:55 PM PDT 24
Finished Apr 21 12:44:57 PM PDT 24
Peak memory 201116 kb
Host smart-22d595e6-9317-46fe-8002-535cb48b9a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503129610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3503129610
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4203908526
Short name T908
Test name
Test status
Simulation time 405368138 ps
CPU time 0.91 seconds
Started Apr 21 12:45:18 PM PDT 24
Finished Apr 21 12:45:20 PM PDT 24
Peak memory 201104 kb
Host smart-5958fa05-858a-4447-a0db-0a4c4ee5e364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203908526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.4203908526
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3963408162
Short name T842
Test name
Test status
Simulation time 467549521 ps
CPU time 1.72 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201236 kb
Host smart-a9fac0c6-311b-40eb-bc07-088d0e23ae0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963408162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3963408162
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.636541173
Short name T864
Test name
Test status
Simulation time 1271176062 ps
CPU time 5.19 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:45:17 PM PDT 24
Peak memory 201416 kb
Host smart-177c4bda-dcdb-431f-bb87-ac8895954167
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636541173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.636541173
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3212491894
Short name T835
Test name
Test status
Simulation time 26862949538 ps
CPU time 10.54 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:12 PM PDT 24
Peak memory 201472 kb
Host smart-cb7a4202-7241-4fe6-a6bf-81e99a734848
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212491894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3212491894
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2654704577
Short name T821
Test name
Test status
Simulation time 1149870718 ps
CPU time 2.04 seconds
Started Apr 21 12:45:06 PM PDT 24
Finished Apr 21 12:45:09 PM PDT 24
Peak memory 201240 kb
Host smart-5d7fb1da-ccef-402b-b11a-572d14c2fea6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654704577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2654704577
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.915915616
Short name T889
Test name
Test status
Simulation time 587445456 ps
CPU time 2.01 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201172 kb
Host smart-a99a2be9-669f-4043-a142-62da966cf94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915915616 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.915915616
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3288145831
Short name T110
Test name
Test status
Simulation time 403806284 ps
CPU time 1.73 seconds
Started Apr 21 12:44:52 PM PDT 24
Finished Apr 21 12:44:54 PM PDT 24
Peak memory 201128 kb
Host smart-e12b3732-018d-42ec-8c8d-1b7387f8ace7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288145831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3288145831
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.137376588
Short name T810
Test name
Test status
Simulation time 451742461 ps
CPU time 1.14 seconds
Started Apr 21 12:45:03 PM PDT 24
Finished Apr 21 12:45:05 PM PDT 24
Peak memory 201232 kb
Host smart-1034d7c4-e2f7-4267-adf7-77a1ed299df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137376588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.137376588
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.177803172
Short name T859
Test name
Test status
Simulation time 2629387323 ps
CPU time 2.75 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:03 PM PDT 24
Peak memory 201296 kb
Host smart-7a9083c4-75f7-4cb9-8132-fa6157b43075
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177803172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.177803172
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3818961328
Short name T811
Test name
Test status
Simulation time 548077462 ps
CPU time 2.2 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:45:15 PM PDT 24
Peak memory 209584 kb
Host smart-3af6105e-cb98-49d3-ae9b-a48b97263be4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818961328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3818961328
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3094840705
Short name T369
Test name
Test status
Simulation time 8626046032 ps
CPU time 7.68 seconds
Started Apr 21 12:44:57 PM PDT 24
Finished Apr 21 12:45:05 PM PDT 24
Peak memory 201464 kb
Host smart-49a14d56-9ea3-407e-95d8-9fe7c97f65e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094840705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3094840705
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4234442231
Short name T915
Test name
Test status
Simulation time 539750801 ps
CPU time 0.93 seconds
Started Apr 21 12:45:27 PM PDT 24
Finished Apr 21 12:45:28 PM PDT 24
Peak memory 201112 kb
Host smart-58737b4e-8f1a-4744-a3fc-31015242de77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234442231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4234442231
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3858285497
Short name T801
Test name
Test status
Simulation time 497631734 ps
CPU time 0.75 seconds
Started Apr 21 12:45:15 PM PDT 24
Finished Apr 21 12:45:16 PM PDT 24
Peak memory 201212 kb
Host smart-faf40371-051c-41aa-9e03-2141b40e52d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858285497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3858285497
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4062878962
Short name T858
Test name
Test status
Simulation time 425398262 ps
CPU time 0.99 seconds
Started Apr 21 12:45:15 PM PDT 24
Finished Apr 21 12:45:16 PM PDT 24
Peak memory 201236 kb
Host smart-8b81100e-dcb5-464a-b91c-368b51e36def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062878962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.4062878962
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2324252259
Short name T866
Test name
Test status
Simulation time 319600570 ps
CPU time 1.38 seconds
Started Apr 21 12:45:16 PM PDT 24
Finished Apr 21 12:45:18 PM PDT 24
Peak memory 201132 kb
Host smart-aa5c575d-2b93-4a06-8a65-ac0968969d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324252259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2324252259
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3952379595
Short name T892
Test name
Test status
Simulation time 435565369 ps
CPU time 0.94 seconds
Started Apr 21 12:45:15 PM PDT 24
Finished Apr 21 12:45:17 PM PDT 24
Peak memory 201196 kb
Host smart-48e8c417-4046-4b7a-b1b6-871d1ebd7a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952379595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3952379595
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.923659950
Short name T868
Test name
Test status
Simulation time 324082769 ps
CPU time 0.84 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 201112 kb
Host smart-2a7eab62-25db-4a9e-9596-93bb93a7b31d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923659950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.923659950
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1882700568
Short name T829
Test name
Test status
Simulation time 408052120 ps
CPU time 1.55 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201232 kb
Host smart-7102df4c-5254-4574-87b2-6e66649a8982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882700568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1882700568
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1969108320
Short name T861
Test name
Test status
Simulation time 417255475 ps
CPU time 1.75 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201236 kb
Host smart-610b4ab9-c2ee-43ab-8c51-2eacddfc08d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969108320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1969108320
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1645712607
Short name T804
Test name
Test status
Simulation time 430114345 ps
CPU time 1.68 seconds
Started Apr 21 12:45:21 PM PDT 24
Finished Apr 21 12:45:23 PM PDT 24
Peak memory 201104 kb
Host smart-ab60782c-ab67-44e7-91c0-c0057ad06202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645712607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1645712607
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.238201500
Short name T885
Test name
Test status
Simulation time 464702222 ps
CPU time 0.77 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:13 PM PDT 24
Peak memory 201232 kb
Host smart-0290128d-58e5-4d6c-8f91-9fd210232126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238201500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.238201500
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3974618732
Short name T116
Test name
Test status
Simulation time 1267006998 ps
CPU time 3.67 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201308 kb
Host smart-eec0f5e0-a7ce-4c12-a1b8-0a2a8bb48af3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974618732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3974618732
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1699451479
Short name T115
Test name
Test status
Simulation time 18370329965 ps
CPU time 27.88 seconds
Started Apr 21 12:45:14 PM PDT 24
Finished Apr 21 12:45:43 PM PDT 24
Peak memory 201416 kb
Host smart-11623a22-a13f-40a8-b071-462104045104
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699451479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1699451479
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2464878431
Short name T119
Test name
Test status
Simulation time 1134041711 ps
CPU time 1.49 seconds
Started Apr 21 12:44:58 PM PDT 24
Finished Apr 21 12:45:00 PM PDT 24
Peak memory 201220 kb
Host smart-ebfd3280-3f5d-4c25-ac30-016929a5a5af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464878431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2464878431
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.757509612
Short name T886
Test name
Test status
Simulation time 566321650 ps
CPU time 2.14 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:02 PM PDT 24
Peak memory 201172 kb
Host smart-d57a5e4d-60df-4362-8c20-b78094f93dfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757509612 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.757509612
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2768325786
Short name T118
Test name
Test status
Simulation time 535933615 ps
CPU time 2.04 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201212 kb
Host smart-bbcf976a-523b-459e-8c1a-be8356aae4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768325786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2768325786
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3156790108
Short name T877
Test name
Test status
Simulation time 368072508 ps
CPU time 1 seconds
Started Apr 21 12:44:55 PM PDT 24
Finished Apr 21 12:44:57 PM PDT 24
Peak memory 201180 kb
Host smart-a8912064-e301-4be0-8835-baf02b6746f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156790108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3156790108
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.952219761
Short name T840
Test name
Test status
Simulation time 4982953303 ps
CPU time 4.51 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 201548 kb
Host smart-0715cb19-8c09-488a-84f8-d1c8fb4d4153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952219761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.952219761
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3175032511
Short name T60
Test name
Test status
Simulation time 1044945826 ps
CPU time 1.41 seconds
Started Apr 21 12:44:57 PM PDT 24
Finished Apr 21 12:44:59 PM PDT 24
Peak memory 201432 kb
Host smart-3527063e-e86b-4c94-b512-7eed7bc460e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175032511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3175032511
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2856561920
Short name T884
Test name
Test status
Simulation time 8770629444 ps
CPU time 12.88 seconds
Started Apr 21 12:44:50 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 201368 kb
Host smart-4e40fd70-7b4a-410f-bee6-6a4e1b450d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856561920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2856561920
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1123284341
Short name T880
Test name
Test status
Simulation time 386160836 ps
CPU time 0.74 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201120 kb
Host smart-6139037e-cb3e-4f92-b117-59caeddb119d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123284341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1123284341
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4003016928
Short name T809
Test name
Test status
Simulation time 452343891 ps
CPU time 0.94 seconds
Started Apr 21 12:45:08 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201140 kb
Host smart-23d55a94-94df-46c4-8f78-ad3bff903faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003016928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4003016928
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1083904050
Short name T865
Test name
Test status
Simulation time 298798981 ps
CPU time 0.81 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:03 PM PDT 24
Peak memory 201120 kb
Host smart-1848e72e-30f3-4400-a499-b3781e5b33fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083904050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1083904050
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2266068575
Short name T841
Test name
Test status
Simulation time 285302860 ps
CPU time 1.29 seconds
Started Apr 21 12:45:16 PM PDT 24
Finished Apr 21 12:45:17 PM PDT 24
Peak memory 201164 kb
Host smart-9684d448-1fc1-4998-83ab-2d5ba8a2ac52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266068575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2266068575
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1630493046
Short name T802
Test name
Test status
Simulation time 368561501 ps
CPU time 1.1 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201112 kb
Host smart-eedb8c60-4fe8-4769-8800-0e4ee7ee5264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630493046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1630493046
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.560781539
Short name T853
Test name
Test status
Simulation time 418168460 ps
CPU time 1.68 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:06 PM PDT 24
Peak memory 201128 kb
Host smart-2ddc6c71-f0bc-4ced-8703-808c6ed4a428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560781539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.560781539
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3956163012
Short name T855
Test name
Test status
Simulation time 412471669 ps
CPU time 1.68 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201132 kb
Host smart-20b5d678-a48b-43db-bd35-b106aaab15cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956163012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3956163012
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.188357288
Short name T815
Test name
Test status
Simulation time 528795890 ps
CPU time 0.96 seconds
Started Apr 21 12:45:03 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 201216 kb
Host smart-fb9b906f-ea5d-4c58-b6c5-0a87df863a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188357288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.188357288
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3785945007
Short name T808
Test name
Test status
Simulation time 364095580 ps
CPU time 1.48 seconds
Started Apr 21 12:45:11 PM PDT 24
Finished Apr 21 12:45:13 PM PDT 24
Peak memory 201120 kb
Host smart-b4db5173-de6c-45e2-a679-0f1b6030dcfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785945007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3785945007
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.890826504
Short name T914
Test name
Test status
Simulation time 494585273 ps
CPU time 1.82 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:15 PM PDT 24
Peak memory 201212 kb
Host smart-23fd794b-56f4-4597-86d3-121902d7e372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890826504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.890826504
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2529111457
Short name T53
Test name
Test status
Simulation time 591934695 ps
CPU time 1.03 seconds
Started Apr 21 12:45:02 PM PDT 24
Finished Apr 21 12:45:04 PM PDT 24
Peak memory 201144 kb
Host smart-20365545-71f2-4f75-9b9c-01e62c350802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529111457 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2529111457
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3008196081
Short name T899
Test name
Test status
Simulation time 393332461 ps
CPU time 1.15 seconds
Started Apr 21 12:45:06 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201216 kb
Host smart-04f3f4e4-f2ea-4d05-b355-5f077d078742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008196081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3008196081
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2005356522
Short name T904
Test name
Test status
Simulation time 513668052 ps
CPU time 0.94 seconds
Started Apr 21 12:44:54 PM PDT 24
Finished Apr 21 12:44:55 PM PDT 24
Peak memory 201240 kb
Host smart-a7ec660b-9119-4be4-904b-0b1ff8416b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005356522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2005356522
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2241394164
Short name T898
Test name
Test status
Simulation time 4448216260 ps
CPU time 17.84 seconds
Started Apr 21 12:44:55 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201540 kb
Host smart-37320687-5075-4230-a7ef-be59669cd553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241394164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2241394164
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3569453304
Short name T63
Test name
Test status
Simulation time 364070808 ps
CPU time 2.12 seconds
Started Apr 21 12:44:50 PM PDT 24
Finished Apr 21 12:44:53 PM PDT 24
Peak memory 201324 kb
Host smart-1bac6d83-67d1-48db-9c02-6943d65d3d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569453304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3569453304
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2135540218
Short name T869
Test name
Test status
Simulation time 8726530526 ps
CPU time 12.56 seconds
Started Apr 21 12:45:09 PM PDT 24
Finished Apr 21 12:45:22 PM PDT 24
Peak memory 201396 kb
Host smart-77d8457e-c354-4596-9540-12cce8cdd6d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135540218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2135540218
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4094437542
Short name T833
Test name
Test status
Simulation time 585356752 ps
CPU time 1.24 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:44:58 PM PDT 24
Peak memory 201296 kb
Host smart-ab81c1fc-f726-4c68-8e4f-4ca9ef0da92d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094437542 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4094437542
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.601907722
Short name T887
Test name
Test status
Simulation time 406353057 ps
CPU time 1.68 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201112 kb
Host smart-2146bfc1-3550-4021-a8e1-de9b293fb111
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601907722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.601907722
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.195753057
Short name T879
Test name
Test status
Simulation time 318174465 ps
CPU time 1.31 seconds
Started Apr 21 12:44:54 PM PDT 24
Finished Apr 21 12:44:56 PM PDT 24
Peak memory 201128 kb
Host smart-26a981a5-f86b-4642-9a5e-7e230321d7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195753057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.195753057
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4162979400
Short name T872
Test name
Test status
Simulation time 5316984290 ps
CPU time 5.29 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:10 PM PDT 24
Peak memory 201344 kb
Host smart-47755929-3e7e-4e39-9f1a-600bb250a55b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162979400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4162979400
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.103706624
Short name T830
Test name
Test status
Simulation time 514544844 ps
CPU time 1.65 seconds
Started Apr 21 12:45:12 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201376 kb
Host smart-f3d9272b-ed20-429e-bf7d-8f9d69642150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103706624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.103706624
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2130916531
Short name T890
Test name
Test status
Simulation time 4388793636 ps
CPU time 4.44 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:45:02 PM PDT 24
Peak memory 201460 kb
Host smart-f62681df-82a3-40df-b379-1edfbdeb6dc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130916531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2130916531
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.181466372
Short name T895
Test name
Test status
Simulation time 484673082 ps
CPU time 2.23 seconds
Started Apr 21 12:45:10 PM PDT 24
Finished Apr 21 12:45:14 PM PDT 24
Peak memory 201196 kb
Host smart-360850f7-cbb5-4c4a-9b56-a4f53ad8c567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181466372 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.181466372
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1583722009
Short name T912
Test name
Test status
Simulation time 552466899 ps
CPU time 1.25 seconds
Started Apr 21 12:44:57 PM PDT 24
Finished Apr 21 12:44:59 PM PDT 24
Peak memory 201132 kb
Host smart-c9d2440c-f9f5-4f76-8d57-780a2ffc611e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583722009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1583722009
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2386619105
Short name T806
Test name
Test status
Simulation time 415970724 ps
CPU time 0.96 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:03 PM PDT 24
Peak memory 201128 kb
Host smart-af181b06-e785-4bcc-88b0-3e3e075e4de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386619105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2386619105
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2702645433
Short name T860
Test name
Test status
Simulation time 4976501264 ps
CPU time 10.81 seconds
Started Apr 21 12:45:01 PM PDT 24
Finished Apr 21 12:45:13 PM PDT 24
Peak memory 201460 kb
Host smart-b77479ad-2de9-4d26-9923-b7c1e7f48f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702645433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2702645433
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.666499295
Short name T813
Test name
Test status
Simulation time 448306769 ps
CPU time 1.6 seconds
Started Apr 21 12:45:03 PM PDT 24
Finished Apr 21 12:45:05 PM PDT 24
Peak memory 201444 kb
Host smart-db2cfe12-1eef-4085-968b-7c3e0da301c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666499295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.666499295
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2058759567
Short name T871
Test name
Test status
Simulation time 4949037473 ps
CPU time 2.09 seconds
Started Apr 21 12:45:02 PM PDT 24
Finished Apr 21 12:45:05 PM PDT 24
Peak memory 201424 kb
Host smart-1b8d5d52-9a7c-4d93-bdc0-e9e1f573e578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058759567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2058759567
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3144427823
Short name T839
Test name
Test status
Simulation time 343588820 ps
CPU time 1.65 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201256 kb
Host smart-2ff4b304-2939-4438-b98d-3117b80b067d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144427823 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3144427823
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3729620960
Short name T120
Test name
Test status
Simulation time 375873970 ps
CPU time 1.41 seconds
Started Apr 21 12:45:06 PM PDT 24
Finished Apr 21 12:45:09 PM PDT 24
Peak memory 201132 kb
Host smart-62f1c5a7-e338-423d-905d-01904352c71b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729620960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3729620960
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3983029908
Short name T838
Test name
Test status
Simulation time 548572598 ps
CPU time 0.77 seconds
Started Apr 21 12:45:05 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201200 kb
Host smart-1faadef2-1a5a-44e6-ab72-bfd36a0d64d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983029908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3983029908
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2023656211
Short name T47
Test name
Test status
Simulation time 2346061783 ps
CPU time 5.15 seconds
Started Apr 21 12:44:58 PM PDT 24
Finished Apr 21 12:45:03 PM PDT 24
Peak memory 201272 kb
Host smart-e0bcc3d7-c553-4159-b807-ee7d2b4d0122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023656211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2023656211
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1714556129
Short name T820
Test name
Test status
Simulation time 474128827 ps
CPU time 3.15 seconds
Started Apr 21 12:45:17 PM PDT 24
Finished Apr 21 12:45:20 PM PDT 24
Peak memory 217732 kb
Host smart-a574ceec-0b3f-4945-85f3-7385b9cf9d83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714556129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1714556129
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1509588337
Short name T903
Test name
Test status
Simulation time 8825551761 ps
CPU time 12.55 seconds
Started Apr 21 12:45:15 PM PDT 24
Finished Apr 21 12:45:28 PM PDT 24
Peak memory 201388 kb
Host smart-3c5bbfe5-282a-41bd-a6d0-f83d9d25a6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509588337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1509588337
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3908698690
Short name T848
Test name
Test status
Simulation time 487249695 ps
CPU time 1.55 seconds
Started Apr 21 12:45:07 PM PDT 24
Finished Apr 21 12:45:09 PM PDT 24
Peak memory 201292 kb
Host smart-c01718e7-5063-4cd0-9b99-51b44ab5b884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908698690 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3908698690
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3233392344
Short name T916
Test name
Test status
Simulation time 355642454 ps
CPU time 0.91 seconds
Started Apr 21 12:44:59 PM PDT 24
Finished Apr 21 12:45:01 PM PDT 24
Peak memory 201196 kb
Host smart-70485c38-d76b-404f-9e4d-33705111e646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233392344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3233392344
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2282563675
Short name T828
Test name
Test status
Simulation time 433913767 ps
CPU time 1.63 seconds
Started Apr 21 12:45:00 PM PDT 24
Finished Apr 21 12:45:03 PM PDT 24
Peak memory 201132 kb
Host smart-12d4d774-b2f6-4e5d-afee-304bda771f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282563675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2282563675
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4173757686
Short name T863
Test name
Test status
Simulation time 1838462835 ps
CPU time 1.6 seconds
Started Apr 21 12:44:56 PM PDT 24
Finished Apr 21 12:44:58 PM PDT 24
Peak memory 201188 kb
Host smart-ff7455e5-31b9-4324-8fd3-4a9ad1d26223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173757686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4173757686
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3115124368
Short name T62
Test name
Test status
Simulation time 370236050 ps
CPU time 2.14 seconds
Started Apr 21 12:45:04 PM PDT 24
Finished Apr 21 12:45:07 PM PDT 24
Peak memory 201396 kb
Host smart-13c92343-3917-4497-a6c9-df47355032b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115124368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3115124368
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1513795055
Short name T897
Test name
Test status
Simulation time 4676381774 ps
CPU time 4.27 seconds
Started Apr 21 12:45:03 PM PDT 24
Finished Apr 21 12:45:08 PM PDT 24
Peak memory 201424 kb
Host smart-d9d40353-8052-43fc-86d9-c5d4ba64e793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513795055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1513795055
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2220763863
Short name T556
Test name
Test status
Simulation time 555859555 ps
CPU time 0.99 seconds
Started Apr 21 01:52:11 PM PDT 24
Finished Apr 21 01:52:12 PM PDT 24
Peak memory 201964 kb
Host smart-7361d3ad-a7be-4f1e-ba2e-09a5a6d9a630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220763863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2220763863
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.918621424
Short name T102
Test name
Test status
Simulation time 165141236584 ps
CPU time 50.03 seconds
Started Apr 21 01:52:03 PM PDT 24
Finished Apr 21 01:52:53 PM PDT 24
Peak memory 202268 kb
Host smart-f5120739-64fc-4f3f-b5dc-7f7884f7a30a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918621424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.918621424
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1186285443
Short name T160
Test name
Test status
Simulation time 418862009583 ps
CPU time 926.52 seconds
Started Apr 21 01:52:06 PM PDT 24
Finished Apr 21 02:07:33 PM PDT 24
Peak memory 202272 kb
Host smart-1d83d63a-693f-418d-ab8a-b3334b910cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186285443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1186285443
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.944070606
Short name T252
Test name
Test status
Simulation time 495912608284 ps
CPU time 907.4 seconds
Started Apr 21 01:52:02 PM PDT 24
Finished Apr 21 02:07:09 PM PDT 24
Peak memory 202248 kb
Host smart-661f6c07-6a8b-4de8-9294-6cb014e9e408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944070606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.944070606
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.471261267
Short name T742
Test name
Test status
Simulation time 164455752452 ps
CPU time 372.67 seconds
Started Apr 21 01:52:07 PM PDT 24
Finished Apr 21 01:58:20 PM PDT 24
Peak memory 202232 kb
Host smart-452e2570-602e-420d-97b5-c23d94112918
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=471261267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.471261267
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3179800036
Short name T85
Test name
Test status
Simulation time 166497901463 ps
CPU time 197.44 seconds
Started Apr 21 01:51:58 PM PDT 24
Finished Apr 21 01:55:15 PM PDT 24
Peak memory 202244 kb
Host smart-0c9d4702-adbe-44b9-adab-507854068fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179800036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3179800036
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3288915766
Short name T109
Test name
Test status
Simulation time 327877362640 ps
CPU time 101.98 seconds
Started Apr 21 01:52:02 PM PDT 24
Finished Apr 21 01:53:45 PM PDT 24
Peak memory 202320 kb
Host smart-ef62d5bc-8164-4e42-b5b1-3ee57dd8a888
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288915766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3288915766
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.284069565
Short name T206
Test name
Test status
Simulation time 201789272707 ps
CPU time 496.39 seconds
Started Apr 21 01:52:07 PM PDT 24
Finished Apr 21 02:00:24 PM PDT 24
Peak memory 202260 kb
Host smart-e782534b-84cf-4ab6-8760-366185f305f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284069565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.284069565
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3956436267
Short name T600
Test name
Test status
Simulation time 393954761106 ps
CPU time 903.17 seconds
Started Apr 21 01:52:00 PM PDT 24
Finished Apr 21 02:07:03 PM PDT 24
Peak memory 202404 kb
Host smart-a336f07e-af31-40eb-b556-22f57f94f08e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956436267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3956436267
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1064860157
Short name T90
Test name
Test status
Simulation time 87860249583 ps
CPU time 446.55 seconds
Started Apr 21 01:52:06 PM PDT 24
Finished Apr 21 01:59:32 PM PDT 24
Peak memory 202556 kb
Host smart-db213ef2-8729-4f90-a890-d74675db5a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064860157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1064860157
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.148788187
Short name T644
Test name
Test status
Simulation time 43171907501 ps
CPU time 25.89 seconds
Started Apr 21 01:52:05 PM PDT 24
Finished Apr 21 01:52:31 PM PDT 24
Peak memory 202072 kb
Host smart-2826839f-5d88-42ca-93e8-a1275819c560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148788187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.148788187
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2114619062
Short name T481
Test name
Test status
Simulation time 3155429488 ps
CPU time 8.18 seconds
Started Apr 21 01:52:03 PM PDT 24
Finished Apr 21 01:52:12 PM PDT 24
Peak memory 202116 kb
Host smart-f11fc955-5b80-451c-80e7-74cbfe81663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114619062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2114619062
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3204885798
Short name T56
Test name
Test status
Simulation time 3969856929 ps
CPU time 4.48 seconds
Started Apr 21 01:52:03 PM PDT 24
Finished Apr 21 01:52:08 PM PDT 24
Peak memory 217816 kb
Host smart-ed6a70a5-9e27-49e9-a105-1670a462f5e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204885798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3204885798
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.889491809
Short name T705
Test name
Test status
Simulation time 6122042766 ps
CPU time 14.29 seconds
Started Apr 21 01:51:56 PM PDT 24
Finished Apr 21 01:52:11 PM PDT 24
Peak memory 202044 kb
Host smart-c6832be3-843e-44f5-baec-8faeac4480c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889491809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.889491809
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3909645846
Short name T361
Test name
Test status
Simulation time 327661945362 ps
CPU time 508.26 seconds
Started Apr 21 01:52:04 PM PDT 24
Finished Apr 21 02:00:33 PM PDT 24
Peak memory 202356 kb
Host smart-58a6d269-5f6d-4bdd-9c6f-6226b27dee07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909645846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3909645846
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1901293351
Short name T529
Test name
Test status
Simulation time 502826685 ps
CPU time 1.79 seconds
Started Apr 21 01:52:10 PM PDT 24
Finished Apr 21 01:52:12 PM PDT 24
Peak memory 201936 kb
Host smart-ce7e658c-434f-4f40-9f45-f30177c6f319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901293351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1901293351
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2914916367
Short name T202
Test name
Test status
Simulation time 359583712908 ps
CPU time 514.69 seconds
Started Apr 21 01:52:10 PM PDT 24
Finished Apr 21 02:00:45 PM PDT 24
Peak memory 202260 kb
Host smart-18ce79ef-fdc3-4944-8d50-6614837571e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914916367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2914916367
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2782894420
Short name T302
Test name
Test status
Simulation time 495962893658 ps
CPU time 1171.44 seconds
Started Apr 21 01:52:10 PM PDT 24
Finished Apr 21 02:11:42 PM PDT 24
Peak memory 202360 kb
Host smart-820d7fa3-c0ad-410d-8fa5-e61608cdb5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782894420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2782894420
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.26283967
Short name T536
Test name
Test status
Simulation time 323803677114 ps
CPU time 788.75 seconds
Started Apr 21 01:52:09 PM PDT 24
Finished Apr 21 02:05:18 PM PDT 24
Peak memory 202220 kb
Host smart-fa8c8b2f-8fd1-4b98-ba07-ced78541764f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=26283967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_
fixed.26283967
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2508608203
Short name T78
Test name
Test status
Simulation time 503639599088 ps
CPU time 196.8 seconds
Started Apr 21 01:52:04 PM PDT 24
Finished Apr 21 01:55:22 PM PDT 24
Peak memory 202336 kb
Host smart-4c56bbb4-e5da-42ef-a761-c062a170ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508608203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2508608203
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3099456743
Short name T428
Test name
Test status
Simulation time 325769797247 ps
CPU time 429.98 seconds
Started Apr 21 01:52:09 PM PDT 24
Finished Apr 21 01:59:19 PM PDT 24
Peak memory 202232 kb
Host smart-1a30c639-706a-41ab-966b-5a7c5cc9b4cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099456743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3099456743
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.568565486
Short name T550
Test name
Test status
Simulation time 202146637330 ps
CPU time 80.55 seconds
Started Apr 21 01:52:09 PM PDT 24
Finished Apr 21 01:53:30 PM PDT 24
Peak memory 202268 kb
Host smart-e8dcfd6b-e218-45ec-ad56-ef9819fbea58
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568565486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.568565486
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2010400506
Short name T433
Test name
Test status
Simulation time 80184496112 ps
CPU time 401.5 seconds
Started Apr 21 01:52:08 PM PDT 24
Finished Apr 21 01:58:49 PM PDT 24
Peak memory 202600 kb
Host smart-c9bd604f-d5d2-410b-8ab3-673830aa4127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010400506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2010400506
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2269595185
Short name T783
Test name
Test status
Simulation time 30342131120 ps
CPU time 16.38 seconds
Started Apr 21 01:52:10 PM PDT 24
Finished Apr 21 01:52:26 PM PDT 24
Peak memory 202064 kb
Host smart-231102a5-432f-4aba-9505-9232dcd60b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269595185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2269595185
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1714647456
Short name T446
Test name
Test status
Simulation time 5218737096 ps
CPU time 11.96 seconds
Started Apr 21 01:52:07 PM PDT 24
Finished Apr 21 01:52:19 PM PDT 24
Peak memory 202068 kb
Host smart-d02fd8e8-69ec-439f-bb54-1ff3f29165a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714647456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1714647456
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2944190598
Short name T422
Test name
Test status
Simulation time 5891679636 ps
CPU time 12.33 seconds
Started Apr 21 01:52:10 PM PDT 24
Finished Apr 21 01:52:22 PM PDT 24
Peak memory 202076 kb
Host smart-8bbd807a-51c7-437b-8f1a-74b88515c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944190598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2944190598
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1160439730
Short name T346
Test name
Test status
Simulation time 287225019397 ps
CPU time 920.2 seconds
Started Apr 21 01:52:08 PM PDT 24
Finished Apr 21 02:07:28 PM PDT 24
Peak memory 210820 kb
Host smart-0edb49ed-768d-4db5-923a-f3b05f843165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160439730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1160439730
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1877704710
Short name T633
Test name
Test status
Simulation time 52506287486 ps
CPU time 108.6 seconds
Started Apr 21 01:52:09 PM PDT 24
Finished Apr 21 01:53:58 PM PDT 24
Peak memory 210604 kb
Host smart-5f30c1cb-0be6-4fe7-9485-80b33c75ea5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877704710 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1877704710
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2552986147
Short name T203
Test name
Test status
Simulation time 522428063 ps
CPU time 0.83 seconds
Started Apr 21 01:54:31 PM PDT 24
Finished Apr 21 01:54:32 PM PDT 24
Peak memory 201984 kb
Host smart-7861d453-d9f8-4bf8-8569-dd0fbf662d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552986147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2552986147
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4216999292
Short name T332
Test name
Test status
Simulation time 169269124219 ps
CPU time 209.12 seconds
Started Apr 21 01:54:19 PM PDT 24
Finished Apr 21 01:57:49 PM PDT 24
Peak memory 202296 kb
Host smart-839a080f-a8b1-49bb-8b78-f4f54193e9b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216999292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4216999292
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2279131660
Short name T183
Test name
Test status
Simulation time 322627722650 ps
CPU time 698.36 seconds
Started Apr 21 01:54:18 PM PDT 24
Finished Apr 21 02:05:57 PM PDT 24
Peak memory 202240 kb
Host smart-6cab10d3-b325-48c9-8ccd-d59a1d65d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279131660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2279131660
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1368469983
Short name T391
Test name
Test status
Simulation time 494100698922 ps
CPU time 310.04 seconds
Started Apr 21 01:54:16 PM PDT 24
Finished Apr 21 01:59:26 PM PDT 24
Peak memory 202356 kb
Host smart-b9259d67-79fb-47a1-9667-683e6d416bc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368469983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1368469983
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3358937377
Short name T579
Test name
Test status
Simulation time 167677206647 ps
CPU time 91.6 seconds
Started Apr 21 01:54:15 PM PDT 24
Finished Apr 21 01:55:47 PM PDT 24
Peak memory 202320 kb
Host smart-5e414d22-cdba-48ae-a5cb-b17194ef0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358937377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3358937377
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2636260380
Short name T32
Test name
Test status
Simulation time 162720403429 ps
CPU time 50.1 seconds
Started Apr 21 01:54:16 PM PDT 24
Finished Apr 21 01:55:06 PM PDT 24
Peak memory 202304 kb
Host smart-2dcda887-173e-4e23-b5ba-39ee1980d5a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636260380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2636260380
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.140301650
Short name T322
Test name
Test status
Simulation time 183220635639 ps
CPU time 409.39 seconds
Started Apr 21 01:54:18 PM PDT 24
Finished Apr 21 02:01:08 PM PDT 24
Peak memory 202276 kb
Host smart-a1bb884b-c6d3-4b5d-8721-bef8e0eb5768
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140301650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.140301650
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.267415823
Short name T544
Test name
Test status
Simulation time 198539785934 ps
CPU time 252.77 seconds
Started Apr 21 01:54:21 PM PDT 24
Finished Apr 21 01:58:34 PM PDT 24
Peak memory 202280 kb
Host smart-f106e558-41c9-4df0-8bf2-16337eb84b92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267415823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.267415823
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2385805457
Short name T491
Test name
Test status
Simulation time 85232313025 ps
CPU time 266.29 seconds
Started Apr 21 01:54:27 PM PDT 24
Finished Apr 21 01:58:54 PM PDT 24
Peak memory 202564 kb
Host smart-37999b35-85d7-49b9-90cd-cf2bbdf874b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385805457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2385805457
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2024781697
Short name T642
Test name
Test status
Simulation time 30067955436 ps
CPU time 68.74 seconds
Started Apr 21 01:54:21 PM PDT 24
Finished Apr 21 01:55:30 PM PDT 24
Peak memory 202100 kb
Host smart-175c7856-32a4-490d-86cc-3748efa0efba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024781697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2024781697
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3821526729
Short name T787
Test name
Test status
Simulation time 3463876214 ps
CPU time 1.46 seconds
Started Apr 21 01:54:21 PM PDT 24
Finished Apr 21 01:54:22 PM PDT 24
Peak memory 202100 kb
Host smart-955cb6c0-0ec0-433c-bef1-6cbdbbe7e597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821526729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3821526729
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1899500593
Short name T377
Test name
Test status
Simulation time 5833991786 ps
CPU time 13.59 seconds
Started Apr 21 01:54:14 PM PDT 24
Finished Apr 21 01:54:27 PM PDT 24
Peak memory 202080 kb
Host smart-d94af524-6812-46af-8440-4acc6bac8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899500593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1899500593
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3237049848
Short name T151
Test name
Test status
Simulation time 529983256593 ps
CPU time 330.64 seconds
Started Apr 21 01:54:27 PM PDT 24
Finished Apr 21 01:59:58 PM PDT 24
Peak memory 202192 kb
Host smart-3c93f7d4-d8bb-4e97-b41a-ac4c1f2f3e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237049848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3237049848
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2436667423
Short name T352
Test name
Test status
Simulation time 158397710181 ps
CPU time 355.39 seconds
Started Apr 21 01:54:26 PM PDT 24
Finished Apr 21 02:00:22 PM PDT 24
Peak memory 218336 kb
Host smart-eb8ac071-8fc7-45fc-aa83-0d62a43d0220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436667423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2436667423
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2351963390
Short name T488
Test name
Test status
Simulation time 510485135 ps
CPU time 0.73 seconds
Started Apr 21 01:55:08 PM PDT 24
Finished Apr 21 01:55:09 PM PDT 24
Peak memory 201880 kb
Host smart-16b09eb1-7041-4cff-a796-4363539cb39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351963390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2351963390
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2059223400
Short name T211
Test name
Test status
Simulation time 379253139305 ps
CPU time 192.84 seconds
Started Apr 21 01:54:53 PM PDT 24
Finished Apr 21 01:58:06 PM PDT 24
Peak memory 202388 kb
Host smart-b09dc0a8-0767-4c4e-a5bb-1fd25d8c4595
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059223400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2059223400
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3968101439
Short name T319
Test name
Test status
Simulation time 494337037890 ps
CPU time 598.26 seconds
Started Apr 21 01:54:54 PM PDT 24
Finished Apr 21 02:04:52 PM PDT 24
Peak memory 202264 kb
Host smart-653e05ac-df3c-43b1-8d74-54a085ebe3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968101439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3968101439
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.296613287
Short name T711
Test name
Test status
Simulation time 323658648488 ps
CPU time 214.78 seconds
Started Apr 21 01:54:43 PM PDT 24
Finished Apr 21 01:58:18 PM PDT 24
Peak memory 202240 kb
Host smart-51e639eb-9d9f-48d8-b99c-ada1646cf415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296613287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.296613287
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2314189089
Short name T706
Test name
Test status
Simulation time 501925017720 ps
CPU time 309.82 seconds
Started Apr 21 01:54:43 PM PDT 24
Finished Apr 21 01:59:53 PM PDT 24
Peak memory 202272 kb
Host smart-e05b39eb-ef3c-439d-a17e-ab40fe4a38b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314189089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2314189089
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3169396447
Short name T720
Test name
Test status
Simulation time 332367371595 ps
CPU time 526.65 seconds
Started Apr 21 01:54:36 PM PDT 24
Finished Apr 21 02:03:23 PM PDT 24
Peak memory 202336 kb
Host smart-088897f0-8365-4887-848a-bb8e6f57d797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169396447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3169396447
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2802790811
Short name T460
Test name
Test status
Simulation time 171457166231 ps
CPU time 210.03 seconds
Started Apr 21 01:54:43 PM PDT 24
Finished Apr 21 01:58:13 PM PDT 24
Peak memory 202312 kb
Host smart-866f843a-2931-4289-a581-4ecb297682d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802790811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2802790811
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.795350513
Short name T539
Test name
Test status
Simulation time 553488239185 ps
CPU time 1212.8 seconds
Started Apr 21 01:54:50 PM PDT 24
Finished Apr 21 02:15:03 PM PDT 24
Peak memory 202332 kb
Host smart-1f5f8587-7689-4001-a9b0-116e61557451
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795350513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.795350513
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1137416854
Short name T678
Test name
Test status
Simulation time 404707592556 ps
CPU time 953.57 seconds
Started Apr 21 01:54:48 PM PDT 24
Finished Apr 21 02:10:42 PM PDT 24
Peak memory 202312 kb
Host smart-c7a5ccfd-5ded-491a-b5a7-29ba0193b2c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137416854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1137416854
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3129950983
Short name T670
Test name
Test status
Simulation time 93247234844 ps
CPU time 379.52 seconds
Started Apr 21 01:54:58 PM PDT 24
Finished Apr 21 02:01:18 PM PDT 24
Peak memory 202544 kb
Host smart-4569f416-551d-4e3a-a646-7c827716b2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129950983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3129950983
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3320713337
Short name T385
Test name
Test status
Simulation time 32852820358 ps
CPU time 74.15 seconds
Started Apr 21 01:54:58 PM PDT 24
Finished Apr 21 01:56:12 PM PDT 24
Peak memory 202036 kb
Host smart-7be1061b-8944-430d-8284-f8e802357c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320713337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3320713337
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1023795203
Short name T169
Test name
Test status
Simulation time 3314768126 ps
CPU time 2.49 seconds
Started Apr 21 01:54:55 PM PDT 24
Finished Apr 21 01:54:58 PM PDT 24
Peak memory 202116 kb
Host smart-70f194cc-2c25-4c5b-a596-257e0e72d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023795203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1023795203
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3042765144
Short name T498
Test name
Test status
Simulation time 5729105278 ps
CPU time 4.21 seconds
Started Apr 21 01:54:30 PM PDT 24
Finished Apr 21 01:54:35 PM PDT 24
Peak memory 202076 kb
Host smart-70c5b665-33d3-4f41-910d-b4541e4c7623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042765144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3042765144
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3203790674
Short name T636
Test name
Test status
Simulation time 6140344391 ps
CPU time 10.6 seconds
Started Apr 21 01:55:03 PM PDT 24
Finished Apr 21 01:55:14 PM PDT 24
Peak memory 202132 kb
Host smart-d40650fb-2425-4c07-904b-82d1c2c5f62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203790674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3203790674
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.651198660
Short name T18
Test name
Test status
Simulation time 139491870012 ps
CPU time 230 seconds
Started Apr 21 01:55:05 PM PDT 24
Finished Apr 21 01:58:55 PM PDT 24
Peak memory 210592 kb
Host smart-3242e282-1907-45d1-b899-cdfdeae8e074
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651198660 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.651198660
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3832363605
Short name T652
Test name
Test status
Simulation time 524936238 ps
CPU time 0.75 seconds
Started Apr 21 01:55:19 PM PDT 24
Finished Apr 21 01:55:20 PM PDT 24
Peak memory 201976 kb
Host smart-30727a94-4771-4db7-804a-fbe3a3870c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832363605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3832363605
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1657250532
Short name T639
Test name
Test status
Simulation time 372002519260 ps
CPU time 447.13 seconds
Started Apr 21 01:55:16 PM PDT 24
Finished Apr 21 02:02:44 PM PDT 24
Peak memory 202344 kb
Host smart-fe357d6c-419a-410a-a6c3-dd0ede2d4665
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657250532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1657250532
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.475838084
Short name T365
Test name
Test status
Simulation time 570823726648 ps
CPU time 347.42 seconds
Started Apr 21 01:55:17 PM PDT 24
Finished Apr 21 02:01:05 PM PDT 24
Peak memory 202252 kb
Host smart-925ca816-f116-435d-b912-15d2bc8f7322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475838084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.475838084
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.595945705
Short name T795
Test name
Test status
Simulation time 163917068572 ps
CPU time 379.8 seconds
Started Apr 21 01:55:13 PM PDT 24
Finished Apr 21 02:01:33 PM PDT 24
Peak memory 202220 kb
Host smart-abb074b4-0b49-4143-a02f-66c31ebdb682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595945705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.595945705
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.194401115
Short name T504
Test name
Test status
Simulation time 332809843013 ps
CPU time 787 seconds
Started Apr 21 01:55:12 PM PDT 24
Finished Apr 21 02:08:19 PM PDT 24
Peak memory 202192 kb
Host smart-70175d3e-707c-42c4-bd27-062a9e954b98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=194401115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.194401115
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1729479113
Short name T174
Test name
Test status
Simulation time 165855146816 ps
CPU time 71.53 seconds
Started Apr 21 01:55:07 PM PDT 24
Finished Apr 21 01:56:19 PM PDT 24
Peak memory 202252 kb
Host smart-62250d04-4aed-4961-b76b-b4dfc8976771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729479113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1729479113
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2925848660
Short name T643
Test name
Test status
Simulation time 167508365369 ps
CPU time 96.08 seconds
Started Apr 21 01:55:10 PM PDT 24
Finished Apr 21 01:56:46 PM PDT 24
Peak memory 202244 kb
Host smart-2aec4bbb-ceac-4a3c-9a65-23e916fabdf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925848660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2925848660
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2201263235
Short name T771
Test name
Test status
Simulation time 602593381926 ps
CPU time 364.79 seconds
Started Apr 21 01:55:12 PM PDT 24
Finished Apr 21 02:01:17 PM PDT 24
Peak memory 202200 kb
Host smart-0b641538-5a4f-4951-808a-81b0f78fb2d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201263235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2201263235
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1287637620
Short name T653
Test name
Test status
Simulation time 110766931834 ps
CPU time 396.44 seconds
Started Apr 21 01:55:21 PM PDT 24
Finished Apr 21 02:01:57 PM PDT 24
Peak memory 202616 kb
Host smart-479bfcd5-4bff-4252-a1ce-36cdad1b4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287637620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1287637620
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.514179389
Short name T721
Test name
Test status
Simulation time 32739133622 ps
CPU time 18.39 seconds
Started Apr 21 01:55:19 PM PDT 24
Finished Apr 21 01:55:37 PM PDT 24
Peak memory 202064 kb
Host smart-80f79e51-4a97-4cb0-8f51-2da6eb11fcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514179389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.514179389
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3771387103
Short name T494
Test name
Test status
Simulation time 4743375011 ps
CPU time 10.98 seconds
Started Apr 21 01:55:17 PM PDT 24
Finished Apr 21 01:55:28 PM PDT 24
Peak memory 202076 kb
Host smart-433f9e43-8a2e-4faa-bb88-03aa8c03ff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771387103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3771387103
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.475303076
Short name T500
Test name
Test status
Simulation time 5792665714 ps
CPU time 13 seconds
Started Apr 21 01:55:07 PM PDT 24
Finished Apr 21 01:55:20 PM PDT 24
Peak memory 202080 kb
Host smart-c745223a-31f0-4c05-8dbb-fb721a40bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475303076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.475303076
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1408883899
Short name T634
Test name
Test status
Simulation time 208039629643 ps
CPU time 248.07 seconds
Started Apr 21 01:55:21 PM PDT 24
Finished Apr 21 01:59:29 PM PDT 24
Peak memory 202260 kb
Host smart-0e402355-6ad6-4648-94d2-594c4ab3046c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408883899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1408883899
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2033797185
Short name T690
Test name
Test status
Simulation time 42772426832 ps
CPU time 48.17 seconds
Started Apr 21 01:55:21 PM PDT 24
Finished Apr 21 01:56:09 PM PDT 24
Peak memory 202364 kb
Host smart-5fca8d4d-b5b3-4a45-a743-768c80700223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033797185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2033797185
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1176280413
Short name T780
Test name
Test status
Simulation time 531975680 ps
CPU time 0.89 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 01:55:33 PM PDT 24
Peak memory 201980 kb
Host smart-41425697-21e1-4657-a37e-2b32e5828bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176280413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1176280413
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2211436803
Short name T28
Test name
Test status
Simulation time 168646006952 ps
CPU time 354.8 seconds
Started Apr 21 01:55:25 PM PDT 24
Finished Apr 21 02:01:20 PM PDT 24
Peak memory 202284 kb
Host smart-00b87e52-17bd-45c3-9f78-2482c311ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211436803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2211436803
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1498008742
Short name T144
Test name
Test status
Simulation time 326658554167 ps
CPU time 361.22 seconds
Started Apr 21 01:55:24 PM PDT 24
Finished Apr 21 02:01:25 PM PDT 24
Peak memory 202320 kb
Host smart-0b4b59b9-ad2e-4dab-bc6f-211a65fbf572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498008742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1498008742
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2320842992
Short name T170
Test name
Test status
Simulation time 170307611450 ps
CPU time 208.52 seconds
Started Apr 21 01:55:28 PM PDT 24
Finished Apr 21 01:58:57 PM PDT 24
Peak memory 202272 kb
Host smart-7f015c3e-efa6-450d-aac3-5b466111a473
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320842992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2320842992
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3104534862
Short name T36
Test name
Test status
Simulation time 490232459163 ps
CPU time 1075.64 seconds
Started Apr 21 01:55:22 PM PDT 24
Finished Apr 21 02:13:18 PM PDT 24
Peak memory 202348 kb
Host smart-1be6210f-b725-460b-a05e-203e57679818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104534862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3104534862
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3090225479
Short name T419
Test name
Test status
Simulation time 162863648922 ps
CPU time 178.41 seconds
Started Apr 21 01:55:22 PM PDT 24
Finished Apr 21 01:58:20 PM PDT 24
Peak memory 202216 kb
Host smart-0a3a41a0-636a-489b-be43-bae00c43b8a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090225479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3090225479
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3129591116
Short name T274
Test name
Test status
Simulation time 371279370427 ps
CPU time 443.89 seconds
Started Apr 21 01:55:24 PM PDT 24
Finished Apr 21 02:02:48 PM PDT 24
Peak memory 202316 kb
Host smart-c1e5d4d5-3228-40b3-a738-36ba5d3ca108
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129591116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3129591116
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1172908656
Short name T566
Test name
Test status
Simulation time 584298242802 ps
CPU time 113.51 seconds
Started Apr 21 01:55:25 PM PDT 24
Finished Apr 21 01:57:19 PM PDT 24
Peak memory 202196 kb
Host smart-9743d330-cdf9-4e74-a8ad-64719262161c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172908656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1172908656
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1734334722
Short name T754
Test name
Test status
Simulation time 103809685718 ps
CPU time 577.31 seconds
Started Apr 21 01:55:25 PM PDT 24
Finished Apr 21 02:05:02 PM PDT 24
Peak memory 202588 kb
Host smart-53d151b1-a914-4f84-a1da-53552e288316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734334722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1734334722
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.842419706
Short name T505
Test name
Test status
Simulation time 38809443597 ps
CPU time 23.01 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 01:55:55 PM PDT 24
Peak memory 202064 kb
Host smart-7389be60-35f2-40d7-b107-9ea670c45521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842419706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.842419706
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2626205829
Short name T674
Test name
Test status
Simulation time 3642032086 ps
CPU time 7.98 seconds
Started Apr 21 01:55:26 PM PDT 24
Finished Apr 21 01:55:34 PM PDT 24
Peak memory 202044 kb
Host smart-e253cc35-8566-4b4a-b437-b35933d2200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626205829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2626205829
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2660882251
Short name T379
Test name
Test status
Simulation time 5989506624 ps
CPU time 8.43 seconds
Started Apr 21 01:55:21 PM PDT 24
Finished Apr 21 01:55:29 PM PDT 24
Peak memory 202068 kb
Host smart-3a7df637-250c-4fd3-ac75-e4b5b540abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660882251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2660882251
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3161886007
Short name T207
Test name
Test status
Simulation time 332119212 ps
CPU time 0.81 seconds
Started Apr 21 01:55:38 PM PDT 24
Finished Apr 21 01:55:39 PM PDT 24
Peak memory 201972 kb
Host smart-b090bbd3-2d08-46e0-a5dc-839d82fba87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161886007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3161886007
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3963161066
Short name T212
Test name
Test status
Simulation time 331934158750 ps
CPU time 182.95 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 01:58:34 PM PDT 24
Peak memory 202348 kb
Host smart-7bbd4579-bb8f-41ca-9e38-6a590969d011
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963161066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3963161066
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3714727021
Short name T177
Test name
Test status
Simulation time 491613773726 ps
CPU time 1087.98 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 02:13:40 PM PDT 24
Peak memory 202264 kb
Host smart-97f29657-0313-4fb5-a6ed-1eac6bf2e1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714727021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3714727021
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1366881294
Short name T559
Test name
Test status
Simulation time 328456950255 ps
CPU time 152.98 seconds
Started Apr 21 01:55:28 PM PDT 24
Finished Apr 21 01:58:01 PM PDT 24
Peak memory 202244 kb
Host smart-79044c23-9b0f-400d-a35c-51f305c617fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366881294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1366881294
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3012383775
Short name T316
Test name
Test status
Simulation time 493017461276 ps
CPU time 536.26 seconds
Started Apr 21 01:55:28 PM PDT 24
Finished Apr 21 02:04:24 PM PDT 24
Peak memory 202224 kb
Host smart-d2ef0cec-cbf9-41a3-b945-b51446f7ea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012383775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3012383775
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.4272928834
Short name T709
Test name
Test status
Simulation time 501559116511 ps
CPU time 165.14 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 01:58:17 PM PDT 24
Peak memory 202228 kb
Host smart-df845af5-e7e2-4d6b-ac84-9cce4a4c93e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272928834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.4272928834
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3605858170
Short name T87
Test name
Test status
Simulation time 560057276581 ps
CPU time 1291.2 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 02:17:02 PM PDT 24
Peak memory 202240 kb
Host smart-be63d44f-8ff7-4169-bc66-73f7362f8d9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605858170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3605858170
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2666669958
Short name T557
Test name
Test status
Simulation time 206333519796 ps
CPU time 118.53 seconds
Started Apr 21 01:55:32 PM PDT 24
Finished Apr 21 01:57:31 PM PDT 24
Peak memory 202212 kb
Host smart-cecae112-9c3c-4032-9640-ff4e0a3acd81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666669958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2666669958
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3001466521
Short name T371
Test name
Test status
Simulation time 131012027074 ps
CPU time 692.64 seconds
Started Apr 21 01:55:33 PM PDT 24
Finished Apr 21 02:07:06 PM PDT 24
Peak memory 202648 kb
Host smart-635669c6-381c-467a-be65-9d2e37fa1377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001466521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3001466521
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1671740090
Short name T27
Test name
Test status
Simulation time 36458849370 ps
CPU time 8.22 seconds
Started Apr 21 01:55:33 PM PDT 24
Finished Apr 21 01:55:41 PM PDT 24
Peak memory 202120 kb
Host smart-10acc46a-afb8-41a5-8b14-e0b1b185993f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671740090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1671740090
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3509446498
Short name T747
Test name
Test status
Simulation time 5242980350 ps
CPU time 12.03 seconds
Started Apr 21 01:55:31 PM PDT 24
Finished Apr 21 01:55:43 PM PDT 24
Peak memory 202072 kb
Host smart-c4671b84-6adc-4f11-91d8-bcb2033b8e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509446498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3509446498
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2282840061
Short name T83
Test name
Test status
Simulation time 6098706203 ps
CPU time 14.61 seconds
Started Apr 21 01:55:28 PM PDT 24
Finished Apr 21 01:55:43 PM PDT 24
Peak memory 202060 kb
Host smart-fb9ef0ee-077a-4f68-9682-57aa2ad40be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282840061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2282840061
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2378149425
Short name T33
Test name
Test status
Simulation time 11612497211 ps
CPU time 32.15 seconds
Started Apr 21 01:55:33 PM PDT 24
Finished Apr 21 01:56:05 PM PDT 24
Peak memory 210888 kb
Host smart-3ddf474d-26ec-4e54-9ab4-0a91767385cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378149425 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2378149425
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.4236435903
Short name T243
Test name
Test status
Simulation time 187685321993 ps
CPU time 397.27 seconds
Started Apr 21 01:55:36 PM PDT 24
Finished Apr 21 02:02:14 PM PDT 24
Peak memory 202348 kb
Host smart-9ee72950-949d-4a09-9c0d-08f8cffd522e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236435903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.4236435903
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1923560164
Short name T438
Test name
Test status
Simulation time 253891503331 ps
CPU time 602.32 seconds
Started Apr 21 01:55:36 PM PDT 24
Finished Apr 21 02:05:39 PM PDT 24
Peak memory 202272 kb
Host smart-e034fbe9-0ccf-4cb1-a85d-e8e54892d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923560164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1923560164
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3421677772
Short name T159
Test name
Test status
Simulation time 334086988739 ps
CPU time 79.89 seconds
Started Apr 21 01:55:37 PM PDT 24
Finished Apr 21 01:56:57 PM PDT 24
Peak memory 202264 kb
Host smart-f45156a1-d5b2-4846-8723-e5facf755f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421677772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3421677772
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2598841794
Short name T450
Test name
Test status
Simulation time 158993571186 ps
CPU time 197.7 seconds
Started Apr 21 01:55:36 PM PDT 24
Finished Apr 21 01:58:54 PM PDT 24
Peak memory 202228 kb
Host smart-92ec59ef-08c9-4e85-91f9-4cafea8ffd04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598841794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2598841794
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3951494073
Short name T286
Test name
Test status
Simulation time 492870139799 ps
CPU time 272.24 seconds
Started Apr 21 01:55:33 PM PDT 24
Finished Apr 21 02:00:06 PM PDT 24
Peak memory 202252 kb
Host smart-2046a524-8060-44b9-a8e5-6860ad804138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951494073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3951494073
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2461258505
Short name T393
Test name
Test status
Simulation time 164939210201 ps
CPU time 389.71 seconds
Started Apr 21 01:55:37 PM PDT 24
Finished Apr 21 02:02:07 PM PDT 24
Peak memory 202276 kb
Host smart-737da93c-f2c8-4b89-98c1-a4b6ef880352
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461258505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2461258505
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.479452365
Short name T363
Test name
Test status
Simulation time 537770443056 ps
CPU time 545.54 seconds
Started Apr 21 01:55:36 PM PDT 24
Finished Apr 21 02:04:42 PM PDT 24
Peak memory 202292 kb
Host smart-004cc660-f9fb-47b9-9d64-61eb918cc0de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479452365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.479452365
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.265007562
Short name T664
Test name
Test status
Simulation time 601273062902 ps
CPU time 331.23 seconds
Started Apr 21 01:55:36 PM PDT 24
Finished Apr 21 02:01:08 PM PDT 24
Peak memory 202224 kb
Host smart-d68bdbc9-f18f-4526-a852-22ec6cab1b4e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265007562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.265007562
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.606874304
Short name T726
Test name
Test status
Simulation time 77290086936 ps
CPU time 310.12 seconds
Started Apr 21 01:55:39 PM PDT 24
Finished Apr 21 02:00:50 PM PDT 24
Peak memory 202660 kb
Host smart-48ae1fc1-20df-49e9-886c-bf5ce6601268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606874304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.606874304
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.377804098
Short name T6
Test name
Test status
Simulation time 39782505079 ps
CPU time 96.18 seconds
Started Apr 21 01:55:41 PM PDT 24
Finished Apr 21 01:57:17 PM PDT 24
Peak memory 202068 kb
Host smart-ffd6fad1-9897-4ebf-a68e-8c140ca1c55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377804098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.377804098
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.854874720
Short name T485
Test name
Test status
Simulation time 3848255596 ps
CPU time 9.78 seconds
Started Apr 21 01:55:41 PM PDT 24
Finished Apr 21 01:55:51 PM PDT 24
Peak memory 202076 kb
Host smart-9934d80f-5af0-43d7-b4b8-1843f07b6c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854874720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.854874720
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3712702326
Short name T524
Test name
Test status
Simulation time 5878162212 ps
CPU time 3.58 seconds
Started Apr 21 01:55:33 PM PDT 24
Finished Apr 21 01:55:37 PM PDT 24
Peak memory 202080 kb
Host smart-9bb01d02-1757-4a72-a075-0525a1f37877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712702326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3712702326
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.770249388
Short name T241
Test name
Test status
Simulation time 196713414230 ps
CPU time 115.06 seconds
Started Apr 21 01:55:41 PM PDT 24
Finished Apr 21 01:57:37 PM PDT 24
Peak memory 202272 kb
Host smart-f3a7754c-5508-495f-8943-2375164b94a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770249388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
770249388
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2997532119
Short name T612
Test name
Test status
Simulation time 24678838254 ps
CPU time 55.46 seconds
Started Apr 21 01:55:39 PM PDT 24
Finished Apr 21 01:56:34 PM PDT 24
Peak memory 212376 kb
Host smart-9ee5ae0d-496a-4fd3-9469-adc5e431e81b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997532119 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2997532119
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1251233628
Short name T628
Test name
Test status
Simulation time 384565721 ps
CPU time 0.74 seconds
Started Apr 21 01:55:54 PM PDT 24
Finished Apr 21 01:55:55 PM PDT 24
Peak memory 201924 kb
Host smart-54d2f663-e764-4b94-956a-26e61f345814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251233628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1251233628
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1111369372
Short name T217
Test name
Test status
Simulation time 362250316696 ps
CPU time 232.6 seconds
Started Apr 21 01:55:51 PM PDT 24
Finished Apr 21 01:59:44 PM PDT 24
Peak memory 202268 kb
Host smart-4b33dfdb-46e6-4291-98fb-be94990f32e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111369372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1111369372
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1431762042
Short name T630
Test name
Test status
Simulation time 167668006838 ps
CPU time 46.59 seconds
Started Apr 21 01:55:44 PM PDT 24
Finished Apr 21 01:56:31 PM PDT 24
Peak memory 202244 kb
Host smart-8fb7e75f-d285-4667-b09f-f6552408b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431762042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1431762042
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3805624868
Short name T784
Test name
Test status
Simulation time 163083318750 ps
CPU time 104.96 seconds
Started Apr 21 01:55:45 PM PDT 24
Finished Apr 21 01:57:30 PM PDT 24
Peak memory 202268 kb
Host smart-1b440907-63b4-48db-95f3-da435f7239cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805624868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3805624868
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.758429435
Short name T631
Test name
Test status
Simulation time 161588986797 ps
CPU time 398.25 seconds
Started Apr 21 01:55:45 PM PDT 24
Finished Apr 21 02:02:24 PM PDT 24
Peak memory 202268 kb
Host smart-fcf1ae57-4dac-45d2-bc72-896616916bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758429435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.758429435
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2599727538
Short name T443
Test name
Test status
Simulation time 165003457316 ps
CPU time 186.49 seconds
Started Apr 21 01:55:49 PM PDT 24
Finished Apr 21 01:58:56 PM PDT 24
Peak memory 202188 kb
Host smart-3216cbc6-030d-4791-a2b0-97dcbd28917e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599727538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2599727538
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1821390159
Short name T338
Test name
Test status
Simulation time 425131993840 ps
CPU time 280.94 seconds
Started Apr 21 01:55:47 PM PDT 24
Finished Apr 21 02:00:29 PM PDT 24
Peak memory 202240 kb
Host smart-c4558abc-4004-48c7-acb0-e1d223eb64e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821390159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1821390159
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.453009390
Short name T775
Test name
Test status
Simulation time 198187243719 ps
CPU time 433.32 seconds
Started Apr 21 01:55:47 PM PDT 24
Finished Apr 21 02:03:01 PM PDT 24
Peak memory 202220 kb
Host smart-2b2e4bb2-7d1d-406c-bf02-eae335301bc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453009390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.453009390
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.33278270
Short name T456
Test name
Test status
Simulation time 70140236355 ps
CPU time 361.26 seconds
Started Apr 21 01:55:55 PM PDT 24
Finished Apr 21 02:01:56 PM PDT 24
Peak memory 202656 kb
Host smart-e8d5963d-1af6-435e-be0e-78d0d5b51704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33278270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.33278270
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3760541401
Short name T722
Test name
Test status
Simulation time 32659744095 ps
CPU time 19.37 seconds
Started Apr 21 01:55:51 PM PDT 24
Finished Apr 21 01:56:10 PM PDT 24
Peak memory 202044 kb
Host smart-be721345-41a2-4fd3-a673-427308ba65f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760541401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3760541401
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.182247523
Short name T386
Test name
Test status
Simulation time 3463898285 ps
CPU time 3.02 seconds
Started Apr 21 01:55:51 PM PDT 24
Finished Apr 21 01:55:55 PM PDT 24
Peak memory 202076 kb
Host smart-71d546ab-ce34-4d14-95d8-bb265ed21acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182247523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.182247523
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3188048716
Short name T597
Test name
Test status
Simulation time 6046599461 ps
CPU time 4.43 seconds
Started Apr 21 01:55:43 PM PDT 24
Finished Apr 21 01:55:48 PM PDT 24
Peak memory 202060 kb
Host smart-1ac2fce4-5271-4d84-9897-34fdc67d26a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188048716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3188048716
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3791218364
Short name T594
Test name
Test status
Simulation time 272011258297 ps
CPU time 959.87 seconds
Started Apr 21 01:55:50 PM PDT 24
Finished Apr 21 02:11:51 PM PDT 24
Peak memory 212640 kb
Host smart-c3f9b741-4e25-4724-aef8-115702e6d6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791218364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3791218364
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2322694312
Short name T570
Test name
Test status
Simulation time 383800474 ps
CPU time 0.82 seconds
Started Apr 21 01:56:02 PM PDT 24
Finished Apr 21 01:56:03 PM PDT 24
Peak memory 201928 kb
Host smart-b2b3cd97-fc44-4ab2-9801-e43a7b28c1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322694312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2322694312
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2815439539
Short name T512
Test name
Test status
Simulation time 329765486020 ps
CPU time 775.93 seconds
Started Apr 21 01:55:53 PM PDT 24
Finished Apr 21 02:08:49 PM PDT 24
Peak memory 202212 kb
Host smart-cb91f209-d746-4e14-b457-8240a6722653
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815439539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2815439539
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2527762008
Short name T405
Test name
Test status
Simulation time 162047920388 ps
CPU time 198.75 seconds
Started Apr 21 01:55:52 PM PDT 24
Finished Apr 21 01:59:11 PM PDT 24
Peak memory 202248 kb
Host smart-d5bc6298-ac2c-436b-9156-c5fd8f1a71c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527762008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2527762008
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4153851937
Short name T729
Test name
Test status
Simulation time 495306095430 ps
CPU time 1168.98 seconds
Started Apr 21 01:55:56 PM PDT 24
Finished Apr 21 02:15:25 PM PDT 24
Peak memory 202236 kb
Host smart-767be836-1b8f-4542-924b-4ab7f393ea24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153851937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4153851937
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.884041853
Short name T521
Test name
Test status
Simulation time 589683813455 ps
CPU time 350 seconds
Started Apr 21 01:55:56 PM PDT 24
Finished Apr 21 02:01:46 PM PDT 24
Peak memory 202224 kb
Host smart-8da512d0-0627-4b0b-85c3-ee1ab734c37d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884041853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.884041853
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2009779906
Short name T739
Test name
Test status
Simulation time 111701669018 ps
CPU time 467.86 seconds
Started Apr 21 01:56:11 PM PDT 24
Finished Apr 21 02:03:59 PM PDT 24
Peak memory 202560 kb
Host smart-27290cb8-2e2c-4eb3-8c7c-ed5ee177cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009779906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2009779906
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3829574558
Short name T573
Test name
Test status
Simulation time 45487584616 ps
CPU time 55.35 seconds
Started Apr 21 01:55:59 PM PDT 24
Finished Apr 21 01:56:54 PM PDT 24
Peak memory 202072 kb
Host smart-3d31516e-2045-4f16-a19b-27f12b322782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829574558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3829574558
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2417116650
Short name T106
Test name
Test status
Simulation time 5338652469 ps
CPU time 3.44 seconds
Started Apr 21 01:56:11 PM PDT 24
Finished Apr 21 01:56:14 PM PDT 24
Peak memory 202068 kb
Host smart-a5c7ca98-e8ff-4ca7-9751-a1dc2935aa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417116650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2417116650
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.966663160
Short name T171
Test name
Test status
Simulation time 5950421113 ps
CPU time 14.18 seconds
Started Apr 21 01:55:51 PM PDT 24
Finished Apr 21 01:56:06 PM PDT 24
Peak memory 202056 kb
Host smart-a7e3a910-4f7b-405f-b0f5-4269968e55e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966663160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.966663160
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.626492069
Short name T687
Test name
Test status
Simulation time 385673334036 ps
CPU time 201.54 seconds
Started Apr 21 01:56:02 PM PDT 24
Finished Apr 21 01:59:24 PM PDT 24
Peak memory 202196 kb
Host smart-aa9bfae1-7207-45ad-8f4e-66ecb36ec4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626492069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
626492069
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3597864931
Short name T37
Test name
Test status
Simulation time 156812651069 ps
CPU time 96.22 seconds
Started Apr 21 01:56:01 PM PDT 24
Finished Apr 21 01:57:37 PM PDT 24
Peak memory 202380 kb
Host smart-d12fa887-be66-45c0-b805-70b1f14df8e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597864931 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3597864931
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.810736050
Short name T689
Test name
Test status
Simulation time 476477590 ps
CPU time 1.16 seconds
Started Apr 21 01:56:06 PM PDT 24
Finished Apr 21 01:56:07 PM PDT 24
Peak memory 201968 kb
Host smart-449c7b20-0b23-4034-b0d4-5662c4b1fb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810736050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.810736050
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1687384512
Short name T782
Test name
Test status
Simulation time 164914228163 ps
CPU time 373.61 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 02:02:26 PM PDT 24
Peak memory 202240 kb
Host smart-0945cbb1-1787-46f3-b9d4-4c10e6544abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687384512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1687384512
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.688700222
Short name T166
Test name
Test status
Simulation time 327729079774 ps
CPU time 816.62 seconds
Started Apr 21 01:56:03 PM PDT 24
Finished Apr 21 02:09:40 PM PDT 24
Peak memory 202320 kb
Host smart-63055683-82e5-4a1d-a230-81518deda956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688700222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.688700222
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1101722331
Short name T519
Test name
Test status
Simulation time 325994854944 ps
CPU time 206.38 seconds
Started Apr 21 01:56:00 PM PDT 24
Finished Apr 21 01:59:27 PM PDT 24
Peak memory 202216 kb
Host smart-a927c7ed-9847-428d-9efe-95282ffad03a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101722331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1101722331
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2758351159
Short name T596
Test name
Test status
Simulation time 332521805897 ps
CPU time 208.39 seconds
Started Apr 21 01:56:02 PM PDT 24
Finished Apr 21 01:59:30 PM PDT 24
Peak memory 202252 kb
Host smart-f1aea384-e8b3-4c8f-9486-0c622c023411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758351159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2758351159
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.4161477456
Short name T717
Test name
Test status
Simulation time 161430771035 ps
CPU time 219.54 seconds
Started Apr 21 01:56:01 PM PDT 24
Finished Apr 21 01:59:41 PM PDT 24
Peak memory 202236 kb
Host smart-1e2a8e52-4ae4-452c-a429-b8ba364594aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161477456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.4161477456
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1062206082
Short name T277
Test name
Test status
Simulation time 196956725108 ps
CPU time 116.58 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 01:58:09 PM PDT 24
Peak memory 202336 kb
Host smart-eae4157a-feac-4abd-b75a-fc5c30a9e499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062206082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1062206082
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3040111550
Short name T400
Test name
Test status
Simulation time 603939114962 ps
CPU time 658.28 seconds
Started Apr 21 01:56:03 PM PDT 24
Finished Apr 21 02:07:02 PM PDT 24
Peak memory 202124 kb
Host smart-41c34f9e-edbe-4740-89d8-91c47b5f178b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040111550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3040111550
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1929662446
Short name T757
Test name
Test status
Simulation time 30325591438 ps
CPU time 36.85 seconds
Started Apr 21 01:56:06 PM PDT 24
Finished Apr 21 01:56:44 PM PDT 24
Peak memory 202100 kb
Host smart-1dc5e45d-197e-4962-85d3-fe7ac58f4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929662446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1929662446
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3888317277
Short name T411
Test name
Test status
Simulation time 3194046323 ps
CPU time 4.4 seconds
Started Apr 21 01:55:59 PM PDT 24
Finished Apr 21 01:56:04 PM PDT 24
Peak memory 202032 kb
Host smart-b0876edc-1c48-4822-af38-d082194eed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888317277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3888317277
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.975734862
Short name T497
Test name
Test status
Simulation time 5961494165 ps
CPU time 4.54 seconds
Started Apr 21 01:55:59 PM PDT 24
Finished Apr 21 01:56:04 PM PDT 24
Peak memory 202080 kb
Host smart-aaf9b4c7-598d-4d32-adc0-88ed54f161cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975734862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.975734862
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2849013883
Short name T225
Test name
Test status
Simulation time 254424347435 ps
CPU time 349.21 seconds
Started Apr 21 01:56:05 PM PDT 24
Finished Apr 21 02:01:55 PM PDT 24
Peak memory 210896 kb
Host smart-85971d94-a723-4df0-8dde-7a3699984b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849013883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2849013883
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3987401156
Short name T99
Test name
Test status
Simulation time 21715031443 ps
CPU time 102.84 seconds
Started Apr 21 01:56:05 PM PDT 24
Finished Apr 21 01:57:49 PM PDT 24
Peak memory 210960 kb
Host smart-43481f54-60bf-4360-99c0-1aa3e4c61568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987401156 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3987401156
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.365677743
Short name T437
Test name
Test status
Simulation time 301343015 ps
CPU time 0.98 seconds
Started Apr 21 01:56:08 PM PDT 24
Finished Apr 21 01:56:09 PM PDT 24
Peak memory 201968 kb
Host smart-0bc98b50-06ae-430b-9eb4-baf3b6ab5f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365677743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.365677743
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3063361924
Short name T248
Test name
Test status
Simulation time 165997693271 ps
CPU time 24.41 seconds
Started Apr 21 01:56:07 PM PDT 24
Finished Apr 21 01:56:32 PM PDT 24
Peak memory 202268 kb
Host smart-ed2a48d2-eb11-48cc-82e8-e7dd3245b144
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063361924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3063361924
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.618029295
Short name T778
Test name
Test status
Simulation time 326285333673 ps
CPU time 51.81 seconds
Started Apr 21 01:56:08 PM PDT 24
Finished Apr 21 01:57:00 PM PDT 24
Peak memory 202276 kb
Host smart-b8bb9b0a-b6dc-4c1f-ba52-4a4ce1e70245
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=618029295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.618029295
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3480914438
Short name T627
Test name
Test status
Simulation time 335049391028 ps
CPU time 709.25 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 02:08:02 PM PDT 24
Peak memory 202304 kb
Host smart-85c94d13-bb5d-410a-8c6f-7546b81c0092
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480914438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3480914438
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2607571949
Short name T294
Test name
Test status
Simulation time 588315138500 ps
CPU time 1373.12 seconds
Started Apr 21 01:56:07 PM PDT 24
Finished Apr 21 02:19:01 PM PDT 24
Peak memory 202156 kb
Host smart-56aef814-f970-4aab-bd93-c47e47c761e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607571949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2607571949
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2402982663
Short name T569
Test name
Test status
Simulation time 190518136576 ps
CPU time 435.65 seconds
Started Apr 21 01:56:08 PM PDT 24
Finished Apr 21 02:03:24 PM PDT 24
Peak memory 202220 kb
Host smart-460ea03f-0819-4840-9036-7e4b39888a61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402982663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2402982663
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4226968689
Short name T42
Test name
Test status
Simulation time 71809551687 ps
CPU time 399.51 seconds
Started Apr 21 01:56:08 PM PDT 24
Finished Apr 21 02:02:48 PM PDT 24
Peak memory 202568 kb
Host smart-6a2c9885-80e3-46ac-a60d-6f1d396d2518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226968689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4226968689
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2951954945
Short name T677
Test name
Test status
Simulation time 23185268531 ps
CPU time 57.35 seconds
Started Apr 21 01:56:09 PM PDT 24
Finished Apr 21 01:57:07 PM PDT 24
Peak memory 202068 kb
Host smart-e5b5189c-a03f-45e3-8689-5646aedea26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951954945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2951954945
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2813648692
Short name T416
Test name
Test status
Simulation time 5456810234 ps
CPU time 7.72 seconds
Started Apr 21 01:56:11 PM PDT 24
Finished Apr 21 01:56:19 PM PDT 24
Peak memory 202064 kb
Host smart-194fd9ce-6dc2-4b67-9afe-f03caeed5dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813648692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2813648692
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1507111102
Short name T448
Test name
Test status
Simulation time 6092278247 ps
CPU time 4.73 seconds
Started Apr 21 01:56:05 PM PDT 24
Finished Apr 21 01:56:10 PM PDT 24
Peak memory 202088 kb
Host smart-9f6b4dcc-20c9-4af8-a384-c8f84a60a9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507111102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1507111102
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2932114059
Short name T605
Test name
Test status
Simulation time 281222810707 ps
CPU time 921.01 seconds
Started Apr 21 01:56:08 PM PDT 24
Finished Apr 21 02:11:30 PM PDT 24
Peak memory 202632 kb
Host smart-b58354f0-0138-4d46-a1a9-b68810f1dab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932114059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2932114059
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.583594285
Short name T637
Test name
Test status
Simulation time 314631718 ps
CPU time 1 seconds
Started Apr 21 01:52:15 PM PDT 24
Finished Apr 21 01:52:16 PM PDT 24
Peak memory 201740 kb
Host smart-d1c7dcab-ee96-4a26-a035-3b8934d262cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583594285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.583594285
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1871505395
Short name T658
Test name
Test status
Simulation time 220521203347 ps
CPU time 29.61 seconds
Started Apr 21 01:52:11 PM PDT 24
Finished Apr 21 01:52:41 PM PDT 24
Peak memory 202204 kb
Host smart-178f505a-781a-4eab-8abb-25b4f88ae725
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871505395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1871505395
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1403360679
Short name T712
Test name
Test status
Simulation time 191278748728 ps
CPU time 80.46 seconds
Started Apr 21 01:52:13 PM PDT 24
Finished Apr 21 01:53:33 PM PDT 24
Peak memory 202296 kb
Host smart-d2410ed4-05b6-4dd7-a48c-65ab63802c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403360679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1403360679
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1531137374
Short name T184
Test name
Test status
Simulation time 163197158994 ps
CPU time 100.24 seconds
Started Apr 21 01:52:12 PM PDT 24
Finished Apr 21 01:53:53 PM PDT 24
Peak memory 202304 kb
Host smart-3d52baa6-a981-446a-acf2-a3e0c7982f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531137374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1531137374
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3029692173
Short name T414
Test name
Test status
Simulation time 168538445086 ps
CPU time 105.71 seconds
Started Apr 21 01:52:20 PM PDT 24
Finished Apr 21 01:54:06 PM PDT 24
Peak memory 202176 kb
Host smart-d3fb2a5a-bc26-4fdf-9479-56fea618a062
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029692173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3029692173
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2390575902
Short name T695
Test name
Test status
Simulation time 331189020078 ps
CPU time 816.66 seconds
Started Apr 21 01:52:13 PM PDT 24
Finished Apr 21 02:05:50 PM PDT 24
Peak memory 202256 kb
Host smart-2c1020c9-dee2-43e3-aef9-fa6494902cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390575902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2390575902
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2382584252
Short name T759
Test name
Test status
Simulation time 164334489622 ps
CPU time 63.8 seconds
Started Apr 21 01:52:11 PM PDT 24
Finished Apr 21 01:53:15 PM PDT 24
Peak memory 202356 kb
Host smart-285d70eb-d8bb-4f84-8d50-4833689d3ac6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382584252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2382584252
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2873209923
Short name T214
Test name
Test status
Simulation time 412737560625 ps
CPU time 242.86 seconds
Started Apr 21 01:52:12 PM PDT 24
Finished Apr 21 01:56:15 PM PDT 24
Peak memory 202260 kb
Host smart-0509951d-8d4b-4ccd-89ac-f8a417087737
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873209923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2873209923
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3457066508
Short name T772
Test name
Test status
Simulation time 79468788327 ps
CPU time 436.04 seconds
Started Apr 21 01:52:27 PM PDT 24
Finished Apr 21 01:59:44 PM PDT 24
Peak memory 202592 kb
Host smart-63199635-c3ce-4362-aad6-9992fcf9ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457066508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3457066508
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2035917552
Short name T699
Test name
Test status
Simulation time 40586654378 ps
CPU time 6.24 seconds
Started Apr 21 01:52:16 PM PDT 24
Finished Apr 21 01:52:22 PM PDT 24
Peak memory 202068 kb
Host smart-f00bff98-eebd-40a1-ba96-73057481588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035917552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2035917552
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.899326078
Short name T523
Test name
Test status
Simulation time 5081885162 ps
CPU time 3.34 seconds
Started Apr 21 01:52:13 PM PDT 24
Finished Apr 21 01:52:16 PM PDT 24
Peak memory 202060 kb
Host smart-86b555a4-6395-44da-9c86-90bf82bccb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899326078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.899326078
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.366463457
Short name T68
Test name
Test status
Simulation time 8647108234 ps
CPU time 2.06 seconds
Started Apr 21 01:52:14 PM PDT 24
Finished Apr 21 01:52:16 PM PDT 24
Peak memory 218840 kb
Host smart-11bc0581-a0b6-465a-91fe-810854c2ddd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366463457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.366463457
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1367899790
Short name T490
Test name
Test status
Simulation time 6109822647 ps
CPU time 15.85 seconds
Started Apr 21 01:52:09 PM PDT 24
Finished Apr 21 01:52:25 PM PDT 24
Peak memory 202032 kb
Host smart-b4e71b60-5367-46cf-b850-740df5fb14c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367899790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1367899790
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3693354123
Short name T647
Test name
Test status
Simulation time 168244262931 ps
CPU time 102.46 seconds
Started Apr 21 01:52:15 PM PDT 24
Finished Apr 21 01:53:58 PM PDT 24
Peak memory 202156 kb
Host smart-b535ba1f-15d7-4f25-863c-391467ad47bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693354123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3693354123
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2099712130
Short name T100
Test name
Test status
Simulation time 61752830826 ps
CPU time 126.22 seconds
Started Apr 21 01:52:16 PM PDT 24
Finished Apr 21 01:54:23 PM PDT 24
Peak memory 210624 kb
Host smart-f4f2e5ea-07f2-4514-9430-cd51856ff444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099712130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2099712130
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3293075026
Short name T684
Test name
Test status
Simulation time 322776278 ps
CPU time 1.35 seconds
Started Apr 21 01:56:15 PM PDT 24
Finished Apr 21 01:56:17 PM PDT 24
Peak memory 201976 kb
Host smart-87bf404b-e040-42e7-85c4-aee2e0b961ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293075026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3293075026
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.660771875
Short name T337
Test name
Test status
Simulation time 325080393461 ps
CPU time 387.55 seconds
Started Apr 21 01:56:11 PM PDT 24
Finished Apr 21 02:02:39 PM PDT 24
Peak memory 202264 kb
Host smart-395bb7a6-52c0-41b3-8c80-15f1f4911773
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660771875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.660771875
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.866987179
Short name T84
Test name
Test status
Simulation time 350840229619 ps
CPU time 781.51 seconds
Started Apr 21 01:56:15 PM PDT 24
Finished Apr 21 02:09:17 PM PDT 24
Peak memory 202252 kb
Host smart-deeb9050-224f-4d5a-8334-0c618d7cfa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866987179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.866987179
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3430897918
Short name T522
Test name
Test status
Simulation time 168415922603 ps
CPU time 114.07 seconds
Started Apr 21 01:56:16 PM PDT 24
Finished Apr 21 01:58:10 PM PDT 24
Peak memory 202244 kb
Host smart-0ec5f670-c8d1-4163-b260-8b20ca31d3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430897918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3430897918
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3437400195
Short name T714
Test name
Test status
Simulation time 162047884876 ps
CPU time 102.99 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 01:57:55 PM PDT 24
Peak memory 202292 kb
Host smart-902a8e8c-8f80-4424-b638-341e17b8e22a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437400195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3437400195
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1911030136
Short name T696
Test name
Test status
Simulation time 163154816381 ps
CPU time 171.61 seconds
Started Apr 21 01:56:17 PM PDT 24
Finished Apr 21 01:59:09 PM PDT 24
Peak memory 202252 kb
Host smart-d6a27262-cb4c-4686-96a0-ccc1293e206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911030136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1911030136
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2587979466
Short name T134
Test name
Test status
Simulation time 486525240775 ps
CPU time 1145.23 seconds
Started Apr 21 01:56:10 PM PDT 24
Finished Apr 21 02:15:15 PM PDT 24
Peak memory 202228 kb
Host smart-e4b238ee-ac4d-416b-9fbd-b8ba4e3beb4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587979466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2587979466
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3368640276
Short name T663
Test name
Test status
Simulation time 181468356249 ps
CPU time 403.45 seconds
Started Apr 21 01:56:12 PM PDT 24
Finished Apr 21 02:02:56 PM PDT 24
Peak memory 202268 kb
Host smart-47d5cccf-05f4-46d7-9d39-4411ba9ca6ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368640276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3368640276
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2166591574
Short name T447
Test name
Test status
Simulation time 609431092690 ps
CPU time 1475.98 seconds
Started Apr 21 01:56:10 PM PDT 24
Finished Apr 21 02:20:47 PM PDT 24
Peak memory 202184 kb
Host smart-41b77bc4-9c49-485f-9c42-5109c29ac582
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166591574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2166591574
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3017631363
Short name T172
Test name
Test status
Simulation time 103794522369 ps
CPU time 556.26 seconds
Started Apr 21 01:56:18 PM PDT 24
Finished Apr 21 02:05:34 PM PDT 24
Peak memory 202568 kb
Host smart-5ee5c797-9009-421d-96d2-46e4f987194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017631363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3017631363
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1408723482
Short name T478
Test name
Test status
Simulation time 22157820623 ps
CPU time 13.16 seconds
Started Apr 21 01:56:14 PM PDT 24
Finished Apr 21 01:56:27 PM PDT 24
Peak memory 202088 kb
Host smart-ade72c59-b109-448f-b707-9bf5d170cda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408723482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1408723482
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1700728306
Short name T462
Test name
Test status
Simulation time 4632447663 ps
CPU time 12.6 seconds
Started Apr 21 01:56:14 PM PDT 24
Finished Apr 21 01:56:27 PM PDT 24
Peak memory 201976 kb
Host smart-f02d3530-c6f4-4c3b-a876-671c143c2ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700728306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1700728306
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2568579888
Short name T132
Test name
Test status
Simulation time 5832898823 ps
CPU time 3.32 seconds
Started Apr 21 01:56:11 PM PDT 24
Finished Apr 21 01:56:15 PM PDT 24
Peak memory 202080 kb
Host smart-9bdc0002-ee46-4643-ab6c-17616f3c6df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568579888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2568579888
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.294122176
Short name T510
Test name
Test status
Simulation time 207717889739 ps
CPU time 480.61 seconds
Started Apr 21 01:56:15 PM PDT 24
Finished Apr 21 02:04:16 PM PDT 24
Peak memory 202220 kb
Host smart-b4855b6c-eaf5-467a-8f03-eac3588a77cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294122176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
294122176
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.742540906
Short name T314
Test name
Test status
Simulation time 61488911568 ps
CPU time 68.24 seconds
Started Apr 21 01:56:14 PM PDT 24
Finished Apr 21 01:57:22 PM PDT 24
Peak memory 210564 kb
Host smart-c1da4c41-7e0e-44e6-8e44-ab46484130a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742540906 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.742540906
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1226656100
Short name T525
Test name
Test status
Simulation time 384458720 ps
CPU time 0.84 seconds
Started Apr 21 01:56:20 PM PDT 24
Finished Apr 21 01:56:21 PM PDT 24
Peak memory 201984 kb
Host smart-9200d592-de4c-4dd4-9e09-8ecc19af6900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226656100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1226656100
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.4156088841
Short name T349
Test name
Test status
Simulation time 344978808886 ps
CPU time 643.96 seconds
Started Apr 21 01:56:20 PM PDT 24
Finished Apr 21 02:07:04 PM PDT 24
Peak memory 202256 kb
Host smart-dcae2139-92e6-4cc7-a013-4a0777432f6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156088841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.4156088841
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2958808183
Short name T273
Test name
Test status
Simulation time 500992169380 ps
CPU time 269.17 seconds
Started Apr 21 01:56:20 PM PDT 24
Finished Apr 21 02:00:49 PM PDT 24
Peak memory 202268 kb
Host smart-6b0b73e1-e384-457e-bed7-d3ad2de04572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958808183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2958808183
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1282026307
Short name T750
Test name
Test status
Simulation time 319296353463 ps
CPU time 777.2 seconds
Started Apr 21 01:56:17 PM PDT 24
Finished Apr 21 02:09:15 PM PDT 24
Peak memory 202256 kb
Host smart-d958f2b7-9951-4a5b-ab39-e214972e80cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282026307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1282026307
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1516339406
Short name T186
Test name
Test status
Simulation time 328158444786 ps
CPU time 176.58 seconds
Started Apr 21 01:56:17 PM PDT 24
Finished Apr 21 01:59:14 PM PDT 24
Peak memory 202184 kb
Host smart-03faaf34-f087-4b10-800b-fca215fbbec0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516339406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1516339406
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2849834652
Short name T679
Test name
Test status
Simulation time 332868995063 ps
CPU time 195.65 seconds
Started Apr 21 01:56:13 PM PDT 24
Finished Apr 21 01:59:29 PM PDT 24
Peak memory 202248 kb
Host smart-93d92e17-3eae-40de-acee-e3add8930f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849834652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2849834652
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3802740568
Short name T763
Test name
Test status
Simulation time 328098349563 ps
CPU time 819.21 seconds
Started Apr 21 01:56:15 PM PDT 24
Finished Apr 21 02:09:54 PM PDT 24
Peak memory 202208 kb
Host smart-20723b79-8535-4968-a000-0297a078c087
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802740568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3802740568
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.809498449
Short name T427
Test name
Test status
Simulation time 382461562182 ps
CPU time 859.45 seconds
Started Apr 21 01:56:19 PM PDT 24
Finished Apr 21 02:10:38 PM PDT 24
Peak memory 202236 kb
Host smart-84be2e9c-45e3-45b5-b283-0dccb07b24c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809498449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.809498449
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.720542043
Short name T682
Test name
Test status
Simulation time 42504423131 ps
CPU time 17.82 seconds
Started Apr 21 01:56:21 PM PDT 24
Finished Apr 21 01:56:39 PM PDT 24
Peak memory 202084 kb
Host smart-29a39a00-8df4-4622-bdb5-0b4d3b4921d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720542043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.720542043
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3155666515
Short name T471
Test name
Test status
Simulation time 4244348256 ps
CPU time 5.53 seconds
Started Apr 21 01:56:19 PM PDT 24
Finished Apr 21 01:56:25 PM PDT 24
Peak memory 202064 kb
Host smart-48af62cf-fd39-4628-9c4a-cf29dcaab811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155666515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3155666515
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1185915798
Short name T492
Test name
Test status
Simulation time 5670806654 ps
CPU time 6.94 seconds
Started Apr 21 01:56:17 PM PDT 24
Finished Apr 21 01:56:24 PM PDT 24
Peak memory 202076 kb
Host smart-aba844b8-4312-4422-90b0-1654a0aa16b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185915798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1185915798
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3675871877
Short name T736
Test name
Test status
Simulation time 1668760304905 ps
CPU time 1240.39 seconds
Started Apr 21 01:56:21 PM PDT 24
Finished Apr 21 02:17:01 PM PDT 24
Peak memory 210772 kb
Host smart-7c9fc555-41b3-4015-a237-d17d5d9d600b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675871877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3675871877
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.779088824
Short name T285
Test name
Test status
Simulation time 233935864182 ps
CPU time 123.96 seconds
Started Apr 21 01:56:18 PM PDT 24
Finished Apr 21 01:58:22 PM PDT 24
Peak memory 218664 kb
Host smart-cfe9c57f-e640-4364-85f0-368ae519193a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779088824 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.779088824
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3165970332
Short name T587
Test name
Test status
Simulation time 467596578 ps
CPU time 1.59 seconds
Started Apr 21 01:56:25 PM PDT 24
Finished Apr 21 01:56:27 PM PDT 24
Peak memory 201976 kb
Host smart-927fb02a-a847-4ddf-a839-d7c59047e721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165970332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3165970332
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.771590926
Short name T362
Test name
Test status
Simulation time 484085832290 ps
CPU time 901.92 seconds
Started Apr 21 01:56:23 PM PDT 24
Finished Apr 21 02:11:25 PM PDT 24
Peak memory 202256 kb
Host smart-4c2d7318-edf9-4f3c-a5eb-f29590e219d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771590926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.771590926
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1850444969
Short name T590
Test name
Test status
Simulation time 498826431118 ps
CPU time 1161.52 seconds
Started Apr 21 01:56:24 PM PDT 24
Finished Apr 21 02:15:46 PM PDT 24
Peak memory 202336 kb
Host smart-c031bcae-3777-4854-866d-e119a6ad2dca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850444969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1850444969
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2090789694
Short name T649
Test name
Test status
Simulation time 166713185833 ps
CPU time 357.68 seconds
Started Apr 21 01:56:23 PM PDT 24
Finished Apr 21 02:02:21 PM PDT 24
Peak memory 202236 kb
Host smart-35ad8a1e-09a8-414d-8452-84e860453ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090789694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2090789694
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2445590296
Short name T793
Test name
Test status
Simulation time 484731928387 ps
CPU time 1196.94 seconds
Started Apr 21 01:56:24 PM PDT 24
Finished Apr 21 02:16:21 PM PDT 24
Peak memory 202248 kb
Host smart-1e2c8388-ccc6-4d56-ac39-e9ad972999bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445590296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2445590296
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.4193844688
Short name T746
Test name
Test status
Simulation time 403990543089 ps
CPU time 867.96 seconds
Started Apr 21 01:56:26 PM PDT 24
Finished Apr 21 02:10:54 PM PDT 24
Peak memory 202212 kb
Host smart-72874858-5da2-46f3-88bf-dafcf0d5e016
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193844688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.4193844688
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2295564975
Short name T738
Test name
Test status
Simulation time 130131950772 ps
CPU time 533.4 seconds
Started Apr 21 01:56:24 PM PDT 24
Finished Apr 21 02:05:18 PM PDT 24
Peak memory 202612 kb
Host smart-57d18923-7144-4f17-86d8-b7720bf02c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295564975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2295564975
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3217728261
Short name T762
Test name
Test status
Simulation time 37381491944 ps
CPU time 20.87 seconds
Started Apr 21 01:56:25 PM PDT 24
Finished Apr 21 01:56:47 PM PDT 24
Peak memory 202256 kb
Host smart-88bfa747-327d-4ae5-bcf8-7a521d12d4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217728261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3217728261
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2408311681
Short name T700
Test name
Test status
Simulation time 4209073576 ps
CPU time 2.3 seconds
Started Apr 21 01:56:25 PM PDT 24
Finished Apr 21 01:56:28 PM PDT 24
Peak memory 202068 kb
Host smart-32364c52-1e1c-40d0-97f6-dd42f8531266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408311681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2408311681
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1995695293
Short name T167
Test name
Test status
Simulation time 5992250374 ps
CPU time 2.74 seconds
Started Apr 21 01:56:24 PM PDT 24
Finished Apr 21 01:56:27 PM PDT 24
Peak memory 202076 kb
Host smart-e4bc7b78-6624-49a8-8fd3-afecd18d75c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995695293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1995695293
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.284295116
Short name T138
Test name
Test status
Simulation time 384684148517 ps
CPU time 237.46 seconds
Started Apr 21 01:56:24 PM PDT 24
Finished Apr 21 02:00:22 PM PDT 24
Peak memory 202248 kb
Host smart-ec4172d1-7b0d-4a18-9a48-68df3150b39f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284295116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
284295116
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1541511665
Short name T580
Test name
Test status
Simulation time 208034368184 ps
CPU time 211.38 seconds
Started Apr 21 01:56:25 PM PDT 24
Finished Apr 21 01:59:56 PM PDT 24
Peak memory 218384 kb
Host smart-fa6bfd88-056e-4159-b947-d759901a2dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541511665 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1541511665
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2591701770
Short name T654
Test name
Test status
Simulation time 490537867 ps
CPU time 1.68 seconds
Started Apr 21 01:56:35 PM PDT 24
Finished Apr 21 01:56:37 PM PDT 24
Peak memory 201972 kb
Host smart-f49b3ac7-86ad-4e36-a886-27c99b60b033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591701770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2591701770
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2296660716
Short name T181
Test name
Test status
Simulation time 345410806793 ps
CPU time 798.26 seconds
Started Apr 21 01:56:36 PM PDT 24
Finished Apr 21 02:09:55 PM PDT 24
Peak memory 202264 kb
Host smart-a4af3706-f085-4261-88d7-a0fc3708c188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296660716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2296660716
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2039804323
Short name T271
Test name
Test status
Simulation time 328722205128 ps
CPU time 784.47 seconds
Started Apr 21 01:56:28 PM PDT 24
Finished Apr 21 02:09:33 PM PDT 24
Peak memory 202244 kb
Host smart-fbbdfb4b-a16f-49a2-ac42-cc98dc794e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039804323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2039804323
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4102883213
Short name T449
Test name
Test status
Simulation time 495237622340 ps
CPU time 1251.56 seconds
Started Apr 21 01:56:35 PM PDT 24
Finished Apr 21 02:17:27 PM PDT 24
Peak memory 202220 kb
Host smart-b52c4506-ccee-4a45-ba85-134b41fff18d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102883213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4102883213
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3523603267
Short name T158
Test name
Test status
Simulation time 327339119977 ps
CPU time 146.18 seconds
Started Apr 21 01:56:26 PM PDT 24
Finished Apr 21 01:58:53 PM PDT 24
Peak memory 202320 kb
Host smart-ccebceef-f5c3-420a-91e0-8cad2ec8b5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523603267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3523603267
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1274757017
Short name T205
Test name
Test status
Simulation time 487554646894 ps
CPU time 90.96 seconds
Started Apr 21 01:56:35 PM PDT 24
Finished Apr 21 01:58:06 PM PDT 24
Peak memory 202192 kb
Host smart-dfd2d1b1-0e44-453b-9269-03e4216fb410
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274757017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1274757017
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.883798233
Short name T143
Test name
Test status
Simulation time 603033503727 ps
CPU time 179.5 seconds
Started Apr 21 01:56:35 PM PDT 24
Finished Apr 21 01:59:35 PM PDT 24
Peak memory 202200 kb
Host smart-f32adcdb-9376-4837-ad3a-a05f11435d48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883798233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.883798233
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4144787971
Short name T781
Test name
Test status
Simulation time 139201561114 ps
CPU time 492.83 seconds
Started Apr 21 01:56:36 PM PDT 24
Finished Apr 21 02:04:49 PM PDT 24
Peak memory 202568 kb
Host smart-63f0ad44-c4be-43f4-be9a-c6f9a59ccddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144787971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4144787971
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1279669545
Short name T196
Test name
Test status
Simulation time 39511836167 ps
CPU time 16.62 seconds
Started Apr 21 01:56:36 PM PDT 24
Finished Apr 21 01:56:53 PM PDT 24
Peak memory 202068 kb
Host smart-6a4cc579-cbf5-49fe-ae25-6e8179af6cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279669545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1279669545
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.827693589
Short name T604
Test name
Test status
Simulation time 5303757946 ps
CPU time 6.85 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 01:56:45 PM PDT 24
Peak memory 202064 kb
Host smart-2262c4cb-a62a-41ee-9e80-37b65a7edaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827693589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.827693589
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2122327795
Short name T693
Test name
Test status
Simulation time 5886811109 ps
CPU time 1.68 seconds
Started Apr 21 01:56:25 PM PDT 24
Finished Apr 21 01:56:28 PM PDT 24
Peak memory 202108 kb
Host smart-10b5ffc3-014e-4d3d-ae37-13e37dcf5d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122327795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2122327795
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.446610024
Short name T372
Test name
Test status
Simulation time 308680287821 ps
CPU time 971 seconds
Started Apr 21 01:56:33 PM PDT 24
Finished Apr 21 02:12:44 PM PDT 24
Peak memory 210796 kb
Host smart-f6a1540c-c93d-488b-8d98-7efe492af82c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446610024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
446610024
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.394848595
Short name T21
Test name
Test status
Simulation time 126133722721 ps
CPU time 126.73 seconds
Started Apr 21 01:56:34 PM PDT 24
Finished Apr 21 01:58:41 PM PDT 24
Peak memory 210952 kb
Host smart-34f38610-3a5e-489f-8b99-33746628c3be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394848595 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.394848595
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.503725254
Short name T520
Test name
Test status
Simulation time 462381997 ps
CPU time 0.85 seconds
Started Apr 21 01:56:39 PM PDT 24
Finished Apr 21 01:56:40 PM PDT 24
Peak memory 201976 kb
Host smart-a245df10-851d-4bc7-95ca-58895d5dee72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503725254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.503725254
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.4188748292
Short name T354
Test name
Test status
Simulation time 176677603464 ps
CPU time 51.02 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 01:57:29 PM PDT 24
Peak memory 202352 kb
Host smart-e9cb81ac-aaca-4808-9b96-8fe24f7b5299
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188748292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.4188748292
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.296153799
Short name T553
Test name
Test status
Simulation time 497081134957 ps
CPU time 679.39 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 02:07:58 PM PDT 24
Peak memory 202272 kb
Host smart-7ec0c406-a969-481d-9390-9346699219a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296153799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.296153799
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2517464203
Short name T408
Test name
Test status
Simulation time 329009824259 ps
CPU time 411.18 seconds
Started Apr 21 01:56:41 PM PDT 24
Finished Apr 21 02:03:32 PM PDT 24
Peak memory 202224 kb
Host smart-2e01a35a-9e4f-4274-92e2-72d7cc4c295d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517464203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2517464203
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.259424792
Short name T150
Test name
Test status
Simulation time 493417473900 ps
CPU time 261.07 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 02:00:59 PM PDT 24
Peak memory 202228 kb
Host smart-9fabc30d-4b30-4163-927d-f3bd4a5dc5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259424792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.259424792
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3366084238
Short name T589
Test name
Test status
Simulation time 497799358666 ps
CPU time 378.03 seconds
Started Apr 21 01:56:36 PM PDT 24
Finished Apr 21 02:02:55 PM PDT 24
Peak memory 202236 kb
Host smart-d0cb5b75-bb1a-471c-8290-aa3951ce285b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366084238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3366084238
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3127739235
Short name T329
Test name
Test status
Simulation time 178715834531 ps
CPU time 412.36 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 02:03:31 PM PDT 24
Peak memory 202324 kb
Host smart-2766811f-a7bf-4ecc-87cc-4f92bc21f7bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127739235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3127739235
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3658322391
Short name T602
Test name
Test status
Simulation time 200055859632 ps
CPU time 435.22 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 02:03:53 PM PDT 24
Peak memory 202192 kb
Host smart-2099bd81-45cd-44ee-96cd-3c6e77f0e145
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658322391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3658322391
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1417888205
Short name T399
Test name
Test status
Simulation time 45366351736 ps
CPU time 105.18 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 01:58:24 PM PDT 24
Peak memory 202052 kb
Host smart-88bddd32-5173-4f32-9b82-3696d366d823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417888205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1417888205
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2839730347
Short name T571
Test name
Test status
Simulation time 4217691617 ps
CPU time 10.63 seconds
Started Apr 21 01:56:40 PM PDT 24
Finished Apr 21 01:56:51 PM PDT 24
Peak memory 202076 kb
Host smart-06bfd357-321f-4fcf-852f-a66f0c887e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839730347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2839730347
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1742594646
Short name T623
Test name
Test status
Simulation time 6018363491 ps
CPU time 7.67 seconds
Started Apr 21 01:56:34 PM PDT 24
Finished Apr 21 01:56:42 PM PDT 24
Peak memory 202112 kb
Host smart-31c98935-5881-48fb-913a-637f9aac2616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742594646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1742594646
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1471582931
Short name T323
Test name
Test status
Simulation time 185589343151 ps
CPU time 415.52 seconds
Started Apr 21 01:56:39 PM PDT 24
Finished Apr 21 02:03:35 PM PDT 24
Peak memory 202304 kb
Host smart-4bc9bd7b-d6bd-4691-988b-96aa3bb9db54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471582931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1471582931
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.576577759
Short name T40
Test name
Test status
Simulation time 32770252503 ps
CPU time 148.27 seconds
Started Apr 21 01:56:40 PM PDT 24
Finished Apr 21 01:59:09 PM PDT 24
Peak memory 210964 kb
Host smart-4ab474fa-7bb8-4192-9006-3e6eb1cb52cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576577759 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.576577759
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2117844577
Short name T432
Test name
Test status
Simulation time 506460249 ps
CPU time 0.91 seconds
Started Apr 21 01:56:44 PM PDT 24
Finished Apr 21 01:56:46 PM PDT 24
Peak memory 201988 kb
Host smart-aaf62259-71f7-4746-aebf-8302e2943a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117844577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2117844577
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.569799581
Short name T351
Test name
Test status
Simulation time 342534031377 ps
CPU time 336.32 seconds
Started Apr 21 01:56:42 PM PDT 24
Finished Apr 21 02:02:19 PM PDT 24
Peak memory 202260 kb
Host smart-5f91a1ea-8eb2-49fc-86a2-c4e62c1447e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569799581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.569799581
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.922022409
Short name T164
Test name
Test status
Simulation time 555680641726 ps
CPU time 111.15 seconds
Started Apr 21 01:56:42 PM PDT 24
Finished Apr 21 01:58:34 PM PDT 24
Peak memory 202352 kb
Host smart-d4e8bb1b-014e-41d2-aa43-5408ea06ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922022409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.922022409
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3827636492
Short name T578
Test name
Test status
Simulation time 487610922117 ps
CPU time 262.98 seconds
Started Apr 21 01:56:40 PM PDT 24
Finished Apr 21 02:01:03 PM PDT 24
Peak memory 202240 kb
Host smart-84a20e41-6a62-41ae-87b3-ae2c47d0699c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827636492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3827636492
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.826025508
Short name T766
Test name
Test status
Simulation time 489698008781 ps
CPU time 410.57 seconds
Started Apr 21 01:56:38 PM PDT 24
Finished Apr 21 02:03:29 PM PDT 24
Peak memory 202260 kb
Host smart-7c663a47-2559-4497-b7b4-34efb01fc6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826025508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.826025508
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3230898410
Short name T1
Test name
Test status
Simulation time 334286640525 ps
CPU time 812.76 seconds
Started Apr 21 01:56:41 PM PDT 24
Finished Apr 21 02:10:14 PM PDT 24
Peak memory 202296 kb
Host smart-63d89c52-ad5c-4387-a0ab-8835bab3dd4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230898410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3230898410
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.512524767
Short name T187
Test name
Test status
Simulation time 178376569420 ps
CPU time 71.79 seconds
Started Apr 21 01:56:39 PM PDT 24
Finished Apr 21 01:57:51 PM PDT 24
Peak memory 202332 kb
Host smart-2b168864-955b-4252-bacf-35a0ed8956e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512524767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.512524767
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.4006465802
Short name T401
Test name
Test status
Simulation time 599503928721 ps
CPU time 692.07 seconds
Started Apr 21 01:56:44 PM PDT 24
Finished Apr 21 02:08:17 PM PDT 24
Peak memory 202200 kb
Host smart-3616b8f7-aca5-4488-8da5-754f9ab0c266
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006465802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.4006465802
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2594965874
Short name T238
Test name
Test status
Simulation time 135976086039 ps
CPU time 397.28 seconds
Started Apr 21 01:56:45 PM PDT 24
Finished Apr 21 02:03:22 PM PDT 24
Peak memory 202568 kb
Host smart-64b268aa-8de5-4e48-8e74-4a46a66541e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594965874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2594965874
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3122537888
Short name T489
Test name
Test status
Simulation time 26776593859 ps
CPU time 3.76 seconds
Started Apr 21 01:56:43 PM PDT 24
Finished Apr 21 01:56:47 PM PDT 24
Peak memory 202100 kb
Host smart-e04b6f67-de4e-4e1c-9cde-3670701fd9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122537888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3122537888
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.644902228
Short name T439
Test name
Test status
Simulation time 5028505169 ps
CPU time 6.88 seconds
Started Apr 21 01:56:42 PM PDT 24
Finished Apr 21 01:56:49 PM PDT 24
Peak memory 202080 kb
Host smart-2ec10024-fbac-47cb-b3e0-4cc8d65b2619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644902228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.644902228
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3450036109
Short name T454
Test name
Test status
Simulation time 5998362299 ps
CPU time 15.29 seconds
Started Apr 21 01:56:41 PM PDT 24
Finished Apr 21 01:56:57 PM PDT 24
Peak memory 202080 kb
Host smart-71572513-87b6-4f86-a30c-7f1013e6cc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450036109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3450036109
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1584122009
Short name T199
Test name
Test status
Simulation time 530713035419 ps
CPU time 299.64 seconds
Started Apr 21 01:56:46 PM PDT 24
Finished Apr 21 02:01:46 PM PDT 24
Peak memory 202256 kb
Host smart-2fe4e085-e994-4e2c-88c9-82d5704bdba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584122009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1584122009
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.4181039459
Short name T701
Test name
Test status
Simulation time 109145383947 ps
CPU time 241.66 seconds
Started Apr 21 01:56:46 PM PDT 24
Finished Apr 21 02:00:48 PM PDT 24
Peak memory 210948 kb
Host smart-be29935c-a21d-416f-b244-351863050df5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181039459 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.4181039459
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1821358988
Short name T436
Test name
Test status
Simulation time 337509149 ps
CPU time 0.79 seconds
Started Apr 21 01:56:54 PM PDT 24
Finished Apr 21 01:56:55 PM PDT 24
Peak memory 201984 kb
Host smart-61659a26-2689-45e3-97cc-f82c922a6a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821358988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1821358988
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.684979871
Short name T223
Test name
Test status
Simulation time 368082583338 ps
CPU time 133.93 seconds
Started Apr 21 01:56:54 PM PDT 24
Finished Apr 21 01:59:08 PM PDT 24
Peak memory 202268 kb
Host smart-c712b451-053b-4b7d-a4d0-9edb0d0ec558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684979871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.684979871
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2276058666
Short name T800
Test name
Test status
Simulation time 332247002782 ps
CPU time 228.73 seconds
Started Apr 21 01:56:49 PM PDT 24
Finished Apr 21 02:00:39 PM PDT 24
Peak memory 202276 kb
Host smart-8ecd9a59-9d8b-40da-9793-ff1fd0ada0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276058666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2276058666
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2146270962
Short name T599
Test name
Test status
Simulation time 160184183565 ps
CPU time 97.87 seconds
Started Apr 21 01:56:45 PM PDT 24
Finished Apr 21 01:58:23 PM PDT 24
Peak memory 202336 kb
Host smart-ca1e376c-6c43-460c-84d6-190c64f29888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146270962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2146270962
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.823494306
Short name T629
Test name
Test status
Simulation time 328929271034 ps
CPU time 800.19 seconds
Started Apr 21 01:56:44 PM PDT 24
Finished Apr 21 02:10:05 PM PDT 24
Peak memory 202336 kb
Host smart-9b0297bb-6cb7-43c3-a037-6ea011f04d42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=823494306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.823494306
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4228894498
Short name T331
Test name
Test status
Simulation time 347021952859 ps
CPU time 825.96 seconds
Started Apr 21 01:56:49 PM PDT 24
Finished Apr 21 02:10:35 PM PDT 24
Peak memory 202288 kb
Host smart-552f489d-5bd8-46f2-b6d4-844f00505571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228894498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4228894498
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1963699303
Short name T444
Test name
Test status
Simulation time 614729685852 ps
CPU time 1383.62 seconds
Started Apr 21 01:56:48 PM PDT 24
Finished Apr 21 02:19:52 PM PDT 24
Peak memory 202180 kb
Host smart-111e3989-a475-428d-a0ba-45dbec58e619
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963699303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1963699303
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2828182367
Short name T479
Test name
Test status
Simulation time 130233675831 ps
CPU time 592.8 seconds
Started Apr 21 01:56:53 PM PDT 24
Finished Apr 21 02:06:46 PM PDT 24
Peak memory 202556 kb
Host smart-c4acf2b8-09ec-4d1d-a210-837acdf52940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828182367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2828182367
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4077637952
Short name T397
Test name
Test status
Simulation time 28709240307 ps
CPU time 17.96 seconds
Started Apr 21 01:56:55 PM PDT 24
Finished Apr 21 01:57:13 PM PDT 24
Peak memory 202100 kb
Host smart-ccb5768f-3878-4b82-a90f-91954e32700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077637952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4077637952
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1503821762
Short name T387
Test name
Test status
Simulation time 3881666125 ps
CPU time 5.44 seconds
Started Apr 21 01:56:50 PM PDT 24
Finished Apr 21 01:56:56 PM PDT 24
Peak memory 201984 kb
Host smart-55427592-dce0-49a9-b155-d4b6de0e2f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503821762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1503821762
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2741287094
Short name T511
Test name
Test status
Simulation time 6004692842 ps
CPU time 3.26 seconds
Started Apr 21 01:56:48 PM PDT 24
Finished Apr 21 01:56:51 PM PDT 24
Peak memory 202044 kb
Host smart-a237cac7-154f-42f9-a05c-57953d10cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741287094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2741287094
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4070231866
Short name T261
Test name
Test status
Simulation time 221379587794 ps
CPU time 121.32 seconds
Started Apr 21 01:56:55 PM PDT 24
Finished Apr 21 01:58:57 PM PDT 24
Peak memory 202332 kb
Host smart-990b1ce9-5a0d-4491-ac73-cf4c9ebb9c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070231866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4070231866
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1286709272
Short name T564
Test name
Test status
Simulation time 24598398056 ps
CPU time 41.52 seconds
Started Apr 21 01:56:55 PM PDT 24
Finished Apr 21 01:57:37 PM PDT 24
Peak memory 202480 kb
Host smart-7b3bc015-56ad-4f70-a2a0-ea556ebbc30c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286709272 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1286709272
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2556069297
Short name T104
Test name
Test status
Simulation time 391904986 ps
CPU time 1.45 seconds
Started Apr 21 01:56:59 PM PDT 24
Finished Apr 21 01:57:01 PM PDT 24
Peak memory 201980 kb
Host smart-b8193e4e-0ec2-460c-bed9-8144f58a26a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556069297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2556069297
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1848373580
Short name T96
Test name
Test status
Simulation time 429871991567 ps
CPU time 472.18 seconds
Started Apr 21 01:56:57 PM PDT 24
Finished Apr 21 02:04:49 PM PDT 24
Peak memory 202300 kb
Host smart-b7f70b0f-47fc-4c33-ae31-14ea57d5d9fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848373580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1848373580
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4153938831
Short name T685
Test name
Test status
Simulation time 350430178428 ps
CPU time 184.39 seconds
Started Apr 21 01:56:57 PM PDT 24
Finished Apr 21 02:00:02 PM PDT 24
Peak memory 202256 kb
Host smart-08044a14-34b0-44f2-b2c7-e41db7d45fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153938831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4153938831
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.4197102588
Short name T582
Test name
Test status
Simulation time 161637468635 ps
CPU time 28.05 seconds
Started Apr 21 01:56:59 PM PDT 24
Finished Apr 21 01:57:27 PM PDT 24
Peak memory 202288 kb
Host smart-57417fed-3402-43a5-abf5-f3fa80dd7299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197102588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.4197102588
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1619097276
Short name T661
Test name
Test status
Simulation time 168302199849 ps
CPU time 31.59 seconds
Started Apr 21 01:56:58 PM PDT 24
Finished Apr 21 01:57:30 PM PDT 24
Peak memory 202212 kb
Host smart-0f450fd0-e437-4b1d-8804-0defa4801667
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619097276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1619097276
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2206962993
Short name T161
Test name
Test status
Simulation time 487036173192 ps
CPU time 210.88 seconds
Started Apr 21 01:56:55 PM PDT 24
Finished Apr 21 02:00:26 PM PDT 24
Peak memory 202248 kb
Host smart-203344c4-d73f-4bba-b178-b2e519a4fe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206962993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2206962993
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2614986558
Short name T474
Test name
Test status
Simulation time 494897421780 ps
CPU time 1118.81 seconds
Started Apr 21 01:56:54 PM PDT 24
Finished Apr 21 02:15:33 PM PDT 24
Peak memory 202252 kb
Host smart-df6687af-0e87-403d-b92d-1547d50662e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614986558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2614986558
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2837777408
Short name T487
Test name
Test status
Simulation time 226305334679 ps
CPU time 135.62 seconds
Started Apr 21 01:56:56 PM PDT 24
Finished Apr 21 01:59:12 PM PDT 24
Peak memory 202248 kb
Host smart-06415dcb-c490-431a-87c1-5ff4deb1095a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837777408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2837777408
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.668774210
Short name T429
Test name
Test status
Simulation time 195121402978 ps
CPU time 108.38 seconds
Started Apr 21 01:56:58 PM PDT 24
Finished Apr 21 01:58:46 PM PDT 24
Peak memory 202236 kb
Host smart-83dbca96-69af-454e-9011-f929b8373a8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668774210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.668774210
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2125351357
Short name T626
Test name
Test status
Simulation time 86209162365 ps
CPU time 475.66 seconds
Started Apr 21 01:57:01 PM PDT 24
Finished Apr 21 02:04:57 PM PDT 24
Peak memory 202600 kb
Host smart-9056551d-9538-4550-b4d0-724a0f4d411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125351357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2125351357
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1572776647
Short name T452
Test name
Test status
Simulation time 36247732920 ps
CPU time 23.84 seconds
Started Apr 21 01:56:59 PM PDT 24
Finished Apr 21 01:57:23 PM PDT 24
Peak memory 202108 kb
Host smart-8fb8686a-5b44-44cb-8216-d16c3ff6a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572776647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1572776647
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.651996872
Short name T396
Test name
Test status
Simulation time 2724328108 ps
CPU time 2.47 seconds
Started Apr 21 01:57:01 PM PDT 24
Finished Apr 21 01:57:04 PM PDT 24
Peak memory 202088 kb
Host smart-4f66a023-d61b-4719-ae8f-338bd56217d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651996872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.651996872
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4097859213
Short name T625
Test name
Test status
Simulation time 5730746196 ps
CPU time 6.35 seconds
Started Apr 21 01:56:54 PM PDT 24
Finished Apr 21 01:57:01 PM PDT 24
Peak memory 202072 kb
Host smart-6eb51fcd-c2fc-4273-a855-6ad2a6688ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097859213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4097859213
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3771295422
Short name T734
Test name
Test status
Simulation time 28204998737 ps
CPU time 43.87 seconds
Started Apr 21 01:57:01 PM PDT 24
Finished Apr 21 01:57:45 PM PDT 24
Peak memory 202120 kb
Host smart-20e02bcd-ce1e-4037-a247-0d2d7d3a0395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771295422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3771295422
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1695725572
Short name T785
Test name
Test status
Simulation time 1233317487597 ps
CPU time 325.23 seconds
Started Apr 21 01:57:00 PM PDT 24
Finished Apr 21 02:02:26 PM PDT 24
Peak memory 210976 kb
Host smart-e8434eb2-5429-4310-ad74-a9cf4ed75d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695725572 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1695725572
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3562066887
Short name T418
Test name
Test status
Simulation time 307460405 ps
CPU time 0.81 seconds
Started Apr 21 01:57:07 PM PDT 24
Finished Apr 21 01:57:08 PM PDT 24
Peak memory 201948 kb
Host smart-a75619ed-093a-40f6-8697-b999c910198a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562066887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3562066887
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.481196711
Short name T335
Test name
Test status
Simulation time 331806854479 ps
CPU time 206.67 seconds
Started Apr 21 01:57:02 PM PDT 24
Finished Apr 21 02:00:29 PM PDT 24
Peak memory 202272 kb
Host smart-012d0556-3263-44f5-8996-b770ac2c72a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481196711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.481196711
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1161710477
Short name T244
Test name
Test status
Simulation time 167222349433 ps
CPU time 98.62 seconds
Started Apr 21 01:57:02 PM PDT 24
Finished Apr 21 01:58:41 PM PDT 24
Peak memory 202276 kb
Host smart-6d4cf8dc-6fb6-4a28-a3a0-3df8a33e7f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161710477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1161710477
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.998765912
Short name T157
Test name
Test status
Simulation time 168582763334 ps
CPU time 37.24 seconds
Started Apr 21 01:57:03 PM PDT 24
Finished Apr 21 01:57:40 PM PDT 24
Peak memory 202188 kb
Host smart-7baa0442-4766-4918-bd95-a5f43b267bd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=998765912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.998765912
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2444297112
Short name T254
Test name
Test status
Simulation time 160571761395 ps
CPU time 202.95 seconds
Started Apr 21 01:57:04 PM PDT 24
Finished Apr 21 02:00:27 PM PDT 24
Peak memory 202256 kb
Host smart-8e87a9a6-500d-4cb3-b6fe-5670b0a3e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444297112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2444297112
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1065502769
Short name T659
Test name
Test status
Simulation time 325864638481 ps
CPU time 731.42 seconds
Started Apr 21 01:57:03 PM PDT 24
Finished Apr 21 02:09:14 PM PDT 24
Peak memory 202332 kb
Host smart-d0306a5a-acb1-43ec-b4e2-0b7328942a50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065502769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1065502769
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3336415822
Short name T2
Test name
Test status
Simulation time 369270486135 ps
CPU time 103.96 seconds
Started Apr 21 01:57:01 PM PDT 24
Finished Apr 21 01:58:45 PM PDT 24
Peak memory 202216 kb
Host smart-a00ef8ca-5630-45ec-af95-e9dda0120beb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336415822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3336415822
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3452960579
Short name T409
Test name
Test status
Simulation time 577959414466 ps
CPU time 687.28 seconds
Started Apr 21 01:57:01 PM PDT 24
Finished Apr 21 02:08:29 PM PDT 24
Peak memory 202208 kb
Host smart-f75f5d55-08e6-49a4-ba01-b22c385382b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452960579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3452960579
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3707982300
Short name T608
Test name
Test status
Simulation time 115333885698 ps
CPU time 533.27 seconds
Started Apr 21 01:57:04 PM PDT 24
Finished Apr 21 02:05:58 PM PDT 24
Peak memory 202608 kb
Host smart-7141571e-3fa5-41b2-8b45-026eb6a118d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707982300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3707982300
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4028128976
Short name T704
Test name
Test status
Simulation time 38011227524 ps
CPU time 23.08 seconds
Started Apr 21 01:57:08 PM PDT 24
Finished Apr 21 01:57:31 PM PDT 24
Peak memory 202044 kb
Host smart-e3cb081c-4db2-4601-b688-8b93394087f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028128976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4028128976
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.850022552
Short name T702
Test name
Test status
Simulation time 5227620862 ps
CPU time 12.04 seconds
Started Apr 21 01:57:04 PM PDT 24
Finished Apr 21 01:57:16 PM PDT 24
Peak memory 202076 kb
Host smart-a11d2093-23db-4b0c-9e80-dfedceb24f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850022552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.850022552
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.900996419
Short name T477
Test name
Test status
Simulation time 5621063123 ps
CPU time 4.94 seconds
Started Apr 21 01:57:02 PM PDT 24
Finished Apr 21 01:57:08 PM PDT 24
Peak memory 202088 kb
Host smart-5cb62f1e-8f41-462e-8eac-83810e8cf892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900996419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.900996419
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3652406870
Short name T253
Test name
Test status
Simulation time 339017467905 ps
CPU time 744.63 seconds
Started Apr 21 01:57:05 PM PDT 24
Finished Apr 21 02:09:30 PM PDT 24
Peak memory 202276 kb
Host smart-72c2ca57-0456-4235-83d2-4f79e96741e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652406870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3652406870
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2681260193
Short name T219
Test name
Test status
Simulation time 61355242141 ps
CPU time 28.63 seconds
Started Apr 21 01:57:06 PM PDT 24
Finished Apr 21 01:57:34 PM PDT 24
Peak memory 210568 kb
Host smart-81f5eee9-b66b-47ab-89a4-5c59d4844d14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681260193 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2681260193
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3016950163
Short name T591
Test name
Test status
Simulation time 392151225 ps
CPU time 0.91 seconds
Started Apr 21 01:57:11 PM PDT 24
Finished Apr 21 01:57:13 PM PDT 24
Peak memory 201980 kb
Host smart-dbb12458-879e-4795-807a-1d2662c3faa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016950163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3016950163
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3243187712
Short name T357
Test name
Test status
Simulation time 551442917163 ps
CPU time 870.3 seconds
Started Apr 21 01:57:12 PM PDT 24
Finished Apr 21 02:11:43 PM PDT 24
Peak memory 202260 kb
Host smart-06c6b2f4-f1e8-4294-838b-fb941c54c119
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243187712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3243187712
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.805483631
Short name T598
Test name
Test status
Simulation time 191987428963 ps
CPU time 105.09 seconds
Started Apr 21 01:57:11 PM PDT 24
Finished Apr 21 01:58:57 PM PDT 24
Peak memory 202260 kb
Host smart-1ee3e79e-9ae0-47de-98cd-26cb0f2c9e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805483631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.805483631
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3629349335
Short name T255
Test name
Test status
Simulation time 480643914177 ps
CPU time 279.56 seconds
Started Apr 21 01:57:05 PM PDT 24
Finished Apr 21 02:01:44 PM PDT 24
Peak memory 202244 kb
Host smart-2aee5bcd-95a8-45d5-8d90-d0f5e7f14555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629349335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3629349335
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.432698372
Short name T548
Test name
Test status
Simulation time 167507916163 ps
CPU time 97.97 seconds
Started Apr 21 01:57:08 PM PDT 24
Finished Apr 21 01:58:46 PM PDT 24
Peak memory 202180 kb
Host smart-1a1add1e-7e50-4de9-aa9b-5a8d371ab808
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=432698372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.432698372
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2120786221
Short name T180
Test name
Test status
Simulation time 315125049617 ps
CPU time 744.8 seconds
Started Apr 21 01:57:04 PM PDT 24
Finished Apr 21 02:09:29 PM PDT 24
Peak memory 202260 kb
Host smart-a2005e09-3d1a-4344-9c4a-a552451f24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120786221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2120786221
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1073051433
Short name T97
Test name
Test status
Simulation time 328642760867 ps
CPU time 116.45 seconds
Started Apr 21 01:57:08 PM PDT 24
Finished Apr 21 01:59:05 PM PDT 24
Peak memory 202292 kb
Host smart-f349e5e1-de12-43f2-8d91-1dfcb5f53ded
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073051433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1073051433
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2842694451
Short name T426
Test name
Test status
Simulation time 397069267458 ps
CPU time 99.81 seconds
Started Apr 21 01:57:07 PM PDT 24
Finished Apr 21 01:58:47 PM PDT 24
Peak memory 202492 kb
Host smart-e1b57cfb-d737-4987-8b06-d8e70b9a264e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842694451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2842694451
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.394259683
Short name T473
Test name
Test status
Simulation time 81142191160 ps
CPU time 404.84 seconds
Started Apr 21 01:57:10 PM PDT 24
Finished Apr 21 02:03:55 PM PDT 24
Peak memory 202644 kb
Host smart-71c98d99-6de2-4481-a873-1e55d395a058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394259683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.394259683
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4106535855
Short name T788
Test name
Test status
Simulation time 30506882368 ps
CPU time 72.38 seconds
Started Apr 21 01:57:11 PM PDT 24
Finished Apr 21 01:58:24 PM PDT 24
Peak memory 202104 kb
Host smart-70bbf1d5-d195-4440-9330-a87059079414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106535855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4106535855
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.509448115
Short name T558
Test name
Test status
Simulation time 5205894351 ps
CPU time 2.02 seconds
Started Apr 21 01:57:10 PM PDT 24
Finished Apr 21 01:57:12 PM PDT 24
Peak memory 202032 kb
Host smart-c312d94f-dc56-4f84-9a75-15b03ac8d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509448115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.509448115
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2157447084
Short name T453
Test name
Test status
Simulation time 5845327454 ps
CPU time 14.81 seconds
Started Apr 21 01:57:05 PM PDT 24
Finished Apr 21 01:57:20 PM PDT 24
Peak memory 202064 kb
Host smart-7a769318-1a74-463a-b7ec-83ce74306566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157447084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2157447084
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.803337594
Short name T13
Test name
Test status
Simulation time 334534887518 ps
CPU time 384.61 seconds
Started Apr 21 01:57:10 PM PDT 24
Finished Apr 21 02:03:35 PM PDT 24
Peak memory 202332 kb
Host smart-1e44c9d0-df38-4de6-89ce-1b906607ed8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803337594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
803337594
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.949917694
Short name T366
Test name
Test status
Simulation time 172522811577 ps
CPU time 53.05 seconds
Started Apr 21 01:57:10 PM PDT 24
Finished Apr 21 01:58:03 PM PDT 24
Peak memory 202360 kb
Host smart-80b859aa-5b1b-4dcc-8b70-7b3849f010d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949917694 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.949917694
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4143762451
Short name T741
Test name
Test status
Simulation time 451018062 ps
CPU time 1.15 seconds
Started Apr 21 01:52:23 PM PDT 24
Finished Apr 21 01:52:24 PM PDT 24
Peak memory 201896 kb
Host smart-c4a5776f-fe37-4183-b56d-e3f1a9bb212b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143762451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4143762451
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1727541015
Short name T279
Test name
Test status
Simulation time 486209303334 ps
CPU time 1125.03 seconds
Started Apr 21 01:52:21 PM PDT 24
Finished Apr 21 02:11:07 PM PDT 24
Peak memory 202248 kb
Host smart-ea6ef9e3-e80a-4a31-8933-49091f40aadf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727541015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1727541015
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.596663188
Short name T295
Test name
Test status
Simulation time 160524505666 ps
CPU time 94 seconds
Started Apr 21 01:52:25 PM PDT 24
Finished Apr 21 01:53:59 PM PDT 24
Peak memory 202268 kb
Host smart-b451186f-b42c-4452-b609-86254ec3594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596663188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.596663188
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.850630532
Short name T360
Test name
Test status
Simulation time 492907934841 ps
CPU time 707.46 seconds
Started Apr 21 01:52:17 PM PDT 24
Finished Apr 21 02:04:05 PM PDT 24
Peak memory 202272 kb
Host smart-48eef42b-f56b-49b6-ad14-e20a5002456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850630532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.850630532
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2891583751
Short name T779
Test name
Test status
Simulation time 485077258842 ps
CPU time 1175.37 seconds
Started Apr 21 01:52:22 PM PDT 24
Finished Apr 21 02:11:58 PM PDT 24
Peak memory 202272 kb
Host smart-e9f23585-a1f0-4ffa-b8cc-04e15cd3ed1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891583751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2891583751
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3654955820
Short name T472
Test name
Test status
Simulation time 326945839471 ps
CPU time 198.75 seconds
Started Apr 21 01:52:17 PM PDT 24
Finished Apr 21 01:55:35 PM PDT 24
Peak memory 202340 kb
Host smart-9795edbe-e3fb-4e95-84ad-1b53d96ddf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654955820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3654955820
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.132506321
Short name T683
Test name
Test status
Simulation time 486783665785 ps
CPU time 308.17 seconds
Started Apr 21 01:52:18 PM PDT 24
Finished Apr 21 01:57:26 PM PDT 24
Peak memory 202180 kb
Host smart-df1aaf41-4a4a-4bc7-9175-19db6834f34e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=132506321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.132506321
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1857391885
Short name T648
Test name
Test status
Simulation time 285142904073 ps
CPU time 80.38 seconds
Started Apr 21 01:52:19 PM PDT 24
Finished Apr 21 01:53:39 PM PDT 24
Peak memory 202304 kb
Host smart-1c9c4031-b0b3-490c-b8a5-1452e091dab1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857391885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1857391885
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1292951430
Short name T94
Test name
Test status
Simulation time 200780313764 ps
CPU time 444.78 seconds
Started Apr 21 01:52:21 PM PDT 24
Finished Apr 21 01:59:46 PM PDT 24
Peak memory 202124 kb
Host smart-19969d3a-0a11-417a-8aa6-6d8d1de10bd0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292951430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1292951430
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2986348912
Short name T43
Test name
Test status
Simulation time 93866122047 ps
CPU time 532.7 seconds
Started Apr 21 01:52:23 PM PDT 24
Finished Apr 21 02:01:16 PM PDT 24
Peak memory 202692 kb
Host smart-d0037823-74f2-4737-8656-2177e4eb9913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986348912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2986348912
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.4028389239
Short name T526
Test name
Test status
Simulation time 41004076492 ps
CPU time 20.73 seconds
Started Apr 21 01:52:24 PM PDT 24
Finished Apr 21 01:52:45 PM PDT 24
Peak memory 202044 kb
Host smart-056f3059-9d90-4077-84da-d49113bf1b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028389239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4028389239
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1552617892
Short name T493
Test name
Test status
Simulation time 5377978796 ps
CPU time 3.96 seconds
Started Apr 21 01:52:25 PM PDT 24
Finished Apr 21 01:52:29 PM PDT 24
Peak memory 202064 kb
Host smart-ea36a4c9-05a7-4c9e-8dcd-5dafdc835671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552617892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1552617892
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1793587792
Short name T57
Test name
Test status
Simulation time 8372324658 ps
CPU time 20.88 seconds
Started Apr 21 01:52:25 PM PDT 24
Finished Apr 21 01:52:46 PM PDT 24
Peak memory 218992 kb
Host smart-d0f44f46-9726-46ea-beac-8faa8dc91690
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793587792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1793587792
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2586639010
Short name T671
Test name
Test status
Simulation time 6043806301 ps
CPU time 10.04 seconds
Started Apr 21 01:52:17 PM PDT 24
Finished Apr 21 01:52:27 PM PDT 24
Peak memory 202084 kb
Host smart-39b1db2d-d642-46d3-850f-a3cac7b0bca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586639010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2586639010
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2550953686
Short name T740
Test name
Test status
Simulation time 304248725959 ps
CPU time 556.81 seconds
Started Apr 21 01:52:24 PM PDT 24
Finished Apr 21 02:01:41 PM PDT 24
Peak memory 212976 kb
Host smart-7ad8939b-3105-4ab8-a9e4-b139097c7b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550953686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2550953686
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3109252276
Short name T89
Test name
Test status
Simulation time 403693074 ps
CPU time 0.76 seconds
Started Apr 21 01:57:21 PM PDT 24
Finished Apr 21 01:57:22 PM PDT 24
Peak memory 201972 kb
Host smart-df21cfec-6250-40d0-91fd-5f36c0d67417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109252276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3109252276
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1652514095
Short name T543
Test name
Test status
Simulation time 167236663211 ps
CPU time 73.19 seconds
Started Apr 21 01:57:16 PM PDT 24
Finished Apr 21 01:58:30 PM PDT 24
Peak memory 202264 kb
Host smart-c2a4f2ce-9d0d-4970-9000-ad1598e73ee3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652514095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1652514095
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2938557335
Short name T276
Test name
Test status
Simulation time 168253221438 ps
CPU time 383.89 seconds
Started Apr 21 01:57:12 PM PDT 24
Finished Apr 21 02:03:36 PM PDT 24
Peak memory 202280 kb
Host smart-3d92f487-9bee-42c7-9f19-15156c741140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938557335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2938557335
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2391340459
Short name T503
Test name
Test status
Simulation time 163881577885 ps
CPU time 94.39 seconds
Started Apr 21 01:57:13 PM PDT 24
Finished Apr 21 01:58:47 PM PDT 24
Peak memory 202348 kb
Host smart-fdae3500-8bfb-4ac9-bd51-32b67e07e3fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391340459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2391340459
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.232277014
Short name T148
Test name
Test status
Simulation time 158364470156 ps
CPU time 98.22 seconds
Started Apr 21 01:57:10 PM PDT 24
Finished Apr 21 01:58:48 PM PDT 24
Peak memory 202224 kb
Host smart-ab2e86a0-c65b-4c87-9ada-05f8be2557ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232277014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.232277014
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.170648285
Short name T209
Test name
Test status
Simulation time 330329047222 ps
CPU time 172.1 seconds
Started Apr 21 01:57:13 PM PDT 24
Finished Apr 21 02:00:05 PM PDT 24
Peak memory 202236 kb
Host smart-794c248a-8d7e-4373-99f5-0922a2dcf234
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=170648285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.170648285
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3278106885
Short name T341
Test name
Test status
Simulation time 385669216579 ps
CPU time 162.17 seconds
Started Apr 21 01:57:16 PM PDT 24
Finished Apr 21 01:59:58 PM PDT 24
Peak memory 202296 kb
Host smart-7432908e-34d0-40ab-a10d-c609f629bde7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278106885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3278106885
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3330152504
Short name T541
Test name
Test status
Simulation time 405850307687 ps
CPU time 1007.7 seconds
Started Apr 21 01:57:18 PM PDT 24
Finished Apr 21 02:14:06 PM PDT 24
Peak memory 202216 kb
Host smart-db6e4fdc-404b-4a4f-89e9-b216ad0262ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330152504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3330152504
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1974111039
Short name T528
Test name
Test status
Simulation time 96085964563 ps
CPU time 336.67 seconds
Started Apr 21 01:57:20 PM PDT 24
Finished Apr 21 02:02:57 PM PDT 24
Peak memory 202576 kb
Host smart-6c7992a0-ac5e-4c89-a099-111400a0ab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974111039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1974111039
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1500403050
Short name T533
Test name
Test status
Simulation time 28586179116 ps
CPU time 60.77 seconds
Started Apr 21 01:57:19 PM PDT 24
Finished Apr 21 01:58:20 PM PDT 24
Peak memory 202040 kb
Host smart-16511a6d-44bb-42a5-ab7b-2147c617aee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500403050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1500403050
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2633395064
Short name T610
Test name
Test status
Simulation time 2891058770 ps
CPU time 6.72 seconds
Started Apr 21 01:57:15 PM PDT 24
Finished Apr 21 01:57:22 PM PDT 24
Peak memory 202060 kb
Host smart-dd770023-0782-44ea-8863-c27688002cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633395064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2633395064
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3231244556
Short name T216
Test name
Test status
Simulation time 5668093850 ps
CPU time 4.09 seconds
Started Apr 21 01:57:11 PM PDT 24
Finished Apr 21 01:57:15 PM PDT 24
Peak memory 202000 kb
Host smart-3134de66-e81a-4151-9255-34a4dd713f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231244556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3231244556
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.419000825
Short name T34
Test name
Test status
Simulation time 171726242070 ps
CPU time 106.32 seconds
Started Apr 21 01:57:18 PM PDT 24
Finished Apr 21 01:59:05 PM PDT 24
Peak memory 202308 kb
Host smart-8572be61-47c4-4192-a68b-112800e4e0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419000825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
419000825
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3867470755
Short name T583
Test name
Test status
Simulation time 89104350016 ps
CPU time 343.34 seconds
Started Apr 21 01:57:20 PM PDT 24
Finished Apr 21 02:03:04 PM PDT 24
Peak memory 218468 kb
Host smart-0d291e14-5171-4e0d-8c5d-c23d3ef9f5d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867470755 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3867470755
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3024816453
Short name T719
Test name
Test status
Simulation time 394560946 ps
CPU time 0.84 seconds
Started Apr 21 01:57:29 PM PDT 24
Finished Apr 21 01:57:30 PM PDT 24
Peak memory 201980 kb
Host smart-159f4f3c-58f8-4eb4-8eb5-f9df5a90a57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024816453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3024816453
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1610120101
Short name T176
Test name
Test status
Simulation time 351285119584 ps
CPU time 208.21 seconds
Started Apr 21 01:57:24 PM PDT 24
Finished Apr 21 02:00:53 PM PDT 24
Peak memory 202268 kb
Host smart-cf3213dc-90b7-41f5-96e9-4309d823432d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610120101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1610120101
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2953628984
Short name T764
Test name
Test status
Simulation time 163472180512 ps
CPU time 401.33 seconds
Started Apr 21 01:57:25 PM PDT 24
Finished Apr 21 02:04:06 PM PDT 24
Peak memory 202264 kb
Host smart-e47ab5d8-1313-470c-9fe5-477c5a2dd9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953628984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2953628984
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2637790616
Short name T698
Test name
Test status
Simulation time 166726377740 ps
CPU time 103.64 seconds
Started Apr 21 01:57:22 PM PDT 24
Finished Apr 21 01:59:06 PM PDT 24
Peak memory 202176 kb
Host smart-6b31241a-1ca8-4ca1-86b5-ef0db7ac2519
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637790616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2637790616
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1475168953
Short name T680
Test name
Test status
Simulation time 159824205051 ps
CPU time 386.18 seconds
Started Apr 21 01:57:21 PM PDT 24
Finished Apr 21 02:03:47 PM PDT 24
Peak memory 202248 kb
Host smart-45c2d9f8-8756-4944-a75c-0649273df41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475168953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1475168953
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3564772607
Short name T770
Test name
Test status
Simulation time 497425341647 ps
CPU time 1019.87 seconds
Started Apr 21 01:57:24 PM PDT 24
Finished Apr 21 02:14:24 PM PDT 24
Peak memory 202324 kb
Host smart-808e82c9-55b5-4ce0-afed-0d5a0eab7cf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564772607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3564772607
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4014825423
Short name T359
Test name
Test status
Simulation time 178744917917 ps
CPU time 410.65 seconds
Started Apr 21 01:57:23 PM PDT 24
Finished Apr 21 02:04:14 PM PDT 24
Peak memory 202336 kb
Host smart-b3b1bd42-cdd4-486f-b299-d119fc97524b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014825423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4014825423
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3383726634
Short name T728
Test name
Test status
Simulation time 196690653560 ps
CPU time 374.77 seconds
Started Apr 21 01:57:24 PM PDT 24
Finished Apr 21 02:03:39 PM PDT 24
Peak memory 202332 kb
Host smart-cdf9d980-3b1b-4277-b6c2-5530c66467d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383726634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3383726634
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2883094630
Short name T585
Test name
Test status
Simulation time 129594072671 ps
CPU time 532.65 seconds
Started Apr 21 01:57:30 PM PDT 24
Finished Apr 21 02:06:23 PM PDT 24
Peak memory 202576 kb
Host smart-f5497b52-4a7d-4291-984e-0d165c99fcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883094630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2883094630
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1681673823
Short name T749
Test name
Test status
Simulation time 35282379496 ps
CPU time 82.29 seconds
Started Apr 21 01:57:26 PM PDT 24
Finished Apr 21 01:58:49 PM PDT 24
Peak memory 202048 kb
Host smart-1e079ff9-9d6d-4d38-9134-d0313082b63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681673823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1681673823
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.481997471
Short name T592
Test name
Test status
Simulation time 2683585480 ps
CPU time 3.63 seconds
Started Apr 21 01:57:29 PM PDT 24
Finished Apr 21 01:57:33 PM PDT 24
Peak memory 202064 kb
Host smart-a8e71279-8bdd-4767-bf6a-b683e02947f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481997471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.481997471
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.4220103734
Short name T621
Test name
Test status
Simulation time 5701505275 ps
CPU time 14.78 seconds
Started Apr 21 01:57:24 PM PDT 24
Finished Apr 21 01:57:39 PM PDT 24
Peak memory 202084 kb
Host smart-182cac2d-f140-437b-80f7-0e796eccc6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220103734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.4220103734
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4025683430
Short name T251
Test name
Test status
Simulation time 183529754692 ps
CPU time 206.24 seconds
Started Apr 21 01:57:31 PM PDT 24
Finished Apr 21 02:00:57 PM PDT 24
Peak memory 202256 kb
Host smart-5a2e6f74-fbf9-440c-ad4c-62d89d40bd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025683430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4025683430
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.367422193
Short name T73
Test name
Test status
Simulation time 338893026 ps
CPU time 1.36 seconds
Started Apr 21 01:57:46 PM PDT 24
Finished Apr 21 01:57:47 PM PDT 24
Peak memory 202152 kb
Host smart-055ea3bb-b9c9-4e46-bc41-f42be4660347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367422193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.367422193
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.645426932
Short name T748
Test name
Test status
Simulation time 587505353922 ps
CPU time 934.29 seconds
Started Apr 21 01:57:41 PM PDT 24
Finished Apr 21 02:13:15 PM PDT 24
Peak memory 202240 kb
Host smart-099d5966-541d-4be2-b6c8-946b0f714fde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645426932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.645426932
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3516847779
Short name T650
Test name
Test status
Simulation time 172333015743 ps
CPU time 438.79 seconds
Started Apr 21 01:57:40 PM PDT 24
Finished Apr 21 02:04:59 PM PDT 24
Peak memory 202264 kb
Host smart-c240dcdd-9672-447f-99db-f3604aa05ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516847779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3516847779
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.288723224
Short name T292
Test name
Test status
Simulation time 159733545686 ps
CPU time 135.94 seconds
Started Apr 21 01:57:33 PM PDT 24
Finished Apr 21 01:59:49 PM PDT 24
Peak memory 202264 kb
Host smart-47d3cb43-7604-428e-9ff7-1e0becb8e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288723224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.288723224
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1721985242
Short name T786
Test name
Test status
Simulation time 163916987896 ps
CPU time 105.16 seconds
Started Apr 21 01:57:38 PM PDT 24
Finished Apr 21 01:59:23 PM PDT 24
Peak memory 202204 kb
Host smart-6a899ace-322f-401c-b434-58053c5af053
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721985242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1721985242
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.101567473
Short name T732
Test name
Test status
Simulation time 329475582090 ps
CPU time 376.37 seconds
Started Apr 21 01:57:30 PM PDT 24
Finished Apr 21 02:03:47 PM PDT 24
Peak memory 202256 kb
Host smart-4d6e0881-9d65-44d7-964b-7f8fd23c12f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101567473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.101567473
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2843157452
Short name T542
Test name
Test status
Simulation time 165950222227 ps
CPU time 410.12 seconds
Started Apr 21 01:57:32 PM PDT 24
Finished Apr 21 02:04:23 PM PDT 24
Peak memory 202236 kb
Host smart-a6237d6c-c9e4-43ff-a928-08d64ed4e3ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843157452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2843157452
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3066291901
Short name T306
Test name
Test status
Simulation time 168566706699 ps
CPU time 387.25 seconds
Started Apr 21 01:57:37 PM PDT 24
Finished Apr 21 02:04:05 PM PDT 24
Peak memory 202380 kb
Host smart-66e4ee01-6c0c-458c-a159-5eb7b4909d4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066291901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3066291901
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2880865404
Short name T756
Test name
Test status
Simulation time 105401297608 ps
CPU time 506.15 seconds
Started Apr 21 01:57:44 PM PDT 24
Finished Apr 21 02:06:11 PM PDT 24
Peak memory 202628 kb
Host smart-b36d08b7-1dd1-4658-8bec-b3b72168cbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880865404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2880865404
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.434034728
Short name T731
Test name
Test status
Simulation time 30752885021 ps
CPU time 9.08 seconds
Started Apr 21 01:57:44 PM PDT 24
Finished Apr 21 01:57:54 PM PDT 24
Peak memory 202072 kb
Host smart-39d4b62d-6175-4727-b42f-62ba4586a7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434034728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.434034728
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2127502861
Short name T730
Test name
Test status
Simulation time 5434158938 ps
CPU time 2.7 seconds
Started Apr 21 01:57:43 PM PDT 24
Finished Apr 21 01:57:46 PM PDT 24
Peak memory 202096 kb
Host smart-179cfa89-78bd-484f-b25f-97af27568781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127502861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2127502861
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1453499674
Short name T562
Test name
Test status
Simulation time 6056138310 ps
CPU time 14.98 seconds
Started Apr 21 01:57:30 PM PDT 24
Finished Apr 21 01:57:45 PM PDT 24
Peak memory 202052 kb
Host smart-8cb415f6-8a4e-45d6-a801-15130a5ab845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453499674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1453499674
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.4075759053
Short name T692
Test name
Test status
Simulation time 225780038677 ps
CPU time 711.62 seconds
Started Apr 21 01:57:43 PM PDT 24
Finished Apr 21 02:09:35 PM PDT 24
Peak memory 210748 kb
Host smart-c2f09530-94bd-4e84-9ce6-b42b3d0d9899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075759053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.4075759053
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.723193955
Short name T656
Test name
Test status
Simulation time 499866146 ps
CPU time 0.67 seconds
Started Apr 21 01:57:58 PM PDT 24
Finished Apr 21 01:57:59 PM PDT 24
Peak memory 201964 kb
Host smart-f2810f14-ee44-4e41-8694-2bac70db95fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723193955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.723193955
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2875837954
Short name T289
Test name
Test status
Simulation time 157301596267 ps
CPU time 27.16 seconds
Started Apr 21 01:57:50 PM PDT 24
Finished Apr 21 01:58:18 PM PDT 24
Peak memory 202260 kb
Host smart-02e9deb5-b591-40cc-8ad7-d07b0852d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875837954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2875837954
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1104273643
Short name T249
Test name
Test status
Simulation time 497148432044 ps
CPU time 426.94 seconds
Started Apr 21 01:57:50 PM PDT 24
Finished Apr 21 02:04:57 PM PDT 24
Peak memory 202212 kb
Host smart-a61242a5-975e-4f4d-b260-1532514bba13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104273643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1104273643
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4204135859
Short name T546
Test name
Test status
Simulation time 161313351654 ps
CPU time 93.62 seconds
Started Apr 21 01:57:47 PM PDT 24
Finished Apr 21 01:59:21 PM PDT 24
Peak memory 202224 kb
Host smart-52021fb2-6b76-470e-8d73-9f81a5d2a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204135859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4204135859
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1271803304
Short name T425
Test name
Test status
Simulation time 320110546580 ps
CPU time 746.13 seconds
Started Apr 21 01:57:47 PM PDT 24
Finished Apr 21 02:10:13 PM PDT 24
Peak memory 202240 kb
Host smart-91ac5467-c394-4089-9fa7-4bb2b03f1274
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271803304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1271803304
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3817104238
Short name T268
Test name
Test status
Simulation time 351627015491 ps
CPU time 437.13 seconds
Started Apr 21 01:57:52 PM PDT 24
Finished Apr 21 02:05:09 PM PDT 24
Peak memory 202336 kb
Host smart-0b0b3336-1f6e-4e1d-a2e2-2bf5d6127552
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817104238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3817104238
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2934313863
Short name T758
Test name
Test status
Simulation time 201095084645 ps
CPU time 217.84 seconds
Started Apr 21 01:57:51 PM PDT 24
Finished Apr 21 02:01:29 PM PDT 24
Peak memory 202248 kb
Host smart-69a92393-f126-40be-89a4-28b9b16dbdfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934313863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2934313863
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2516161894
Short name T227
Test name
Test status
Simulation time 123509587985 ps
CPU time 485.14 seconds
Started Apr 21 01:57:56 PM PDT 24
Finished Apr 21 02:06:01 PM PDT 24
Peak memory 202664 kb
Host smart-d347a962-256a-4877-826d-c7af8b16bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516161894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2516161894
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2339839349
Short name T7
Test name
Test status
Simulation time 39403541065 ps
CPU time 36.54 seconds
Started Apr 21 01:57:51 PM PDT 24
Finished Apr 21 01:58:28 PM PDT 24
Peak memory 202068 kb
Host smart-915be0bf-db79-45ba-b8ed-6cc5ec05f784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339839349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2339839349
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3205626682
Short name T133
Test name
Test status
Simulation time 4946468770 ps
CPU time 11.02 seconds
Started Apr 21 01:57:53 PM PDT 24
Finished Apr 21 01:58:04 PM PDT 24
Peak memory 202064 kb
Host smart-665b02e8-4a00-4979-a1f5-eef289bb6f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205626682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3205626682
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.100845969
Short name T537
Test name
Test status
Simulation time 5963291731 ps
CPU time 15.02 seconds
Started Apr 21 01:57:47 PM PDT 24
Finished Apr 21 01:58:02 PM PDT 24
Peak memory 202076 kb
Host smart-23cb71ee-b0fa-4236-baba-df04e2250d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100845969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.100845969
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.383818732
Short name T288
Test name
Test status
Simulation time 575002249684 ps
CPU time 569.67 seconds
Started Apr 21 01:57:57 PM PDT 24
Finished Apr 21 02:07:27 PM PDT 24
Peak memory 202588 kb
Host smart-da359417-e95a-481d-93e7-a9b6e8f9ac5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383818732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
383818732
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1117595690
Short name T568
Test name
Test status
Simulation time 125161334570 ps
CPU time 80.15 seconds
Started Apr 21 01:57:55 PM PDT 24
Finished Apr 21 01:59:15 PM PDT 24
Peak memory 202464 kb
Host smart-a3c531ca-5c41-4099-9b20-214ad6522934
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117595690 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1117595690
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3075802535
Short name T601
Test name
Test status
Simulation time 441802921 ps
CPU time 0.81 seconds
Started Apr 21 01:58:06 PM PDT 24
Finished Apr 21 01:58:07 PM PDT 24
Peak memory 201984 kb
Host smart-5ff2c8c7-b8cf-4dda-988c-6c3301d2e475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075802535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3075802535
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2345587762
Short name T326
Test name
Test status
Simulation time 167759164838 ps
CPU time 94.42 seconds
Started Apr 21 01:58:00 PM PDT 24
Finished Apr 21 01:59:35 PM PDT 24
Peak memory 202252 kb
Host smart-239848de-0116-4592-a035-baec3ec888ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345587762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2345587762
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3040061018
Short name T26
Test name
Test status
Simulation time 160095532128 ps
CPU time 95.52 seconds
Started Apr 21 01:58:01 PM PDT 24
Finished Apr 21 01:59:37 PM PDT 24
Peak memory 202272 kb
Host smart-dfab09d3-c06c-4e22-aedc-13c7579a729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040061018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3040061018
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2809356049
Short name T457
Test name
Test status
Simulation time 489809474912 ps
CPU time 577.2 seconds
Started Apr 21 01:58:02 PM PDT 24
Finished Apr 21 02:07:40 PM PDT 24
Peak memory 202228 kb
Host smart-22f0ef50-c225-4f9c-a471-4fcd55872636
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809356049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2809356049
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2953556205
Short name T675
Test name
Test status
Simulation time 165827257821 ps
CPU time 382.03 seconds
Started Apr 21 01:58:00 PM PDT 24
Finished Apr 21 02:04:22 PM PDT 24
Peak memory 202244 kb
Host smart-3d584db5-fdc4-4b94-8ecb-8264d13707e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953556205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2953556205
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3047824357
Short name T501
Test name
Test status
Simulation time 498209470337 ps
CPU time 278.05 seconds
Started Apr 21 01:58:00 PM PDT 24
Finished Apr 21 02:02:38 PM PDT 24
Peak memory 202168 kb
Host smart-8a7fda7d-c82e-41ae-a207-41e5682b76e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047824357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3047824357
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2520240720
Short name T445
Test name
Test status
Simulation time 615897861819 ps
CPU time 121.33 seconds
Started Apr 21 01:58:00 PM PDT 24
Finished Apr 21 02:00:02 PM PDT 24
Peak memory 202244 kb
Host smart-d2d5008b-00b9-411d-82f0-845d32845a0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520240720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2520240720
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1026306314
Short name T560
Test name
Test status
Simulation time 82321510260 ps
CPU time 346.5 seconds
Started Apr 21 01:58:05 PM PDT 24
Finished Apr 21 02:03:52 PM PDT 24
Peak memory 202544 kb
Host smart-4a195c6b-7f9c-4b04-acd5-53865173ced2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026306314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1026306314
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1484709780
Short name T103
Test name
Test status
Simulation time 42007783437 ps
CPU time 23.98 seconds
Started Apr 21 01:58:04 PM PDT 24
Finished Apr 21 01:58:28 PM PDT 24
Peak memory 202096 kb
Host smart-c58e5d75-b378-424e-8181-07bf6111b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484709780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1484709780
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3696643549
Short name T561
Test name
Test status
Simulation time 4983986055 ps
CPU time 12.32 seconds
Started Apr 21 01:58:03 PM PDT 24
Finished Apr 21 01:58:16 PM PDT 24
Peak memory 202076 kb
Host smart-9f78d6ad-87a6-48ea-a29c-4b2597153fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696643549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3696643549
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2495468354
Short name T669
Test name
Test status
Simulation time 5930038601 ps
CPU time 7.63 seconds
Started Apr 21 01:57:57 PM PDT 24
Finished Apr 21 01:58:05 PM PDT 24
Peak memory 202084 kb
Host smart-946d400b-1418-4e72-a490-3a887a599539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495468354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2495468354
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.437620740
Short name T342
Test name
Test status
Simulation time 314091231476 ps
CPU time 196.79 seconds
Started Apr 21 01:58:06 PM PDT 24
Finished Apr 21 02:01:23 PM PDT 24
Peak memory 210968 kb
Host smart-c9719835-dcb1-4778-aec2-d0da13ba2c42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437620740 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.437620740
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2091621512
Short name T518
Test name
Test status
Simulation time 376449149 ps
CPU time 0.81 seconds
Started Apr 21 01:58:40 PM PDT 24
Finished Apr 21 01:58:41 PM PDT 24
Peak memory 201992 kb
Host smart-61be0d2e-be66-4e40-bca1-ffb1169772c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091621512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2091621512
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2282626485
Short name T190
Test name
Test status
Simulation time 556622650568 ps
CPU time 164.6 seconds
Started Apr 21 01:58:17 PM PDT 24
Finished Apr 21 02:01:02 PM PDT 24
Peak memory 202320 kb
Host smart-179e53ff-1f80-40a9-b3d5-9010d7f2e86e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282626485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2282626485
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.26514872
Short name T635
Test name
Test status
Simulation time 169794981340 ps
CPU time 305.6 seconds
Started Apr 21 01:58:15 PM PDT 24
Finished Apr 21 02:03:21 PM PDT 24
Peak memory 202248 kb
Host smart-4c8dce91-653e-412e-9b92-ccea835ecb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26514872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.26514872
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.568248322
Short name T459
Test name
Test status
Simulation time 326917696977 ps
CPU time 276.39 seconds
Started Apr 21 01:58:14 PM PDT 24
Finished Apr 21 02:02:51 PM PDT 24
Peak memory 202224 kb
Host smart-43f71d4a-2893-45ca-9b2d-18a1bcd2e70f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=568248322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.568248322
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4188803565
Short name T145
Test name
Test status
Simulation time 167935961324 ps
CPU time 100.27 seconds
Started Apr 21 01:58:09 PM PDT 24
Finished Apr 21 01:59:50 PM PDT 24
Peak memory 202308 kb
Host smart-894f65b1-951f-40e4-96e2-05ed6e11f529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188803565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4188803565
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.286658444
Short name T502
Test name
Test status
Simulation time 329324814556 ps
CPU time 174.47 seconds
Started Apr 21 01:58:15 PM PDT 24
Finished Apr 21 02:01:09 PM PDT 24
Peak memory 202320 kb
Host smart-e72bf5f8-30cc-4a3b-97d6-c4a7711abb2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=286658444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.286658444
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.760866229
Short name T321
Test name
Test status
Simulation time 378509296537 ps
CPU time 899 seconds
Started Apr 21 01:58:17 PM PDT 24
Finished Apr 21 02:13:16 PM PDT 24
Peak memory 202268 kb
Host smart-6daac54d-cc66-417d-88f6-c4dda5875f6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760866229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.760866229
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.789230097
Short name T195
Test name
Test status
Simulation time 587063283013 ps
CPU time 666.14 seconds
Started Apr 21 01:58:17 PM PDT 24
Finished Apr 21 02:09:23 PM PDT 24
Peak memory 202276 kb
Host smart-c8f8fdde-a741-42b0-8667-a76bf3b3018d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789230097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.789230097
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2382924399
Short name T234
Test name
Test status
Simulation time 76612014004 ps
CPU time 254.54 seconds
Started Apr 21 01:58:29 PM PDT 24
Finished Apr 21 02:02:43 PM PDT 24
Peak memory 202552 kb
Host smart-d8c520a0-507d-4b98-867a-9db9d08d4318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382924399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2382924399
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2641147250
Short name T691
Test name
Test status
Simulation time 34018594885 ps
CPU time 8.67 seconds
Started Apr 21 01:58:26 PM PDT 24
Finished Apr 21 01:58:35 PM PDT 24
Peak memory 202076 kb
Host smart-ceb95db2-7387-4161-b602-9a3e95600aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641147250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2641147250
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3917378400
Short name T71
Test name
Test status
Simulation time 5757870142 ps
CPU time 14.48 seconds
Started Apr 21 01:58:22 PM PDT 24
Finished Apr 21 01:58:37 PM PDT 24
Peak memory 202036 kb
Host smart-04402c53-dccf-4663-9576-5e9e0c52e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917378400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3917378400
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2893008897
Short name T745
Test name
Test status
Simulation time 5862156075 ps
CPU time 13.66 seconds
Started Apr 21 01:58:09 PM PDT 24
Finished Apr 21 01:58:23 PM PDT 24
Peak memory 202064 kb
Host smart-7d70a822-3ce9-4108-9638-3b60082b9d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893008897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2893008897
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.837497453
Short name T535
Test name
Test status
Simulation time 545362786468 ps
CPU time 1244.22 seconds
Started Apr 21 01:58:39 PM PDT 24
Finished Apr 21 02:19:23 PM PDT 24
Peak memory 213588 kb
Host smart-6de8b2f3-b63c-4ec8-abdc-d389a97aa561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837497453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
837497453
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2040463265
Short name T14
Test name
Test status
Simulation time 63232456477 ps
CPU time 124.88 seconds
Started Apr 21 01:58:29 PM PDT 24
Finished Apr 21 02:00:34 PM PDT 24
Peak memory 210940 kb
Host smart-63241949-2c14-40b2-b6e5-72f11304b539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040463265 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2040463265
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.282229451
Short name T383
Test name
Test status
Simulation time 482541446 ps
CPU time 1.36 seconds
Started Apr 21 01:58:47 PM PDT 24
Finished Apr 21 01:58:49 PM PDT 24
Peak memory 201972 kb
Host smart-ee1c3e76-ecc7-4c09-afa6-627a5c585cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282229451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.282229451
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.121240441
Short name T565
Test name
Test status
Simulation time 167230916223 ps
CPU time 212.19 seconds
Started Apr 21 01:58:42 PM PDT 24
Finished Apr 21 02:02:15 PM PDT 24
Peak memory 202380 kb
Host smart-2ca3d5ec-3dec-451f-a265-3af4ed26c7c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121240441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.121240441
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1270263150
Short name T312
Test name
Test status
Simulation time 189395833246 ps
CPU time 71.29 seconds
Started Apr 21 01:58:42 PM PDT 24
Finished Apr 21 01:59:53 PM PDT 24
Peak memory 202284 kb
Host smart-e478cd89-7d4f-4219-a821-5fc767b7ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270263150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1270263150
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2035027236
Short name T194
Test name
Test status
Simulation time 161888171347 ps
CPU time 90.72 seconds
Started Apr 21 01:58:39 PM PDT 24
Finished Apr 21 02:00:10 PM PDT 24
Peak memory 202240 kb
Host smart-5be18caa-eab5-4616-9028-f52766ee312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035027236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2035027236
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3861489062
Short name T574
Test name
Test status
Simulation time 165358261115 ps
CPU time 207.07 seconds
Started Apr 21 01:58:39 PM PDT 24
Finished Apr 21 02:02:07 PM PDT 24
Peak memory 202280 kb
Host smart-191564ea-5a7b-40eb-84cb-2f18ce226823
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861489062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3861489062
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3971810928
Short name T291
Test name
Test status
Simulation time 158923273595 ps
CPU time 180.85 seconds
Started Apr 21 01:58:41 PM PDT 24
Finished Apr 21 02:01:42 PM PDT 24
Peak memory 202296 kb
Host smart-13b9e4e0-0ef3-4cc4-b7d0-19dd5bdda101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971810928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3971810928
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.970551308
Short name T620
Test name
Test status
Simulation time 326557416161 ps
CPU time 406.47 seconds
Started Apr 21 01:58:40 PM PDT 24
Finished Apr 21 02:05:27 PM PDT 24
Peak memory 202276 kb
Host smart-37ddee75-3093-418f-b277-cfd8294884e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=970551308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.970551308
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.955515616
Short name T724
Test name
Test status
Simulation time 531401154442 ps
CPU time 322.41 seconds
Started Apr 21 01:58:38 PM PDT 24
Finished Apr 21 02:04:01 PM PDT 24
Peak memory 202272 kb
Host smart-d92b061d-8460-4bb4-bd8f-00a0b2ed913d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955515616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.955515616
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.982640190
Short name T10
Test name
Test status
Simulation time 209004114547 ps
CPU time 245.23 seconds
Started Apr 21 01:58:41 PM PDT 24
Finished Apr 21 02:02:46 PM PDT 24
Peak memory 202320 kb
Host smart-cff0a28b-1335-450f-b464-001d40e2cbc8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982640190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.982640190
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1877477979
Short name T483
Test name
Test status
Simulation time 99989840554 ps
CPU time 428.85 seconds
Started Apr 21 01:58:44 PM PDT 24
Finished Apr 21 02:05:53 PM PDT 24
Peak memory 202580 kb
Host smart-35348806-27f1-4bda-885f-dfb79a344deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877477979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1877477979
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2884248046
Short name T798
Test name
Test status
Simulation time 26929802789 ps
CPU time 16.44 seconds
Started Apr 21 01:58:41 PM PDT 24
Finished Apr 21 01:58:58 PM PDT 24
Peak memory 202072 kb
Host smart-27809d7b-fa34-49dd-805a-cedfb177bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884248046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2884248046
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1363006198
Short name T760
Test name
Test status
Simulation time 3159399865 ps
CPU time 2.29 seconds
Started Apr 21 01:58:40 PM PDT 24
Finished Apr 21 01:58:43 PM PDT 24
Peak memory 202044 kb
Host smart-e6f8c6c4-9355-4413-bb81-91991f55acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363006198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1363006198
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3385641045
Short name T495
Test name
Test status
Simulation time 5873413596 ps
CPU time 14.94 seconds
Started Apr 21 01:58:40 PM PDT 24
Finished Apr 21 01:58:55 PM PDT 24
Peak memory 202108 kb
Host smart-43ce6a23-7881-4f58-b945-89f8a1d8ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385641045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3385641045
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1378362462
Short name T237
Test name
Test status
Simulation time 400841794362 ps
CPU time 891.95 seconds
Started Apr 21 01:58:48 PM PDT 24
Finished Apr 21 02:13:40 PM PDT 24
Peak memory 219004 kb
Host smart-7303c77a-fb4f-422d-9e4c-25dce9088841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378362462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1378362462
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2829938901
Short name T304
Test name
Test status
Simulation time 89094931543 ps
CPU time 188.59 seconds
Started Apr 21 01:58:45 PM PDT 24
Finished Apr 21 02:01:53 PM PDT 24
Peak memory 219016 kb
Host smart-1fec5ce6-8c79-4034-8736-7cc843a584fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829938901 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2829938901
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3397847158
Short name T173
Test name
Test status
Simulation time 384487806 ps
CPU time 1.46 seconds
Started Apr 21 01:58:56 PM PDT 24
Finished Apr 21 01:58:58 PM PDT 24
Peak memory 201956 kb
Host smart-505975c5-650c-46f9-8a93-0171f74862bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397847158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3397847158
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2196319197
Short name T30
Test name
Test status
Simulation time 506070975992 ps
CPU time 530.99 seconds
Started Apr 21 01:58:53 PM PDT 24
Finished Apr 21 02:07:45 PM PDT 24
Peak memory 202224 kb
Host smart-e9542a9b-a724-4c94-83ba-3ec5226f5e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196319197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2196319197
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.79194639
Short name T353
Test name
Test status
Simulation time 334357257020 ps
CPU time 223.01 seconds
Started Apr 21 01:58:51 PM PDT 24
Finished Apr 21 02:02:35 PM PDT 24
Peak memory 202280 kb
Host smart-8a5e99cd-0a8f-4aeb-909a-be1fcef98fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79194639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.79194639
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1767730938
Short name T208
Test name
Test status
Simulation time 168137850623 ps
CPU time 234.01 seconds
Started Apr 21 01:58:50 PM PDT 24
Finished Apr 21 02:02:44 PM PDT 24
Peak memory 202240 kb
Host smart-25de2c73-fb2c-49e5-bda0-476e4ab4ccff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767730938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1767730938
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1815828545
Short name T576
Test name
Test status
Simulation time 163091789893 ps
CPU time 120.61 seconds
Started Apr 21 01:58:50 PM PDT 24
Finished Apr 21 02:00:51 PM PDT 24
Peak memory 202280 kb
Host smart-a6fff126-7747-4d13-a1c7-18fb27559fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815828545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1815828545
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3253674404
Short name T769
Test name
Test status
Simulation time 326097576673 ps
CPU time 784.99 seconds
Started Apr 21 01:58:48 PM PDT 24
Finished Apr 21 02:11:53 PM PDT 24
Peak memory 202220 kb
Host smart-5b72e82e-8c8d-43d9-abff-115ff0155638
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253674404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3253674404
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1595804664
Short name T264
Test name
Test status
Simulation time 588231118595 ps
CPU time 1430.85 seconds
Started Apr 21 01:58:50 PM PDT 24
Finished Apr 21 02:22:41 PM PDT 24
Peak memory 202264 kb
Host smart-3412bf12-8b29-4e75-a386-8c1dab95dbe0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595804664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1595804664
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3617207408
Short name T507
Test name
Test status
Simulation time 593640860116 ps
CPU time 1389.19 seconds
Started Apr 21 01:58:50 PM PDT 24
Finished Apr 21 02:22:00 PM PDT 24
Peak memory 202228 kb
Host smart-6654ac45-635f-4976-a2de-8cb5da351af8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617207408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3617207408
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2474991302
Short name T11
Test name
Test status
Simulation time 102940895263 ps
CPU time 350.07 seconds
Started Apr 21 01:58:58 PM PDT 24
Finished Apr 21 02:04:48 PM PDT 24
Peak memory 202564 kb
Host smart-d916f637-37be-4c6f-8618-154b8d8c4aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474991302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2474991302
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1726609423
Short name T662
Test name
Test status
Simulation time 32089054943 ps
CPU time 74.54 seconds
Started Apr 21 01:58:54 PM PDT 24
Finished Apr 21 02:00:09 PM PDT 24
Peak memory 202100 kb
Host smart-1da93f0a-5b3d-4910-910d-154082b10937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726609423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1726609423
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2805183245
Short name T792
Test name
Test status
Simulation time 3877665326 ps
CPU time 2.6 seconds
Started Apr 21 01:58:53 PM PDT 24
Finished Apr 21 01:58:56 PM PDT 24
Peak memory 202124 kb
Host smart-ffb08e4b-8527-4d15-b3c7-410f9ae15f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805183245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2805183245
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1415106316
Short name T540
Test name
Test status
Simulation time 5979425428 ps
CPU time 7.59 seconds
Started Apr 21 01:58:46 PM PDT 24
Finished Apr 21 01:58:54 PM PDT 24
Peak memory 202076 kb
Host smart-4a323eff-3d90-4689-bcdc-54a6a5715d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415106316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1415106316
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3390811488
Short name T356
Test name
Test status
Simulation time 329197163783 ps
CPU time 394.99 seconds
Started Apr 21 01:58:57 PM PDT 24
Finished Apr 21 02:05:32 PM PDT 24
Peak memory 202248 kb
Host smart-fc1b4a34-4506-4f17-ad23-125c73554dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390811488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3390811488
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1523822031
Short name T20
Test name
Test status
Simulation time 4733648049 ps
CPU time 12.91 seconds
Started Apr 21 01:58:58 PM PDT 24
Finished Apr 21 01:59:11 PM PDT 24
Peak memory 202464 kb
Host smart-557605e4-12ec-4cb8-b736-24d68eb9b727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523822031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1523822031
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3915197379
Short name T737
Test name
Test status
Simulation time 461590547 ps
CPU time 0.84 seconds
Started Apr 21 01:59:13 PM PDT 24
Finished Apr 21 01:59:15 PM PDT 24
Peak memory 201972 kb
Host smart-8d485749-bc2e-4e80-9aa9-f9e00006effe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915197379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3915197379
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1790367930
Short name T466
Test name
Test status
Simulation time 171894320544 ps
CPU time 196.42 seconds
Started Apr 21 01:59:09 PM PDT 24
Finished Apr 21 02:02:25 PM PDT 24
Peak memory 202264 kb
Host smart-addba6cb-8556-4f34-8a12-0e8162418942
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790367930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1790367930
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.774086961
Short name T328
Test name
Test status
Simulation time 161786042573 ps
CPU time 99.05 seconds
Started Apr 21 01:59:04 PM PDT 24
Finished Apr 21 02:00:43 PM PDT 24
Peak memory 202204 kb
Host smart-a3f58b58-455d-4ae0-9391-46e7f164beb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774086961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.774086961
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2907562305
Short name T404
Test name
Test status
Simulation time 495766571978 ps
CPU time 325.94 seconds
Started Apr 21 01:59:04 PM PDT 24
Finished Apr 21 02:04:30 PM PDT 24
Peak memory 202172 kb
Host smart-c16e2493-2591-4d16-b7f3-1872af2c280b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907562305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2907562305
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4152434963
Short name T301
Test name
Test status
Simulation time 161259220374 ps
CPU time 128.36 seconds
Started Apr 21 01:59:03 PM PDT 24
Finished Apr 21 02:01:11 PM PDT 24
Peak memory 202316 kb
Host smart-a556c1b5-6fe5-49e0-bdda-89579bcc1674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152434963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4152434963
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.245686555
Short name T751
Test name
Test status
Simulation time 327320500200 ps
CPU time 200.96 seconds
Started Apr 21 01:59:02 PM PDT 24
Finished Apr 21 02:02:23 PM PDT 24
Peak memory 202232 kb
Host smart-51fca260-c4cd-4804-a462-8a611b53761b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=245686555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.245686555
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.691272135
Short name T88
Test name
Test status
Simulation time 610406854704 ps
CPU time 600.27 seconds
Started Apr 21 01:59:06 PM PDT 24
Finished Apr 21 02:09:06 PM PDT 24
Peak memory 202236 kb
Host smart-eadd25aa-fe7b-4bc9-8ffe-93648f4faf3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691272135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.691272135
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1522495612
Short name T233
Test name
Test status
Simulation time 139547109884 ps
CPU time 565.54 seconds
Started Apr 21 01:59:11 PM PDT 24
Finished Apr 21 02:08:37 PM PDT 24
Peak memory 202568 kb
Host smart-24fc794b-b22d-4b8f-9776-83a74763e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522495612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1522495612
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1293050823
Short name T607
Test name
Test status
Simulation time 33840550322 ps
CPU time 22.86 seconds
Started Apr 21 01:59:11 PM PDT 24
Finished Apr 21 01:59:34 PM PDT 24
Peak memory 202040 kb
Host smart-ca75a260-eb1d-4cd1-af43-7be6d15ac98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293050823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1293050823
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2318564077
Short name T9
Test name
Test status
Simulation time 5000909869 ps
CPU time 2.01 seconds
Started Apr 21 01:59:11 PM PDT 24
Finished Apr 21 01:59:13 PM PDT 24
Peak memory 202020 kb
Host smart-13cdc01d-3fe3-4a80-8f3c-042ab41968f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318564077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2318564077
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4215542748
Short name T431
Test name
Test status
Simulation time 6032116186 ps
CPU time 3.28 seconds
Started Apr 21 01:59:00 PM PDT 24
Finished Apr 21 01:59:03 PM PDT 24
Peak memory 202056 kb
Host smart-41e30815-d7e9-4317-ae78-ac37faafb3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215542748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4215542748
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.943399870
Short name T300
Test name
Test status
Simulation time 660578185181 ps
CPU time 1605.09 seconds
Started Apr 21 01:59:12 PM PDT 24
Finished Apr 21 02:25:57 PM PDT 24
Peak memory 202272 kb
Host smart-c051300d-d75a-4f08-a128-2b734a092ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943399870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
943399870
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3795196226
Short name T38
Test name
Test status
Simulation time 148575861332 ps
CPU time 178.58 seconds
Started Apr 21 01:59:14 PM PDT 24
Finished Apr 21 02:02:13 PM PDT 24
Peak memory 210780 kb
Host smart-33f80447-c883-4eb8-a524-3bc7ff28a5fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795196226 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3795196226
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1163788985
Short name T716
Test name
Test status
Simulation time 465792899 ps
CPU time 1.6 seconds
Started Apr 21 01:59:23 PM PDT 24
Finished Apr 21 01:59:25 PM PDT 24
Peak memory 201944 kb
Host smart-ea451fba-bb02-4866-9cfe-817937b5b479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163788985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1163788985
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3588662828
Short name T245
Test name
Test status
Simulation time 169858483567 ps
CPU time 209.14 seconds
Started Apr 21 01:59:20 PM PDT 24
Finished Apr 21 02:02:49 PM PDT 24
Peak memory 202292 kb
Host smart-3d0931e4-8b04-492e-81d4-c62627fdbd54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588662828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3588662828
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2486743534
Short name T797
Test name
Test status
Simulation time 326291062424 ps
CPU time 701.7 seconds
Started Apr 21 01:59:19 PM PDT 24
Finished Apr 21 02:11:01 PM PDT 24
Peak memory 202460 kb
Host smart-b011a859-09d0-479c-bfb2-985cd27ed31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486743534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2486743534
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.377377528
Short name T552
Test name
Test status
Simulation time 164134661027 ps
CPU time 256.84 seconds
Started Apr 21 01:59:17 PM PDT 24
Finished Apr 21 02:03:34 PM PDT 24
Peak memory 202220 kb
Host smart-b3a6a528-4261-471d-9300-6a2676c44c15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=377377528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.377377528
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.644777551
Short name T538
Test name
Test status
Simulation time 325979378662 ps
CPU time 193.09 seconds
Started Apr 21 01:59:17 PM PDT 24
Finished Apr 21 02:02:30 PM PDT 24
Peak memory 202252 kb
Host smart-167ba060-d5e4-4bcd-9a2a-a384ac79f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644777551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.644777551
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.222972929
Short name T86
Test name
Test status
Simulation time 502643943524 ps
CPU time 135.32 seconds
Started Apr 21 01:59:17 PM PDT 24
Finished Apr 21 02:01:33 PM PDT 24
Peak memory 202236 kb
Host smart-45d14892-7382-44bf-92c9-dabe2143b189
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=222972929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.222972929
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3278166848
Short name T638
Test name
Test status
Simulation time 374148375303 ps
CPU time 424.47 seconds
Started Apr 21 01:59:17 PM PDT 24
Finished Apr 21 02:06:21 PM PDT 24
Peak memory 202272 kb
Host smart-c66343f0-2e1e-4eff-aebb-3e85f9f00891
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278166848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3278166848
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1363469928
Short name T384
Test name
Test status
Simulation time 590691673834 ps
CPU time 1330.7 seconds
Started Apr 21 01:59:18 PM PDT 24
Finished Apr 21 02:21:29 PM PDT 24
Peak memory 202244 kb
Host smart-49b0c0e9-b343-422b-8b39-86a645fb2b13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363469928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1363469928
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2754883013
Short name T694
Test name
Test status
Simulation time 67195600298 ps
CPU time 373.15 seconds
Started Apr 21 01:59:25 PM PDT 24
Finished Apr 21 02:05:39 PM PDT 24
Peak memory 202544 kb
Host smart-e51f5dbe-7246-4c48-bcf9-84ca32aadf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754883013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2754883013
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3150692705
Short name T468
Test name
Test status
Simulation time 34258739764 ps
CPU time 86.38 seconds
Started Apr 21 01:59:25 PM PDT 24
Finished Apr 21 02:00:51 PM PDT 24
Peak memory 202048 kb
Host smart-5ba69f0b-1596-4601-8604-b40eef083bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150692705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3150692705
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2898840926
Short name T455
Test name
Test status
Simulation time 3197167224 ps
CPU time 7.07 seconds
Started Apr 21 01:59:23 PM PDT 24
Finished Apr 21 01:59:30 PM PDT 24
Peak memory 202052 kb
Host smart-72da9f76-b785-4f91-b400-b4859a38efad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898840926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2898840926
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1844332801
Short name T442
Test name
Test status
Simulation time 6058464613 ps
CPU time 15.61 seconds
Started Apr 21 01:59:17 PM PDT 24
Finished Apr 21 01:59:33 PM PDT 24
Peak memory 202056 kb
Host smart-0920a46d-bf6d-477d-a20e-e02bdb6df6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844332801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1844332801
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3296337457
Short name T551
Test name
Test status
Simulation time 251553213924 ps
CPU time 826.79 seconds
Started Apr 21 01:59:22 PM PDT 24
Finished Apr 21 02:13:09 PM PDT 24
Peak memory 210788 kb
Host smart-19b4fc91-6bc7-45cc-9c8d-312f6668a23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296337457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3296337457
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2429511130
Short name T655
Test name
Test status
Simulation time 621581718731 ps
CPU time 491.4 seconds
Started Apr 21 01:59:23 PM PDT 24
Finished Apr 21 02:07:35 PM PDT 24
Peak memory 218416 kb
Host smart-d76ed48b-5280-41c4-8841-d8c49a4929fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429511130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2429511130
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.940789829
Short name T417
Test name
Test status
Simulation time 292534134 ps
CPU time 1.23 seconds
Started Apr 21 01:52:37 PM PDT 24
Finished Apr 21 01:52:38 PM PDT 24
Peak memory 201980 kb
Host smart-59c60a81-3518-4e9c-a270-386a43b6eb81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940789829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.940789829
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1094438173
Short name T293
Test name
Test status
Simulation time 338118913527 ps
CPU time 661.17 seconds
Started Apr 21 01:52:27 PM PDT 24
Finished Apr 21 02:03:28 PM PDT 24
Peak memory 202348 kb
Host smart-3cd6212b-24af-4a8b-92b6-0f7956851073
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094438173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1094438173
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1044655243
Short name T743
Test name
Test status
Simulation time 485193315879 ps
CPU time 156.75 seconds
Started Apr 21 01:52:26 PM PDT 24
Finished Apr 21 01:55:03 PM PDT 24
Peak memory 202356 kb
Host smart-c1d49167-a7e1-4d80-b9cc-b8147600e2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044655243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1044655243
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.403015061
Short name T624
Test name
Test status
Simulation time 164298032455 ps
CPU time 395.22 seconds
Started Apr 21 01:52:28 PM PDT 24
Finished Apr 21 01:59:03 PM PDT 24
Peak memory 202156 kb
Host smart-d304003e-4ba2-4a22-b0c4-85cd923cbfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403015061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.403015061
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4158827226
Short name T532
Test name
Test status
Simulation time 158439050297 ps
CPU time 34.78 seconds
Started Apr 21 01:52:25 PM PDT 24
Finished Apr 21 01:53:00 PM PDT 24
Peak memory 202224 kb
Host smart-94629ca4-95b3-4b07-9202-ed9220d11aeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158827226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4158827226
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1921318132
Short name T12
Test name
Test status
Simulation time 167763605746 ps
CPU time 361.12 seconds
Started Apr 21 01:52:27 PM PDT 24
Finished Apr 21 01:58:28 PM PDT 24
Peak memory 202236 kb
Host smart-6d1dce0e-a213-45c9-8130-7f17baccc17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921318132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1921318132
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.848841100
Short name T727
Test name
Test status
Simulation time 162605549092 ps
CPU time 159.78 seconds
Started Apr 21 01:52:28 PM PDT 24
Finished Apr 21 01:55:09 PM PDT 24
Peak memory 202316 kb
Host smart-f1cd66d2-57a6-4017-86b5-23af64e1dda9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848841100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.848841100
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.83606426
Short name T281
Test name
Test status
Simulation time 593074891582 ps
CPU time 389.35 seconds
Started Apr 21 01:52:27 PM PDT 24
Finished Apr 21 01:58:57 PM PDT 24
Peak memory 202336 kb
Host smart-58f7deb2-a9f5-44ad-aa13-351c53cdd752
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83606426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wa
keup.83606426
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.769340725
Short name T515
Test name
Test status
Simulation time 586564307754 ps
CPU time 713.9 seconds
Started Apr 21 01:52:27 PM PDT 24
Finished Apr 21 02:04:21 PM PDT 24
Peak memory 202344 kb
Host smart-75496684-62b4-45c1-b135-6fe3a53ec77f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769340725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.769340725
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.31270356
Short name T374
Test name
Test status
Simulation time 130243242682 ps
CPU time 433.24 seconds
Started Apr 21 01:52:30 PM PDT 24
Finished Apr 21 01:59:43 PM PDT 24
Peak memory 202524 kb
Host smart-8a5149d2-b181-49e6-ba79-6ad7873c2ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31270356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.31270356
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2932454322
Short name T440
Test name
Test status
Simulation time 37206448613 ps
CPU time 22.32 seconds
Started Apr 21 01:52:28 PM PDT 24
Finished Apr 21 01:52:51 PM PDT 24
Peak memory 202060 kb
Host smart-0295f0a5-ae22-4da5-8960-fdd38d5d977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932454322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2932454322
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.595319624
Short name T753
Test name
Test status
Simulation time 4949895878 ps
CPU time 3.02 seconds
Started Apr 21 01:52:30 PM PDT 24
Finished Apr 21 01:52:33 PM PDT 24
Peak memory 202076 kb
Host smart-d38c8442-93f1-422c-9912-c219c16e740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595319624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.595319624
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.4129993158
Short name T69
Test name
Test status
Simulation time 4081111353 ps
CPU time 10.46 seconds
Started Apr 21 01:52:33 PM PDT 24
Finished Apr 21 01:52:43 PM PDT 24
Peak memory 217740 kb
Host smart-9026d565-200e-4e42-9497-3cb8647673e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129993158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.4129993158
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2244882687
Short name T581
Test name
Test status
Simulation time 5946644177 ps
CPU time 8 seconds
Started Apr 21 01:52:28 PM PDT 24
Finished Apr 21 01:52:37 PM PDT 24
Peak memory 202032 kb
Host smart-a6d7dd96-358b-4638-8897-d7b305b27f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244882687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2244882687
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4170071708
Short name T266
Test name
Test status
Simulation time 121184691429 ps
CPU time 128.15 seconds
Started Apr 21 01:52:31 PM PDT 24
Finished Apr 21 01:54:39 PM PDT 24
Peak memory 210964 kb
Host smart-08ee164c-fcf1-4d6a-b3aa-28a3c718df58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170071708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.4170071708
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3924976907
Short name T632
Test name
Test status
Simulation time 402056255 ps
CPU time 0.92 seconds
Started Apr 21 01:59:33 PM PDT 24
Finished Apr 21 01:59:34 PM PDT 24
Peak memory 201976 kb
Host smart-a1ba570f-322d-45fa-82dd-ce9607aa0735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924976907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3924976907
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3570024864
Short name T178
Test name
Test status
Simulation time 333329908239 ps
CPU time 202.3 seconds
Started Apr 21 01:59:26 PM PDT 24
Finished Apr 21 02:02:49 PM PDT 24
Peak memory 202220 kb
Host smart-7cd1787d-2689-435f-a113-7712e6c0d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570024864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3570024864
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.973999656
Short name T645
Test name
Test status
Simulation time 330087181719 ps
CPU time 656.17 seconds
Started Apr 21 01:59:26 PM PDT 24
Finished Apr 21 02:10:23 PM PDT 24
Peak memory 202216 kb
Host smart-21ee7a62-5b42-4323-b30b-a8fa7f6fb63e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=973999656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.973999656
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.513844451
Short name T70
Test name
Test status
Simulation time 169225191542 ps
CPU time 92.7 seconds
Started Apr 21 01:59:25 PM PDT 24
Finished Apr 21 02:00:59 PM PDT 24
Peak memory 202212 kb
Host smart-22db4082-5d0b-4e9a-92a5-45aed72f33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513844451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.513844451
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.65643078
Short name T451
Test name
Test status
Simulation time 497734854608 ps
CPU time 1154.14 seconds
Started Apr 21 01:59:25 PM PDT 24
Finished Apr 21 02:18:40 PM PDT 24
Peak memory 202308 kb
Host smart-8ac4c5b2-d2af-43a2-9079-91fd269c5e7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=65643078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed
.65643078
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3267150881
Short name T609
Test name
Test status
Simulation time 533063837146 ps
CPU time 630.94 seconds
Started Apr 21 01:59:24 PM PDT 24
Finished Apr 21 02:09:56 PM PDT 24
Peak memory 202300 kb
Host smart-4b314714-712e-4b3a-ac55-83d55565224c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267150881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3267150881
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.107746314
Short name T735
Test name
Test status
Simulation time 195887448614 ps
CPU time 122.92 seconds
Started Apr 21 01:59:27 PM PDT 24
Finished Apr 21 02:01:30 PM PDT 24
Peak memory 202208 kb
Host smart-19b88ef8-9754-4589-8175-004bcc44cfd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107746314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.107746314
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3781518503
Short name T744
Test name
Test status
Simulation time 75780443135 ps
CPU time 263.61 seconds
Started Apr 21 01:59:32 PM PDT 24
Finished Apr 21 02:03:56 PM PDT 24
Peak memory 202680 kb
Host smart-151c83fa-76db-4a37-8db1-c91c3cd30b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781518503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3781518503
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1178074679
Short name T613
Test name
Test status
Simulation time 25617804264 ps
CPU time 24.08 seconds
Started Apr 21 01:59:31 PM PDT 24
Finished Apr 21 01:59:56 PM PDT 24
Peak memory 202092 kb
Host smart-89cc9717-83c2-468e-a1cb-328c9317eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178074679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1178074679
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3116494525
Short name T197
Test name
Test status
Simulation time 3949337826 ps
CPU time 3.16 seconds
Started Apr 21 01:59:29 PM PDT 24
Finished Apr 21 01:59:32 PM PDT 24
Peak memory 202068 kb
Host smart-f3ce04d2-5c65-403e-8abb-46c20e6bdb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116494525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3116494525
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4012684953
Short name T575
Test name
Test status
Simulation time 6070843604 ps
CPU time 3.2 seconds
Started Apr 21 01:59:26 PM PDT 24
Finished Apr 21 01:59:29 PM PDT 24
Peak memory 202080 kb
Host smart-b3053a79-2053-47b5-9881-c7f7a1c35451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012684953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4012684953
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.77797658
Short name T799
Test name
Test status
Simulation time 255332806586 ps
CPU time 453.2 seconds
Started Apr 21 01:59:35 PM PDT 24
Finished Apr 21 02:07:09 PM PDT 24
Peak memory 202580 kb
Host smart-3410901d-de53-4754-80e3-ea65b64f558e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77797658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.77797658
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1935102735
Short name T105
Test name
Test status
Simulation time 202236471567 ps
CPU time 179.58 seconds
Started Apr 21 01:59:31 PM PDT 24
Finished Apr 21 02:02:31 PM PDT 24
Peak memory 218816 kb
Host smart-3f846864-8e9c-4310-aac2-50d0f3fa7c7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935102735 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1935102735
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2630485162
Short name T476
Test name
Test status
Simulation time 413059167 ps
CPU time 0.83 seconds
Started Apr 21 01:59:44 PM PDT 24
Finished Apr 21 01:59:45 PM PDT 24
Peak memory 201944 kb
Host smart-f2d5b35d-7535-4ce7-9fd0-90618441b45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630485162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2630485162
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2645762512
Short name T82
Test name
Test status
Simulation time 530402107254 ps
CPU time 1233.55 seconds
Started Apr 21 01:59:42 PM PDT 24
Finished Apr 21 02:20:16 PM PDT 24
Peak memory 202312 kb
Host smart-f398bf21-c6a0-49cc-b7fd-622d15fbc4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645762512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2645762512
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.802794168
Short name T146
Test name
Test status
Simulation time 494956167513 ps
CPU time 1154.15 seconds
Started Apr 21 01:59:38 PM PDT 24
Finished Apr 21 02:18:52 PM PDT 24
Peak memory 202184 kb
Host smart-d55a5179-4d17-4d79-8e18-13bf1cd15c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802794168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.802794168
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.286510585
Short name T572
Test name
Test status
Simulation time 171285673849 ps
CPU time 40.63 seconds
Started Apr 21 01:59:39 PM PDT 24
Finished Apr 21 02:00:20 PM PDT 24
Peak memory 202236 kb
Host smart-d98ab6db-0fa9-4239-ace8-131365ad3751
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=286510585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.286510585
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.630288336
Short name T239
Test name
Test status
Simulation time 166687901612 ps
CPU time 362.84 seconds
Started Apr 21 01:59:40 PM PDT 24
Finished Apr 21 02:05:43 PM PDT 24
Peak memory 202256 kb
Host smart-c6196687-bc82-4ec9-a929-f2435074537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630288336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.630288336
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2787764491
Short name T509
Test name
Test status
Simulation time 488021720391 ps
CPU time 283.89 seconds
Started Apr 21 01:59:39 PM PDT 24
Finished Apr 21 02:04:23 PM PDT 24
Peak memory 202224 kb
Host smart-7b44ac5e-c5f0-4ed1-a729-4eefec4791c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787764491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2787764491
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3083477136
Short name T310
Test name
Test status
Simulation time 183880116258 ps
CPU time 196.87 seconds
Started Apr 21 01:59:42 PM PDT 24
Finished Apr 21 02:02:59 PM PDT 24
Peak memory 202356 kb
Host smart-8c5d047f-012f-4606-9017-51929e9dee4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083477136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3083477136
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.72477968
Short name T470
Test name
Test status
Simulation time 198700756394 ps
CPU time 135.01 seconds
Started Apr 21 01:59:43 PM PDT 24
Finished Apr 21 02:01:59 PM PDT 24
Peak memory 202320 kb
Host smart-662b95a3-4eb3-4526-b983-b2a6902ba4c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72477968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.a
dc_ctrl_filters_wakeup_fixed.72477968
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.796728367
Short name T228
Test name
Test status
Simulation time 101571334269 ps
CPU time 313.22 seconds
Started Apr 21 01:59:45 PM PDT 24
Finished Apr 21 02:04:58 PM PDT 24
Peak memory 202656 kb
Host smart-69bed370-7737-498f-8b8a-944ab8da6ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796728367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.796728367
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2371452638
Short name T39
Test name
Test status
Simulation time 38980452032 ps
CPU time 100.17 seconds
Started Apr 21 01:59:46 PM PDT 24
Finished Apr 21 02:01:26 PM PDT 24
Peak memory 202040 kb
Host smart-bf3f6c09-7649-425b-bfc0-33382e80f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371452638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2371452638
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3145757070
Short name T715
Test name
Test status
Simulation time 3736670136 ps
CPU time 3.02 seconds
Started Apr 21 01:59:45 PM PDT 24
Finished Apr 21 01:59:48 PM PDT 24
Peak memory 202020 kb
Host smart-b3467e06-8625-404e-9090-0119c5257f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145757070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3145757070
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.201014684
Short name T606
Test name
Test status
Simulation time 5849744537 ps
CPU time 7.87 seconds
Started Apr 21 01:59:35 PM PDT 24
Finished Apr 21 01:59:43 PM PDT 24
Peak memory 202104 kb
Host smart-36c09c87-b0ee-4b7c-b848-232ff3d25031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201014684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.201014684
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.4110657428
Short name T708
Test name
Test status
Simulation time 183635120876 ps
CPU time 175.31 seconds
Started Apr 21 01:59:44 PM PDT 24
Finished Apr 21 02:02:39 PM PDT 24
Peak memory 213084 kb
Host smart-07a86f7e-6818-4f31-b453-2a645a6d4b19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110657428 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.4110657428
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1034975981
Short name T666
Test name
Test status
Simulation time 515687920 ps
CPU time 0.77 seconds
Started Apr 21 01:59:57 PM PDT 24
Finished Apr 21 01:59:58 PM PDT 24
Peak memory 201992 kb
Host smart-168218d6-a85c-4626-9eb9-6cd1effb7d29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034975981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1034975981
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4252579220
Short name T527
Test name
Test status
Simulation time 491216143488 ps
CPU time 1124.4 seconds
Started Apr 21 01:59:49 PM PDT 24
Finished Apr 21 02:18:33 PM PDT 24
Peak memory 202240 kb
Host smart-578c27d2-5048-482f-8cca-00a78f8ede70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252579220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4252579220
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.39715939
Short name T421
Test name
Test status
Simulation time 167993005464 ps
CPU time 108.78 seconds
Started Apr 21 01:59:50 PM PDT 24
Finished Apr 21 02:01:39 PM PDT 24
Peak memory 202236 kb
Host smart-d3fb80d8-d0f1-4067-9b92-131c9b7ad862
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt
_fixed.39715939
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2818782914
Short name T755
Test name
Test status
Simulation time 321708777372 ps
CPU time 200.48 seconds
Started Apr 21 01:59:47 PM PDT 24
Finished Apr 21 02:03:08 PM PDT 24
Peak memory 202224 kb
Host smart-be7ca598-fe42-4702-91c4-2225b7e0f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818782914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2818782914
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1755029459
Short name T424
Test name
Test status
Simulation time 499978797400 ps
CPU time 1192.73 seconds
Started Apr 21 01:59:50 PM PDT 24
Finished Apr 21 02:19:43 PM PDT 24
Peak memory 202320 kb
Host smart-3f664e10-f722-44e9-b5ad-5a870e6a3e3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755029459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1755029459
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1638490944
Short name T668
Test name
Test status
Simulation time 193357890558 ps
CPU time 102.43 seconds
Started Apr 21 01:59:52 PM PDT 24
Finished Apr 21 02:01:35 PM PDT 24
Peak memory 202240 kb
Host smart-59e89445-12fc-4fe9-8e47-a256b59fca96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638490944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1638490944
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3502726014
Short name T752
Test name
Test status
Simulation time 118350162924 ps
CPU time 615.68 seconds
Started Apr 21 01:59:56 PM PDT 24
Finished Apr 21 02:10:12 PM PDT 24
Peak memory 202632 kb
Host smart-f4f2ab12-e8b7-427d-91ca-99026059abb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502726014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3502726014
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3123013905
Short name T220
Test name
Test status
Simulation time 30505435685 ps
CPU time 8.21 seconds
Started Apr 21 01:59:56 PM PDT 24
Finished Apr 21 02:00:05 PM PDT 24
Peak memory 202064 kb
Host smart-ebb83921-a4ee-457f-b2ab-2740ef71135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123013905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3123013905
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3548530731
Short name T441
Test name
Test status
Simulation time 3716994877 ps
CPU time 8.98 seconds
Started Apr 21 01:59:55 PM PDT 24
Finished Apr 21 02:00:04 PM PDT 24
Peak memory 202012 kb
Host smart-19f311c9-b7e9-4ee9-ada4-00bf054bd139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548530731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3548530731
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.4245067888
Short name T76
Test name
Test status
Simulation time 5713560303 ps
CPU time 4.46 seconds
Started Apr 21 01:59:48 PM PDT 24
Finished Apr 21 01:59:53 PM PDT 24
Peak memory 202080 kb
Host smart-8628f5c9-5c97-4cc4-8e0f-16868b2f32e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245067888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4245067888
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.573670005
Short name T334
Test name
Test status
Simulation time 513361382399 ps
CPU time 582.7 seconds
Started Apr 21 01:59:56 PM PDT 24
Finished Apr 21 02:09:39 PM PDT 24
Peak memory 202252 kb
Host smart-6a932895-22ef-4891-81d9-e763a11e7619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573670005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
573670005
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3749060587
Short name T107
Test name
Test status
Simulation time 460996973076 ps
CPU time 237.78 seconds
Started Apr 21 01:59:57 PM PDT 24
Finished Apr 21 02:03:55 PM PDT 24
Peak memory 210852 kb
Host smart-51ac1ca7-8de8-4599-b34a-db9ee03293d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749060587 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3749060587
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1671234461
Short name T29
Test name
Test status
Simulation time 338504718 ps
CPU time 1.02 seconds
Started Apr 21 02:00:05 PM PDT 24
Finished Apr 21 02:00:06 PM PDT 24
Peak memory 201980 kb
Host smart-e1a897f6-297e-4a8d-a465-0f9caa622ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671234461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1671234461
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2238060988
Short name T688
Test name
Test status
Simulation time 508134759738 ps
CPU time 1199.01 seconds
Started Apr 21 02:00:01 PM PDT 24
Finished Apr 21 02:20:00 PM PDT 24
Peak memory 202268 kb
Host smart-377eeb58-6a84-45a7-8daf-ce48e39485a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238060988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2238060988
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1097684154
Short name T318
Test name
Test status
Simulation time 498570129138 ps
CPU time 1236.64 seconds
Started Apr 21 01:59:59 PM PDT 24
Finished Apr 21 02:20:36 PM PDT 24
Peak memory 202252 kb
Host smart-edefe97a-5901-45fa-b628-9d2171c2299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097684154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1097684154
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2594168148
Short name T484
Test name
Test status
Simulation time 164647964385 ps
CPU time 377.07 seconds
Started Apr 21 01:59:59 PM PDT 24
Finished Apr 21 02:06:16 PM PDT 24
Peak memory 202204 kb
Host smart-b16a7025-53a7-44e1-819b-c5817c4b33f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594168148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2594168148
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1835601366
Short name T153
Test name
Test status
Simulation time 500880372114 ps
CPU time 999.59 seconds
Started Apr 21 01:59:57 PM PDT 24
Finished Apr 21 02:16:37 PM PDT 24
Peak memory 202200 kb
Host smart-ec7d671e-480f-4d80-b0b1-0472a052d699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835601366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1835601366
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4000002190
Short name T563
Test name
Test status
Simulation time 327151876872 ps
CPU time 743.45 seconds
Started Apr 21 01:59:56 PM PDT 24
Finished Apr 21 02:12:20 PM PDT 24
Peak memory 202316 kb
Host smart-cfb2d7f3-4aa2-4135-8757-e604daae0745
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000002190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4000002190
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4240990108
Short name T347
Test name
Test status
Simulation time 370954260312 ps
CPU time 245.61 seconds
Started Apr 21 01:59:59 PM PDT 24
Finished Apr 21 02:04:04 PM PDT 24
Peak memory 202232 kb
Host smart-b6e48fb6-1d30-40fc-aab0-d924c2d29f3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240990108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4240990108
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.417441910
Short name T380
Test name
Test status
Simulation time 401145852288 ps
CPU time 253.77 seconds
Started Apr 21 01:59:59 PM PDT 24
Finished Apr 21 02:04:13 PM PDT 24
Peak memory 202212 kb
Host smart-8ff603a1-8555-4769-ba8a-1dfb8594d6da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417441910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.417441910
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2559663861
Short name T375
Test name
Test status
Simulation time 120062083939 ps
CPU time 436.67 seconds
Started Apr 21 02:00:02 PM PDT 24
Finished Apr 21 02:07:19 PM PDT 24
Peak memory 202656 kb
Host smart-523f0744-18e2-40e2-9d14-e4b7695495fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559663861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2559663861
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1176011880
Short name T586
Test name
Test status
Simulation time 28617457478 ps
CPU time 16.78 seconds
Started Apr 21 02:00:02 PM PDT 24
Finished Apr 21 02:00:19 PM PDT 24
Peak memory 202048 kb
Host smart-c9add194-3b39-4b68-a74b-ed5133a3106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176011880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1176011880
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3915235599
Short name T547
Test name
Test status
Simulation time 2710284253 ps
CPU time 1.75 seconds
Started Apr 21 02:00:01 PM PDT 24
Finished Apr 21 02:00:04 PM PDT 24
Peak memory 202060 kb
Host smart-66dd197b-87f2-4f31-988d-f4e18772e621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915235599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3915235599
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3808119914
Short name T204
Test name
Test status
Simulation time 5937347316 ps
CPU time 4.29 seconds
Started Apr 21 01:59:55 PM PDT 24
Finished Apr 21 01:59:59 PM PDT 24
Peak memory 202080 kb
Host smart-539916a6-a0ae-4b80-9072-638e8a40af39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808119914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3808119914
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1872628676
Short name T236
Test name
Test status
Simulation time 617131087284 ps
CPU time 451.13 seconds
Started Apr 21 02:00:06 PM PDT 24
Finished Apr 21 02:07:37 PM PDT 24
Peak memory 202672 kb
Host smart-b17d29c9-13b2-4384-bb2f-6363eddb4364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872628676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1872628676
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.778345287
Short name T733
Test name
Test status
Simulation time 113381299589 ps
CPU time 122.93 seconds
Started Apr 21 02:00:04 PM PDT 24
Finished Apr 21 02:02:07 PM PDT 24
Peak memory 202776 kb
Host smart-6535ed9b-3b42-4120-97b3-7ba3895c881b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778345287 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.778345287
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2210103199
Short name T651
Test name
Test status
Simulation time 541676829 ps
CPU time 0.78 seconds
Started Apr 21 02:00:20 PM PDT 24
Finished Apr 21 02:00:21 PM PDT 24
Peak memory 201972 kb
Host smart-bde4c3ee-f7d2-4668-9ef8-f4e201f210ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210103199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2210103199
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.784668340
Short name T139
Test name
Test status
Simulation time 178503888612 ps
CPU time 98.75 seconds
Started Apr 21 02:00:17 PM PDT 24
Finished Apr 21 02:01:56 PM PDT 24
Peak memory 202376 kb
Host smart-50901aa7-e9b5-4366-b5a8-e39c923ab9b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784668340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.784668340
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3296632353
Short name T259
Test name
Test status
Simulation time 329085039941 ps
CPU time 357.02 seconds
Started Apr 21 02:00:12 PM PDT 24
Finished Apr 21 02:06:09 PM PDT 24
Peak memory 202268 kb
Host smart-0e8d6eb4-1f99-4758-8406-ec5b1e7a0614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296632353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3296632353
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2980800048
Short name T697
Test name
Test status
Simulation time 165654546263 ps
CPU time 44.53 seconds
Started Apr 21 02:00:14 PM PDT 24
Finished Apr 21 02:00:59 PM PDT 24
Peak memory 202208 kb
Host smart-bdd5ba0c-dbe8-41e6-b201-4009cbd3ee0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980800048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2980800048
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1279239199
Short name T499
Test name
Test status
Simulation time 489339263162 ps
CPU time 714.69 seconds
Started Apr 21 02:00:10 PM PDT 24
Finished Apr 21 02:12:05 PM PDT 24
Peak memory 202336 kb
Host smart-7945ff82-76e6-4021-8b09-1a2622ac96b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279239199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1279239199
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3303713670
Short name T517
Test name
Test status
Simulation time 166672763664 ps
CPU time 358.6 seconds
Started Apr 21 02:00:09 PM PDT 24
Finished Apr 21 02:06:08 PM PDT 24
Peak memory 202284 kb
Host smart-3cf907ed-0960-447a-9c40-d573ca605d69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303713670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3303713670
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.303027277
Short name T189
Test name
Test status
Simulation time 375314281210 ps
CPU time 138.28 seconds
Started Apr 21 02:00:17 PM PDT 24
Finished Apr 21 02:02:35 PM PDT 24
Peak memory 202264 kb
Host smart-01526089-34f5-4839-89de-05b3e2b05e8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303027277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.303027277
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2259834282
Short name T430
Test name
Test status
Simulation time 406187291033 ps
CPU time 889.99 seconds
Started Apr 21 02:00:17 PM PDT 24
Finished Apr 21 02:15:07 PM PDT 24
Peak memory 202240 kb
Host smart-1ec38713-07a5-40fe-822e-b81e9e1cef33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259834282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2259834282
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1443165958
Short name T593
Test name
Test status
Simulation time 109229742171 ps
CPU time 372.21 seconds
Started Apr 21 02:00:19 PM PDT 24
Finished Apr 21 02:06:32 PM PDT 24
Peak memory 202480 kb
Host smart-c34ed1ef-e224-4bea-b199-12d970fac706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443165958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1443165958
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1750844506
Short name T415
Test name
Test status
Simulation time 34451827543 ps
CPU time 20.97 seconds
Started Apr 21 02:00:18 PM PDT 24
Finished Apr 21 02:00:39 PM PDT 24
Peak memory 202040 kb
Host smart-6dfe426e-2cd2-42ef-9300-97cd508449fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750844506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1750844506
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2261983746
Short name T595
Test name
Test status
Simulation time 3715969842 ps
CPU time 9.45 seconds
Started Apr 21 02:00:16 PM PDT 24
Finished Apr 21 02:00:26 PM PDT 24
Peak memory 202052 kb
Host smart-f9b3890b-2053-4a71-85cf-6c38f9da0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261983746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2261983746
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3441620269
Short name T77
Test name
Test status
Simulation time 5802721637 ps
CPU time 15.31 seconds
Started Apr 21 02:00:04 PM PDT 24
Finished Apr 21 02:00:20 PM PDT 24
Peak memory 202024 kb
Host smart-fb0c6211-cd13-4da1-b7e7-cacab14d94a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441620269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3441620269
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.898211065
Short name T224
Test name
Test status
Simulation time 392045749626 ps
CPU time 341.36 seconds
Started Apr 21 02:00:20 PM PDT 24
Finished Apr 21 02:06:01 PM PDT 24
Peak memory 210864 kb
Host smart-aae36cf0-1537-4b71-8aaf-0180b24fca84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898211065 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.898211065
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2848270947
Short name T796
Test name
Test status
Simulation time 388526225 ps
CPU time 1.51 seconds
Started Apr 21 02:00:32 PM PDT 24
Finished Apr 21 02:00:33 PM PDT 24
Peak memory 201988 kb
Host smart-6813272f-9a37-42c7-83cb-c6e94a1e5f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848270947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2848270947
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3052275637
Short name T287
Test name
Test status
Simulation time 166700213767 ps
CPU time 397.02 seconds
Started Apr 21 02:00:26 PM PDT 24
Finished Apr 21 02:07:03 PM PDT 24
Peak memory 202236 kb
Host smart-38d22f0e-54b1-478c-bc7c-ce7d1a8f4545
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052275637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3052275637
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.78056094
Short name T348
Test name
Test status
Simulation time 359427178415 ps
CPU time 168.48 seconds
Started Apr 21 02:00:29 PM PDT 24
Finished Apr 21 02:03:18 PM PDT 24
Peak memory 202284 kb
Host smart-dc2855ed-fb83-4bd3-9cd4-75bf5e53bf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78056094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.78056094
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.477444037
Short name T257
Test name
Test status
Simulation time 318691393613 ps
CPU time 753.49 seconds
Started Apr 21 02:00:23 PM PDT 24
Finished Apr 21 02:12:56 PM PDT 24
Peak memory 202304 kb
Host smart-8958d037-1d32-4400-8e31-386f8e61480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477444037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.477444037
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2084738783
Short name T461
Test name
Test status
Simulation time 325212480534 ps
CPU time 211.08 seconds
Started Apr 21 02:00:27 PM PDT 24
Finished Apr 21 02:03:59 PM PDT 24
Peak memory 202280 kb
Host smart-cee39e97-8826-469b-bb1d-980e51f60cf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084738783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2084738783
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4088545447
Short name T660
Test name
Test status
Simulation time 158066430511 ps
CPU time 378.81 seconds
Started Apr 21 02:00:24 PM PDT 24
Finished Apr 21 02:06:43 PM PDT 24
Peak memory 202324 kb
Host smart-f1eedb9d-b8d8-4589-806c-22cfb7ff667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088545447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4088545447
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4208752932
Short name T482
Test name
Test status
Simulation time 164871499539 ps
CPU time 389.81 seconds
Started Apr 21 02:00:22 PM PDT 24
Finished Apr 21 02:06:52 PM PDT 24
Peak memory 202192 kb
Host smart-03760f0a-7322-4446-acf8-90de6dd1cb3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208752932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4208752932
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.977855714
Short name T794
Test name
Test status
Simulation time 175268966971 ps
CPU time 77 seconds
Started Apr 21 02:00:26 PM PDT 24
Finished Apr 21 02:01:43 PM PDT 24
Peak memory 202336 kb
Host smart-4d731bc7-5da7-49fa-a9e2-454d8ab6c80f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977855714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.977855714
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3184507140
Short name T480
Test name
Test status
Simulation time 587062949610 ps
CPU time 1295.22 seconds
Started Apr 21 02:00:25 PM PDT 24
Finished Apr 21 02:22:00 PM PDT 24
Peak memory 202332 kb
Host smart-c58910b5-797e-479d-8af7-866bf5c48297
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184507140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3184507140
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.583919469
Short name T376
Test name
Test status
Simulation time 101552814442 ps
CPU time 366.1 seconds
Started Apr 21 02:00:29 PM PDT 24
Finished Apr 21 02:06:35 PM PDT 24
Peak memory 202552 kb
Host smart-6447af11-6585-4a5a-bd17-12f003b6b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583919469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.583919469
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3782315293
Short name T530
Test name
Test status
Simulation time 28516975556 ps
CPU time 64.89 seconds
Started Apr 21 02:00:28 PM PDT 24
Finished Apr 21 02:01:33 PM PDT 24
Peak memory 202068 kb
Host smart-fb320f02-302b-480e-95a8-3b2bc9c5fd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782315293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3782315293
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3095949098
Short name T516
Test name
Test status
Simulation time 2911223408 ps
CPU time 2.42 seconds
Started Apr 21 02:00:29 PM PDT 24
Finished Apr 21 02:00:31 PM PDT 24
Peak memory 202048 kb
Host smart-edd092ae-785d-4c81-b93a-037765af7ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095949098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3095949098
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1663475638
Short name T555
Test name
Test status
Simulation time 5960171607 ps
CPU time 14.36 seconds
Started Apr 21 02:00:21 PM PDT 24
Finished Apr 21 02:00:36 PM PDT 24
Peak memory 202048 kb
Host smart-e6b70e6c-7b8a-4dd2-8553-7aa20a123861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663475638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1663475638
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2679191397
Short name T275
Test name
Test status
Simulation time 732443630388 ps
CPU time 631 seconds
Started Apr 21 02:00:34 PM PDT 24
Finished Apr 21 02:11:05 PM PDT 24
Peak memory 210804 kb
Host smart-05c1293b-7f45-4afa-9e4a-72b7d307654b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679191397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2679191397
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.825251215
Short name T789
Test name
Test status
Simulation time 79430808490 ps
CPU time 191.66 seconds
Started Apr 21 02:00:29 PM PDT 24
Finished Apr 21 02:03:41 PM PDT 24
Peak memory 202468 kb
Host smart-0b758f2b-b9f0-43d9-8053-b8796f086d11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825251215 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.825251215
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.331449995
Short name T395
Test name
Test status
Simulation time 314958385 ps
CPU time 1.26 seconds
Started Apr 21 02:00:50 PM PDT 24
Finished Apr 21 02:00:52 PM PDT 24
Peak memory 201996 kb
Host smart-311efb61-c378-41d5-97c7-3ee40ab82948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331449995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.331449995
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3212245670
Short name T725
Test name
Test status
Simulation time 174232538145 ps
CPU time 194.64 seconds
Started Apr 21 02:00:39 PM PDT 24
Finished Apr 21 02:03:54 PM PDT 24
Peak memory 202272 kb
Host smart-d3fa0999-3a82-42b0-95ab-776b979617d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212245670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3212245670
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2038537290
Short name T514
Test name
Test status
Simulation time 171381552294 ps
CPU time 407.86 seconds
Started Apr 21 02:00:35 PM PDT 24
Finished Apr 21 02:07:23 PM PDT 24
Peak memory 202344 kb
Host smart-e4ae9cf3-e690-4089-bc8c-47275efef396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038537290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2038537290
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4065674063
Short name T534
Test name
Test status
Simulation time 488505755079 ps
CPU time 604.1 seconds
Started Apr 21 02:00:38 PM PDT 24
Finished Apr 21 02:10:43 PM PDT 24
Peak memory 202308 kb
Host smart-47e6267d-7313-4ad0-9189-59f3cb49f14e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065674063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4065674063
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3687959069
Short name T641
Test name
Test status
Simulation time 166123705790 ps
CPU time 353.31 seconds
Started Apr 21 02:00:38 PM PDT 24
Finished Apr 21 02:06:32 PM PDT 24
Peak memory 202252 kb
Host smart-82fccf6f-6aaf-4b78-bf43-9b1ee09732e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687959069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3687959069
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1547066071
Short name T611
Test name
Test status
Simulation time 158992153986 ps
CPU time 347.82 seconds
Started Apr 21 02:00:36 PM PDT 24
Finished Apr 21 02:06:24 PM PDT 24
Peak memory 202216 kb
Host smart-146855ca-0197-44ca-977f-f5b2b5b2f737
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547066071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1547066071
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3669513091
Short name T713
Test name
Test status
Simulation time 201475673608 ps
CPU time 195.17 seconds
Started Apr 21 02:00:34 PM PDT 24
Finished Apr 21 02:03:50 PM PDT 24
Peak memory 202324 kb
Host smart-83542bd9-e887-4196-a67e-1c98e32b79a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669513091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3669513091
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.303359320
Short name T435
Test name
Test status
Simulation time 603539977410 ps
CPU time 372.19 seconds
Started Apr 21 02:00:36 PM PDT 24
Finished Apr 21 02:06:48 PM PDT 24
Peak memory 202240 kb
Host smart-b756fafa-b81c-447f-b885-e181132eb5bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303359320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.303359320
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3724099388
Short name T232
Test name
Test status
Simulation time 89854660077 ps
CPU time 339.18 seconds
Started Apr 21 02:00:51 PM PDT 24
Finished Apr 21 02:06:30 PM PDT 24
Peak memory 202576 kb
Host smart-93b99f88-f93c-43e8-941f-47d448b17af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724099388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3724099388
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.796343574
Short name T791
Test name
Test status
Simulation time 31620834005 ps
CPU time 19.17 seconds
Started Apr 21 02:00:44 PM PDT 24
Finished Apr 21 02:01:03 PM PDT 24
Peak memory 202056 kb
Host smart-ce29978f-0181-405f-afc1-ab9e9aa3aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796343574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.796343574
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.474899233
Short name T464
Test name
Test status
Simulation time 5301316819 ps
CPU time 3.82 seconds
Started Apr 21 02:00:43 PM PDT 24
Finished Apr 21 02:00:47 PM PDT 24
Peak memory 202064 kb
Host smart-bd416bff-3647-4d70-a614-8afa8c1f6e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474899233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.474899233
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.109498435
Short name T406
Test name
Test status
Simulation time 6006122664 ps
CPU time 14.51 seconds
Started Apr 21 02:00:33 PM PDT 24
Finished Apr 21 02:00:48 PM PDT 24
Peak memory 202076 kb
Host smart-25cd7de5-3d3e-45e8-893d-2c2b152a3d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109498435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.109498435
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2454690809
Short name T774
Test name
Test status
Simulation time 122954406717 ps
CPU time 137.11 seconds
Started Apr 21 02:00:50 PM PDT 24
Finished Apr 21 02:03:08 PM PDT 24
Peak memory 211048 kb
Host smart-9ead97c1-b216-4c38-81cd-0094a6979723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454690809 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2454690809
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1639929543
Short name T773
Test name
Test status
Simulation time 411604048 ps
CPU time 0.85 seconds
Started Apr 21 02:01:03 PM PDT 24
Finished Apr 21 02:01:04 PM PDT 24
Peak memory 201944 kb
Host smart-44d4bbe8-e3b2-400c-8562-b63349460c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639929543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1639929543
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3055119410
Short name T297
Test name
Test status
Simulation time 162723614323 ps
CPU time 99.26 seconds
Started Apr 21 02:00:55 PM PDT 24
Finished Apr 21 02:02:34 PM PDT 24
Peak memory 202296 kb
Host smart-96bc468f-3bc8-4ee2-b0dd-3361a4d6ee0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055119410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3055119410
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3830013124
Short name T614
Test name
Test status
Simulation time 165673251003 ps
CPU time 392.39 seconds
Started Apr 21 02:00:55 PM PDT 24
Finished Apr 21 02:07:28 PM PDT 24
Peak memory 202292 kb
Host smart-8a304518-7357-40b7-bde1-0f354dfd16e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830013124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3830013124
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1239981017
Short name T394
Test name
Test status
Simulation time 160269745799 ps
CPU time 102.97 seconds
Started Apr 21 02:00:52 PM PDT 24
Finished Apr 21 02:02:36 PM PDT 24
Peak memory 202292 kb
Host smart-094c973e-3e62-416d-b879-0fb85bf2421e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239981017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1239981017
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2994090940
Short name T272
Test name
Test status
Simulation time 163400182972 ps
CPU time 382.99 seconds
Started Apr 21 02:00:51 PM PDT 24
Finished Apr 21 02:07:15 PM PDT 24
Peak memory 202312 kb
Host smart-ffdb16e6-757f-4485-bc82-84d6be641006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994090940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2994090940
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1966152093
Short name T378
Test name
Test status
Simulation time 161318797229 ps
CPU time 92.16 seconds
Started Apr 21 02:00:53 PM PDT 24
Finished Apr 21 02:02:25 PM PDT 24
Peak memory 202232 kb
Host smart-748fc2fd-c75a-49ef-bf63-c11df648fe12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966152093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1966152093
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3972083302
Short name T317
Test name
Test status
Simulation time 527833987545 ps
CPU time 285.07 seconds
Started Apr 21 02:00:57 PM PDT 24
Finished Apr 21 02:05:42 PM PDT 24
Peak memory 202288 kb
Host smart-e87b3c59-d36f-4937-9c48-e5c3c30f2786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972083302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3972083302
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.86879344
Short name T412
Test name
Test status
Simulation time 199056628918 ps
CPU time 212.54 seconds
Started Apr 21 02:00:54 PM PDT 24
Finished Apr 21 02:04:27 PM PDT 24
Peak memory 202184 kb
Host smart-f1b88f7f-dc16-4369-a684-f2a09c94dc6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86879344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.a
dc_ctrl_filters_wakeup_fixed.86879344
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1113703769
Short name T554
Test name
Test status
Simulation time 103727352046 ps
CPU time 530.72 seconds
Started Apr 21 02:01:00 PM PDT 24
Finished Apr 21 02:09:51 PM PDT 24
Peak memory 202644 kb
Host smart-446bff5b-595b-4859-ac69-9d97dd53972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113703769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1113703769
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.333218959
Short name T657
Test name
Test status
Simulation time 29135424744 ps
CPU time 7.29 seconds
Started Apr 21 02:00:58 PM PDT 24
Finished Apr 21 02:01:06 PM PDT 24
Peak memory 202052 kb
Host smart-91b8af9c-a5be-4f7b-adca-f1e586100dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333218959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.333218959
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.49978363
Short name T467
Test name
Test status
Simulation time 3264433185 ps
CPU time 7.41 seconds
Started Apr 21 02:00:56 PM PDT 24
Finished Apr 21 02:01:04 PM PDT 24
Peak memory 202064 kb
Host smart-69271e89-ece1-4bbe-94bc-8bc926de5ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49978363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.49978363
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1582725660
Short name T423
Test name
Test status
Simulation time 5886039029 ps
CPU time 2.37 seconds
Started Apr 21 02:00:51 PM PDT 24
Finished Apr 21 02:00:54 PM PDT 24
Peak memory 202080 kb
Host smart-54a99086-b8e2-483a-b1c3-7cf5cf32aae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582725660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1582725660
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1852646737
Short name T235
Test name
Test status
Simulation time 469031578916 ps
CPU time 506.35 seconds
Started Apr 21 02:01:02 PM PDT 24
Finished Apr 21 02:09:29 PM PDT 24
Peak memory 202564 kb
Host smart-bf5d4d0e-bee3-49b4-a58f-98cb262ca888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852646737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1852646737
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1962740267
Short name T17
Test name
Test status
Simulation time 852492614542 ps
CPU time 270.78 seconds
Started Apr 21 02:01:02 PM PDT 24
Finished Apr 21 02:05:33 PM PDT 24
Peak memory 210876 kb
Host smart-cd1452e5-38a6-45a6-b211-aec87c429222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962740267 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1962740267
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2989243328
Short name T640
Test name
Test status
Simulation time 335159913 ps
CPU time 0.76 seconds
Started Apr 21 02:01:23 PM PDT 24
Finished Apr 21 02:01:24 PM PDT 24
Peak memory 201984 kb
Host smart-da25993d-9743-4357-85b0-a67224295eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989243328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2989243328
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1289555938
Short name T200
Test name
Test status
Simulation time 522933385359 ps
CPU time 257.6 seconds
Started Apr 21 02:01:15 PM PDT 24
Finished Apr 21 02:05:33 PM PDT 24
Peak memory 202352 kb
Host smart-9d9d77b3-6b4f-477b-aa33-2c4d00d23a41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289555938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1289555938
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1600301365
Short name T776
Test name
Test status
Simulation time 352345626802 ps
CPU time 762.38 seconds
Started Apr 21 02:01:21 PM PDT 24
Finished Apr 21 02:14:03 PM PDT 24
Peak memory 202232 kb
Host smart-534094fe-d199-4e4b-8bde-ee45cec88c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600301365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1600301365
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2438558473
Short name T761
Test name
Test status
Simulation time 164669016711 ps
CPU time 66.08 seconds
Started Apr 21 02:01:11 PM PDT 24
Finished Apr 21 02:02:17 PM PDT 24
Peak memory 202264 kb
Host smart-e8c87508-4651-42da-998e-6a86ece82a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438558473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2438558473
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.442427352
Short name T703
Test name
Test status
Simulation time 165471435270 ps
CPU time 218 seconds
Started Apr 21 02:01:12 PM PDT 24
Finished Apr 21 02:04:50 PM PDT 24
Peak memory 202224 kb
Host smart-636149a0-8408-4cb4-b6fb-00ad322feedc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=442427352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.442427352
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1680724785
Short name T364
Test name
Test status
Simulation time 494766908549 ps
CPU time 1052.5 seconds
Started Apr 21 02:01:07 PM PDT 24
Finished Apr 21 02:18:40 PM PDT 24
Peak memory 202336 kb
Host smart-b3bb3f51-dcd1-419e-87a1-4d39a6bc4d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680724785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1680724785
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2500975102
Short name T420
Test name
Test status
Simulation time 167079303896 ps
CPU time 187.57 seconds
Started Apr 21 02:01:08 PM PDT 24
Finished Apr 21 02:04:16 PM PDT 24
Peak memory 202308 kb
Host smart-fbc639f4-92ed-48c3-9d01-1698099eff3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500975102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2500975102
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.447287186
Short name T193
Test name
Test status
Simulation time 365646962785 ps
CPU time 440.93 seconds
Started Apr 21 02:01:14 PM PDT 24
Finished Apr 21 02:08:35 PM PDT 24
Peak memory 202220 kb
Host smart-9acfd173-9936-4a5f-907d-596b2ba876ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447287186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.447287186
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.757014661
Short name T185
Test name
Test status
Simulation time 403203238230 ps
CPU time 248.77 seconds
Started Apr 21 02:01:14 PM PDT 24
Finished Apr 21 02:05:23 PM PDT 24
Peak memory 202228 kb
Host smart-901d501a-6aba-4bd2-b1cc-8ae927c0b4dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757014661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.757014661
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1226490140
Short name T381
Test name
Test status
Simulation time 29817494839 ps
CPU time 34.44 seconds
Started Apr 21 02:01:17 PM PDT 24
Finished Apr 21 02:01:52 PM PDT 24
Peak memory 202068 kb
Host smart-62ee61dd-9f72-45af-a423-e99248a61d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226490140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1226490140
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1527433682
Short name T410
Test name
Test status
Simulation time 5041461229 ps
CPU time 3.44 seconds
Started Apr 21 02:01:17 PM PDT 24
Finished Apr 21 02:01:20 PM PDT 24
Peak memory 202076 kb
Host smart-2a281c1c-9c97-4f8b-bd72-34428449d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527433682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1527433682
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4146923441
Short name T508
Test name
Test status
Simulation time 6034392274 ps
CPU time 8.1 seconds
Started Apr 21 02:01:03 PM PDT 24
Finished Apr 21 02:01:12 PM PDT 24
Peak memory 202080 kb
Host smart-09e5eca9-b21f-4105-a95c-dc0e0e44e2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146923441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4146923441
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2131171065
Short name T35
Test name
Test status
Simulation time 168335645204 ps
CPU time 165.83 seconds
Started Apr 21 02:01:17 PM PDT 24
Finished Apr 21 02:04:03 PM PDT 24
Peak memory 202304 kb
Host smart-2cfd9604-61ee-43a9-9433-bef6ec9c280f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131171065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2131171065
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4164983533
Short name T22
Test name
Test status
Simulation time 214041493044 ps
CPU time 235.55 seconds
Started Apr 21 02:01:18 PM PDT 24
Finished Apr 21 02:05:14 PM PDT 24
Peak memory 218900 kb
Host smart-1a4bbfbf-46ea-47bb-9ab2-05441a441fe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164983533 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4164983533
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.549274507
Short name T486
Test name
Test status
Simulation time 425196584 ps
CPU time 1.57 seconds
Started Apr 21 02:01:38 PM PDT 24
Finished Apr 21 02:01:40 PM PDT 24
Peak memory 201968 kb
Host smart-bd16e5cb-210f-47c0-b11d-ffe28be0138c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549274507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.549274507
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2119464088
Short name T222
Test name
Test status
Simulation time 349921847813 ps
CPU time 397.48 seconds
Started Apr 21 02:01:27 PM PDT 24
Finished Apr 21 02:08:05 PM PDT 24
Peak memory 202260 kb
Host smart-747029cf-f806-4dd6-8737-fafb38148514
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119464088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2119464088
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2985183490
Short name T777
Test name
Test status
Simulation time 164656075281 ps
CPU time 321.95 seconds
Started Apr 21 02:01:28 PM PDT 24
Finished Apr 21 02:06:50 PM PDT 24
Peak memory 202252 kb
Host smart-a007441f-76d1-46c3-b596-67c328d75bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985183490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2985183490
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2093723729
Short name T676
Test name
Test status
Simulation time 167289562469 ps
CPU time 89.64 seconds
Started Apr 21 02:01:26 PM PDT 24
Finished Apr 21 02:02:56 PM PDT 24
Peak memory 202264 kb
Host smart-9779126d-0a18-40b2-8b4c-3b340f301ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093723729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2093723729
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1046535567
Short name T665
Test name
Test status
Simulation time 333427317573 ps
CPU time 190.93 seconds
Started Apr 21 02:01:23 PM PDT 24
Finished Apr 21 02:04:34 PM PDT 24
Peak memory 202292 kb
Host smart-1949d2bc-569e-43c4-b732-90ea4ede581a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046535567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1046535567
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.925909613
Short name T618
Test name
Test status
Simulation time 333931412635 ps
CPU time 419.67 seconds
Started Apr 21 02:01:24 PM PDT 24
Finished Apr 21 02:08:24 PM PDT 24
Peak memory 202260 kb
Host smart-76911981-20c9-4679-8b79-f73e615ed55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925909613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.925909613
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3395922166
Short name T465
Test name
Test status
Simulation time 160078054984 ps
CPU time 379.83 seconds
Started Apr 21 02:01:22 PM PDT 24
Finished Apr 21 02:07:42 PM PDT 24
Peak memory 202216 kb
Host smart-c47ec414-fc01-4309-bc4d-69fe1c318a9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395922166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3395922166
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3503821209
Short name T188
Test name
Test status
Simulation time 173359239589 ps
CPU time 412.31 seconds
Started Apr 21 02:01:25 PM PDT 24
Finished Apr 21 02:08:18 PM PDT 24
Peak memory 202304 kb
Host smart-76030b27-d336-4e15-a843-58c03c916407
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503821209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3503821209
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.186228219
Short name T434
Test name
Test status
Simulation time 399754841192 ps
CPU time 474.51 seconds
Started Apr 21 02:01:24 PM PDT 24
Finished Apr 21 02:09:18 PM PDT 24
Peak memory 202216 kb
Host smart-80558ea6-8f79-412d-a5c8-bc0944feff46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186228219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.186228219
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1157869774
Short name T230
Test name
Test status
Simulation time 87628532637 ps
CPU time 346.41 seconds
Started Apr 21 02:01:32 PM PDT 24
Finished Apr 21 02:07:19 PM PDT 24
Peak memory 202588 kb
Host smart-ed4c3eec-0f0d-4bad-a17f-3e3ed17f162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157869774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1157869774
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1791888927
Short name T584
Test name
Test status
Simulation time 35243007243 ps
CPU time 43.66 seconds
Started Apr 21 02:01:28 PM PDT 24
Finished Apr 21 02:02:12 PM PDT 24
Peak memory 202076 kb
Host smart-d58084aa-8ef8-46ce-8a54-3dd3f89971d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791888927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1791888927
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.690042801
Short name T398
Test name
Test status
Simulation time 3817525792 ps
CPU time 8.98 seconds
Started Apr 21 02:01:27 PM PDT 24
Finished Apr 21 02:01:36 PM PDT 24
Peak memory 202040 kb
Host smart-9acf8866-fbe0-4331-86e9-ff3c7c03e74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690042801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.690042801
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4033819677
Short name T567
Test name
Test status
Simulation time 5810653404 ps
CPU time 7.22 seconds
Started Apr 21 02:01:21 PM PDT 24
Finished Apr 21 02:01:29 PM PDT 24
Peak memory 202076 kb
Host smart-687f8a0f-3330-44b2-8943-37e0893c620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033819677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4033819677
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1520275496
Short name T108
Test name
Test status
Simulation time 330765763054 ps
CPU time 353.92 seconds
Started Apr 21 02:01:33 PM PDT 24
Finished Apr 21 02:07:27 PM PDT 24
Peak memory 202360 kb
Host smart-83b356ad-41e4-4d63-a59a-5acb0299cf37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520275496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1520275496
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3653364930
Short name T350
Test name
Test status
Simulation time 110877593269 ps
CPU time 201.41 seconds
Started Apr 21 02:01:32 PM PDT 24
Finished Apr 21 02:04:54 PM PDT 24
Peak memory 218676 kb
Host smart-7bbf6c80-0ff2-4929-98d3-5bde14056458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653364930 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3653364930
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3091360187
Short name T616
Test name
Test status
Simulation time 479221554 ps
CPU time 1.16 seconds
Started Apr 21 01:52:51 PM PDT 24
Finished Apr 21 01:52:52 PM PDT 24
Peak memory 201944 kb
Host smart-7b7cdd4b-daa2-47b2-9c31-1aadd2effb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091360187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3091360187
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2688269975
Short name T673
Test name
Test status
Simulation time 190878508971 ps
CPU time 158.4 seconds
Started Apr 21 01:52:46 PM PDT 24
Finished Apr 21 01:55:24 PM PDT 24
Peak memory 202336 kb
Host smart-106db6be-3b0f-490e-a367-32913966d851
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688269975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2688269975
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2503613774
Short name T325
Test name
Test status
Simulation time 167132044190 ps
CPU time 204.57 seconds
Started Apr 21 01:52:39 PM PDT 24
Finished Apr 21 01:56:04 PM PDT 24
Peak memory 202232 kb
Host smart-f764dacb-9701-46b7-b1f9-393e0b4f2935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503613774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2503613774
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2132745175
Short name T156
Test name
Test status
Simulation time 167964330076 ps
CPU time 67.54 seconds
Started Apr 21 01:52:40 PM PDT 24
Finished Apr 21 01:53:48 PM PDT 24
Peak memory 202340 kb
Host smart-e1c9bd6e-475e-4f27-ba9f-faefb93fb682
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132745175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2132745175
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.971276165
Short name T3
Test name
Test status
Simulation time 479403408537 ps
CPU time 167.82 seconds
Started Apr 21 01:52:37 PM PDT 24
Finished Apr 21 01:55:25 PM PDT 24
Peak memory 202256 kb
Host smart-4d0242ee-2624-4938-a7ac-ae7a1b3e9f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971276165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.971276165
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1285359554
Short name T513
Test name
Test status
Simulation time 497588566291 ps
CPU time 157.87 seconds
Started Apr 21 01:52:40 PM PDT 24
Finished Apr 21 01:55:19 PM PDT 24
Peak memory 202232 kb
Host smart-e2a9a916-55f8-4ba5-b7f1-eb57e7b48375
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285359554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1285359554
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1145721899
Short name T603
Test name
Test status
Simulation time 168751177822 ps
CPU time 371.6 seconds
Started Apr 21 01:52:43 PM PDT 24
Finished Apr 21 01:58:55 PM PDT 24
Peak memory 202344 kb
Host smart-02e26590-7aaa-4750-82b2-87349df0ec92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145721899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1145721899
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2836174102
Short name T390
Test name
Test status
Simulation time 414500152937 ps
CPU time 882.3 seconds
Started Apr 21 01:52:42 PM PDT 24
Finished Apr 21 02:07:25 PM PDT 24
Peak memory 202264 kb
Host smart-c9d847db-1618-4526-96a1-981a2ac6058f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836174102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2836174102
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4174339498
Short name T622
Test name
Test status
Simulation time 112637779177 ps
CPU time 393.56 seconds
Started Apr 21 01:52:49 PM PDT 24
Finished Apr 21 01:59:22 PM PDT 24
Peak memory 202668 kb
Host smart-d0f93694-9985-4eb9-a61e-a4b790b7d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174339498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4174339498
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2448927989
Short name T135
Test name
Test status
Simulation time 43516586264 ps
CPU time 11.34 seconds
Started Apr 21 01:52:49 PM PDT 24
Finished Apr 21 01:53:01 PM PDT 24
Peak memory 202068 kb
Host smart-d6898b92-b228-4dab-a979-5bc1a7a9e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448927989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2448927989
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.405363726
Short name T667
Test name
Test status
Simulation time 5106961535 ps
CPU time 13.87 seconds
Started Apr 21 01:52:46 PM PDT 24
Finished Apr 21 01:53:00 PM PDT 24
Peak memory 202120 kb
Host smart-f6628ba4-7020-44b9-b81e-1c2709ebfec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405363726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.405363726
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3187521056
Short name T389
Test name
Test status
Simulation time 5733890716 ps
CPU time 9.65 seconds
Started Apr 21 01:52:38 PM PDT 24
Finished Apr 21 01:52:48 PM PDT 24
Peak memory 202120 kb
Host smart-7efbe2f9-1614-499f-ab63-a264e2b42602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187521056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3187521056
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1525037065
Short name T260
Test name
Test status
Simulation time 202518292804 ps
CPU time 439.59 seconds
Started Apr 21 01:52:52 PM PDT 24
Finished Apr 21 02:00:12 PM PDT 24
Peak memory 202324 kb
Host smart-739dd8da-b431-4193-8d7d-f0ab248853b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525037065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1525037065
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3490502839
Short name T61
Test name
Test status
Simulation time 367765415 ps
CPU time 0.81 seconds
Started Apr 21 01:53:07 PM PDT 24
Finished Apr 21 01:53:08 PM PDT 24
Peak memory 201984 kb
Host smart-863d5513-d77f-45af-95b2-7bf5f902f0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490502839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3490502839
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2281522166
Short name T280
Test name
Test status
Simulation time 328457397528 ps
CPU time 768.61 seconds
Started Apr 21 01:52:57 PM PDT 24
Finished Apr 21 02:05:46 PM PDT 24
Peak memory 202264 kb
Host smart-5fb800a8-87df-4527-9aef-a5055ee7fb2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281522166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2281522166
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3397624908
Short name T367
Test name
Test status
Simulation time 340074696960 ps
CPU time 168.35 seconds
Started Apr 21 01:52:59 PM PDT 24
Finished Apr 21 01:55:47 PM PDT 24
Peak memory 202248 kb
Host smart-bf6ebafd-40db-4892-bbdd-ea873d13f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397624908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3397624908
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1300642365
Short name T218
Test name
Test status
Simulation time 480165975106 ps
CPU time 766.2 seconds
Started Apr 21 01:52:50 PM PDT 24
Finished Apr 21 02:05:37 PM PDT 24
Peak memory 202256 kb
Host smart-02a71c1b-46a5-49d9-818c-9619c2e7658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300642365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1300642365
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.825237243
Short name T463
Test name
Test status
Simulation time 328653559522 ps
CPU time 144.42 seconds
Started Apr 21 01:52:55 PM PDT 24
Finished Apr 21 01:55:20 PM PDT 24
Peak memory 202236 kb
Host smart-3d96525d-34a5-4e60-85dd-43335efd4c44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=825237243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.825237243
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3229306669
Short name T710
Test name
Test status
Simulation time 169176590950 ps
CPU time 429.38 seconds
Started Apr 21 01:52:51 PM PDT 24
Finished Apr 21 02:00:00 PM PDT 24
Peak memory 202304 kb
Host smart-c92d9e9a-bbf3-48ff-a6bb-894fa21035db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229306669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3229306669
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3710252980
Short name T382
Test name
Test status
Simulation time 325950985929 ps
CPU time 796.12 seconds
Started Apr 21 01:52:51 PM PDT 24
Finished Apr 21 02:06:08 PM PDT 24
Peak memory 202236 kb
Host smart-77bf9540-47f7-4177-97e3-e8a17126916c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710252980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3710252980
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3254763093
Short name T93
Test name
Test status
Simulation time 386460729894 ps
CPU time 240.76 seconds
Started Apr 21 01:52:54 PM PDT 24
Finished Apr 21 01:56:55 PM PDT 24
Peak memory 202352 kb
Host smart-8bebe975-a2ae-47e6-b430-78c37e6de0f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254763093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3254763093
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1942720600
Short name T182
Test name
Test status
Simulation time 586024548336 ps
CPU time 1465.25 seconds
Started Apr 21 01:52:57 PM PDT 24
Finished Apr 21 02:17:23 PM PDT 24
Peak memory 202260 kb
Host smart-5f16672b-ebab-4787-89b3-9a325e2c45df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942720600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1942720600
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2569455602
Short name T44
Test name
Test status
Simulation time 85030935471 ps
CPU time 339.8 seconds
Started Apr 21 01:53:04 PM PDT 24
Finished Apr 21 01:58:44 PM PDT 24
Peak memory 202560 kb
Host smart-afdf32f6-7565-4475-b26d-ddd4ceeff07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569455602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2569455602
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3295157565
Short name T718
Test name
Test status
Simulation time 40076499578 ps
CPU time 50.22 seconds
Started Apr 21 01:52:59 PM PDT 24
Finished Apr 21 01:53:50 PM PDT 24
Peak memory 202040 kb
Host smart-7b6d654f-1b19-450f-8d34-17bc840c6ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295157565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3295157565
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1578047501
Short name T407
Test name
Test status
Simulation time 3588041971 ps
CPU time 2.97 seconds
Started Apr 21 01:53:00 PM PDT 24
Finished Apr 21 01:53:03 PM PDT 24
Peak memory 202016 kb
Host smart-a58f9e9e-2263-47b8-af02-50aa331cc025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578047501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1578047501
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2266546338
Short name T767
Test name
Test status
Simulation time 5952226250 ps
CPU time 15.17 seconds
Started Apr 21 01:52:51 PM PDT 24
Finished Apr 21 01:53:07 PM PDT 24
Peak memory 202052 kb
Host smart-3521dc4b-ba4a-4dd5-ade9-f576cd702271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266546338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2266546338
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3458523586
Short name T545
Test name
Test status
Simulation time 417975075 ps
CPU time 1.45 seconds
Started Apr 21 01:53:27 PM PDT 24
Finished Apr 21 01:53:28 PM PDT 24
Peak memory 201976 kb
Host smart-256f8d8c-c9b5-4b33-870e-2a28b6f2bf98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458523586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3458523586
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1130833154
Short name T213
Test name
Test status
Simulation time 524976885692 ps
CPU time 599.19 seconds
Started Apr 21 01:53:15 PM PDT 24
Finished Apr 21 02:03:14 PM PDT 24
Peak memory 202196 kb
Host smart-dc1f11d9-2ae4-42e2-8121-da1d9f6f3ff0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130833154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1130833154
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3315540706
Short name T308
Test name
Test status
Simulation time 429434119998 ps
CPU time 231.47 seconds
Started Apr 21 01:53:20 PM PDT 24
Finished Apr 21 01:57:12 PM PDT 24
Peak memory 202312 kb
Host smart-2190f40f-d0f4-48dc-92a9-caba9c87b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315540706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3315540706
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.4151736532
Short name T147
Test name
Test status
Simulation time 328342262280 ps
CPU time 713.22 seconds
Started Apr 21 01:53:14 PM PDT 24
Finished Apr 21 02:05:08 PM PDT 24
Peak memory 202256 kb
Host smart-92b38d13-3733-4043-b41c-21c80a88bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151736532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.4151736532
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3593833339
Short name T686
Test name
Test status
Simulation time 340634178537 ps
CPU time 213.55 seconds
Started Apr 21 01:53:14 PM PDT 24
Finished Apr 21 01:56:48 PM PDT 24
Peak memory 202244 kb
Host smart-99d31191-2706-4721-8d43-e21d17a88252
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593833339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3593833339
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1759223004
Short name T403
Test name
Test status
Simulation time 161285526902 ps
CPU time 190.17 seconds
Started Apr 21 01:53:11 PM PDT 24
Finished Apr 21 01:56:22 PM PDT 24
Peak memory 202228 kb
Host smart-6a26e46c-6071-48ee-915a-529c21021d8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759223004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1759223004
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1262793186
Short name T790
Test name
Test status
Simulation time 200296793586 ps
CPU time 450.79 seconds
Started Apr 21 01:53:17 PM PDT 24
Finished Apr 21 02:00:48 PM PDT 24
Peak memory 202208 kb
Host smart-087eedda-57a0-4c3b-a1a5-149c9f53659a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262793186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1262793186
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1376286027
Short name T672
Test name
Test status
Simulation time 74397403768 ps
CPU time 287.01 seconds
Started Apr 21 01:53:21 PM PDT 24
Finished Apr 21 01:58:08 PM PDT 24
Peak memory 202620 kb
Host smart-572292ea-787c-4bfb-aaa0-f852334516dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376286027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1376286027
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1662481139
Short name T619
Test name
Test status
Simulation time 36368071982 ps
CPU time 13.44 seconds
Started Apr 21 01:53:20 PM PDT 24
Finished Apr 21 01:53:34 PM PDT 24
Peak memory 202072 kb
Host smart-e874d4ae-a191-4056-9ac3-89a23882cd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662481139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1662481139
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1134059074
Short name T392
Test name
Test status
Simulation time 3875948203 ps
CPU time 11.22 seconds
Started Apr 21 01:53:23 PM PDT 24
Finished Apr 21 01:53:34 PM PDT 24
Peak memory 202072 kb
Host smart-164d0d11-098b-41a1-9acd-43d9e996dcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134059074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1134059074
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1131636022
Short name T496
Test name
Test status
Simulation time 5699124331 ps
CPU time 4.05 seconds
Started Apr 21 01:53:08 PM PDT 24
Finished Apr 21 01:53:12 PM PDT 24
Peak memory 202008 kb
Host smart-e8365ec6-11ea-4f31-9d7a-f594dd913f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131636022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1131636022
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3946860038
Short name T765
Test name
Test status
Simulation time 829334468579 ps
CPU time 1196.28 seconds
Started Apr 21 01:53:26 PM PDT 24
Finished Apr 21 02:13:22 PM PDT 24
Peak memory 202356 kb
Host smart-683da24b-3c62-4153-99cb-fe9947b1daab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946860038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3946860038
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2844434973
Short name T531
Test name
Test status
Simulation time 476417625538 ps
CPU time 298.36 seconds
Started Apr 21 01:53:24 PM PDT 24
Finished Apr 21 01:58:22 PM PDT 24
Peak memory 211000 kb
Host smart-7173ceda-a48a-489d-87a6-f3cdb4ff8fbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844434973 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2844434973
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1856228789
Short name T577
Test name
Test status
Simulation time 453682401 ps
CPU time 0.77 seconds
Started Apr 21 01:53:46 PM PDT 24
Finished Apr 21 01:53:47 PM PDT 24
Peak memory 201984 kb
Host smart-40908913-5954-4371-bbc7-33c356c17027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856228789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1856228789
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3829312784
Short name T615
Test name
Test status
Simulation time 330922243596 ps
CPU time 178.39 seconds
Started Apr 21 01:53:39 PM PDT 24
Finished Apr 21 01:56:38 PM PDT 24
Peak memory 202252 kb
Host smart-62af633d-e0af-4fff-9e36-45e3081e4864
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829312784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3829312784
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3364809116
Short name T154
Test name
Test status
Simulation time 340583041163 ps
CPU time 81.51 seconds
Started Apr 21 01:53:37 PM PDT 24
Finished Apr 21 01:54:59 PM PDT 24
Peak memory 202216 kb
Host smart-4c65446d-944f-48aa-b5b6-84a0bd5babd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364809116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3364809116
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1637948260
Short name T327
Test name
Test status
Simulation time 335126013013 ps
CPU time 381.28 seconds
Started Apr 21 01:53:35 PM PDT 24
Finished Apr 21 01:59:57 PM PDT 24
Peak memory 202360 kb
Host smart-9dc348e3-fc1a-4744-9900-ca3484e0a998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637948260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1637948260
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3798019668
Short name T388
Test name
Test status
Simulation time 157836494298 ps
CPU time 351.26 seconds
Started Apr 21 01:53:36 PM PDT 24
Finished Apr 21 01:59:27 PM PDT 24
Peak memory 202252 kb
Host smart-cee06068-4997-4f83-bd53-43d6af98e601
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798019668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3798019668
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.491187740
Short name T358
Test name
Test status
Simulation time 327619258408 ps
CPU time 409.38 seconds
Started Apr 21 01:53:29 PM PDT 24
Finished Apr 21 02:00:18 PM PDT 24
Peak memory 202252 kb
Host smart-1ac101d5-24ea-4832-8910-61adaa930d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491187740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.491187740
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3568958184
Short name T588
Test name
Test status
Simulation time 332381983758 ps
CPU time 705.23 seconds
Started Apr 21 01:53:32 PM PDT 24
Finished Apr 21 02:05:17 PM PDT 24
Peak memory 202320 kb
Host smart-5a9204e5-96c0-4684-a4d2-e9c4d6ceffc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568958184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3568958184
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.67199447
Short name T278
Test name
Test status
Simulation time 542646927283 ps
CPU time 612.2 seconds
Started Apr 21 01:53:35 PM PDT 24
Finished Apr 21 02:03:48 PM PDT 24
Peak memory 202388 kb
Host smart-2f6d572e-aa24-45c8-80de-4d4e49deb236
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67199447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wa
keup.67199447
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.194625867
Short name T475
Test name
Test status
Simulation time 406617668016 ps
CPU time 234.62 seconds
Started Apr 21 01:53:37 PM PDT 24
Finished Apr 21 01:57:32 PM PDT 24
Peak memory 202224 kb
Host smart-64abb8e4-2553-4d32-ba57-26135196d81a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194625867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.194625867
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1492663053
Short name T506
Test name
Test status
Simulation time 77345911247 ps
CPU time 296.46 seconds
Started Apr 21 01:53:41 PM PDT 24
Finished Apr 21 01:58:37 PM PDT 24
Peak memory 202640 kb
Host smart-b4632da9-4442-4403-9e79-2280cc13f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492663053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1492663053
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.552391766
Short name T768
Test name
Test status
Simulation time 33179875890 ps
CPU time 84.49 seconds
Started Apr 21 01:53:38 PM PDT 24
Finished Apr 21 01:55:02 PM PDT 24
Peak memory 202076 kb
Host smart-afd0bc4f-f25d-4874-89c0-5fdff9d72d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552391766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.552391766
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3211787642
Short name T549
Test name
Test status
Simulation time 5570128951 ps
CPU time 1.48 seconds
Started Apr 21 01:53:38 PM PDT 24
Finished Apr 21 01:53:40 PM PDT 24
Peak memory 202116 kb
Host smart-a297412e-d0d3-4c1d-bb6c-132d7d12453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211787642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3211787642
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1784039956
Short name T469
Test name
Test status
Simulation time 5966631665 ps
CPU time 8.67 seconds
Started Apr 21 01:53:29 PM PDT 24
Finished Apr 21 01:53:38 PM PDT 24
Peak memory 202060 kb
Host smart-bdefeb63-5a45-4077-af68-ec1390218df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784039956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1784039956
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1166386117
Short name T41
Test name
Test status
Simulation time 290431468778 ps
CPU time 531.51 seconds
Started Apr 21 01:53:44 PM PDT 24
Finished Apr 21 02:02:36 PM PDT 24
Peak memory 213564 kb
Host smart-bb04cbf5-bcd2-492c-9ce9-8186ee867425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166386117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1166386117
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1228799988
Short name T681
Test name
Test status
Simulation time 244865983323 ps
CPU time 151 seconds
Started Apr 21 01:53:39 PM PDT 24
Finished Apr 21 01:56:11 PM PDT 24
Peak memory 210632 kb
Host smart-b0773898-2beb-48be-a53a-76edaf015508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228799988 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1228799988
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3426065407
Short name T402
Test name
Test status
Simulation time 307395524 ps
CPU time 1.34 seconds
Started Apr 21 01:54:12 PM PDT 24
Finished Apr 21 01:54:13 PM PDT 24
Peak memory 201968 kb
Host smart-539d874d-fb01-4139-8de6-1f3720476c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426065407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3426065407
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.303260727
Short name T298
Test name
Test status
Simulation time 165952636917 ps
CPU time 50.09 seconds
Started Apr 21 01:54:04 PM PDT 24
Finished Apr 21 01:54:54 PM PDT 24
Peak memory 202248 kb
Host smart-748ade10-6058-4fd0-ab1e-799644f83ab5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303260727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.303260727
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2257109766
Short name T247
Test name
Test status
Simulation time 164674433845 ps
CPU time 62.07 seconds
Started Apr 21 01:53:53 PM PDT 24
Finished Apr 21 01:54:55 PM PDT 24
Peak memory 202340 kb
Host smart-87273b16-e376-450c-88d5-429ef96b86f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257109766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2257109766
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1322860800
Short name T74
Test name
Test status
Simulation time 322968510266 ps
CPU time 180.14 seconds
Started Apr 21 01:53:48 PM PDT 24
Finished Apr 21 01:56:49 PM PDT 24
Peak memory 202248 kb
Host smart-7577583f-eee0-4c64-ae75-44c81834bac3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322860800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1322860800
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2597373808
Short name T646
Test name
Test status
Simulation time 164298003382 ps
CPU time 182 seconds
Started Apr 21 01:53:47 PM PDT 24
Finished Apr 21 01:56:49 PM PDT 24
Peak memory 202344 kb
Host smart-381ffcb1-1e13-41e8-92f7-4445df135a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597373808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2597373808
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2316762317
Short name T617
Test name
Test status
Simulation time 334329274793 ps
CPU time 753.65 seconds
Started Apr 21 01:53:50 PM PDT 24
Finished Apr 21 02:06:23 PM PDT 24
Peak memory 202316 kb
Host smart-bbb8e161-414a-485a-8721-a664ddcee19d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316762317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2316762317
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1176786481
Short name T707
Test name
Test status
Simulation time 392770555753 ps
CPU time 177.76 seconds
Started Apr 21 01:53:58 PM PDT 24
Finished Apr 21 01:56:56 PM PDT 24
Peak memory 202264 kb
Host smart-5548bdb6-cce1-41e2-a55c-839e70b70ca4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176786481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1176786481
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2567223928
Short name T413
Test name
Test status
Simulation time 600427559538 ps
CPU time 321.49 seconds
Started Apr 21 01:54:02 PM PDT 24
Finished Apr 21 01:59:24 PM PDT 24
Peak memory 202108 kb
Host smart-5a58ed4c-e1ce-41dc-ae3c-ba9e955c5b0f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567223928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2567223928
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2343758150
Short name T226
Test name
Test status
Simulation time 82915527396 ps
CPU time 465.49 seconds
Started Apr 21 01:54:04 PM PDT 24
Finished Apr 21 02:01:50 PM PDT 24
Peak memory 202660 kb
Host smart-746ece86-558d-4dff-80ca-827d4bf1becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343758150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2343758150
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4243440561
Short name T723
Test name
Test status
Simulation time 34466323509 ps
CPU time 20.47 seconds
Started Apr 21 01:54:06 PM PDT 24
Finished Apr 21 01:54:26 PM PDT 24
Peak memory 202120 kb
Host smart-83d7e33e-c39b-4cd1-b375-b034819ccfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243440561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4243440561
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1798991401
Short name T458
Test name
Test status
Simulation time 5158455193 ps
CPU time 6.75 seconds
Started Apr 21 01:54:07 PM PDT 24
Finished Apr 21 01:54:14 PM PDT 24
Peak memory 202064 kb
Host smart-f9dac229-b7da-404f-8a8e-6d420591bd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798991401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1798991401
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1814855685
Short name T72
Test name
Test status
Simulation time 5480380765 ps
CPU time 5.07 seconds
Started Apr 21 01:53:47 PM PDT 24
Finished Apr 21 01:53:52 PM PDT 24
Peak memory 202008 kb
Host smart-a8afb91c-4c09-4e8c-83c6-53791310a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814855685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1814855685
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3222720906
Short name T330
Test name
Test status
Simulation time 157688850904 ps
CPU time 396.14 seconds
Started Apr 21 01:54:11 PM PDT 24
Finished Apr 21 02:00:47 PM PDT 24
Peak memory 218080 kb
Host smart-7dbeefcb-e20d-42d0-8494-e64a7c282277
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222720906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3222720906
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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