Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6932	1			T1	57		T2	20		T5	44
testmodes[AdcCtrlTestmodeNormal]	5456	1			T1	60		T3	3		T5	28
testmodes[AdcCtrlTestmodeLowpower]	5630	1			T1	47		T4	12		T5	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3815	1			T1	17		T2	19		T5	31
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1679	1			T1	21		T5	11		T16	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1334	1			T1	19		T5	2		T12	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1673	1			T1	22		T5	11		T16	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2060	1			T1	24		T3	2		T5	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1378	1			T1	14		T5	4		T10	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1327	1			T1	17		T5	2		T12	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1379	1			T1	15		T5	3		T10	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2674	1			T1	14		T4	11		T5	4