Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20464

1

T1

164

T2

20

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

5723

1

T3

3

T6

4

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20272

1

T1

164

T2

20

T4

12

auto[1]

5915

1

T3

3

T6

3

T7

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T210	16		-	-		-	-
values[0]	72	1			T145	1		T211	12		T192	1
values[1]	573	1			T6	1		T10	18		T11	20
values[2]	479	1			T12	3		T45	21		T47	1
values[3]	652	1			T120	10		T212	10		T29	10
values[4]	807	1			T6	8		T14	12		T45	33
values[5]	633	1			T48	9		T144	18		T29	11
values[6]	633	1			T10	26		T46	13		T48	4
values[7]	858	1			T7	5		T45	2		T47	1
values[8]	752	1			T9	12		T10	7		T47	3
values[9]	3666	1			T3	3		T6	3		T9	5
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	774	1			T6	1		T10	18		T11	20
values[1]	2737	1			T3	3		T12	3		T13	3
values[2]	580	1			T45	33		T120	10		T212	10
values[3]	839	1			T6	8		T14	12		T47	1
values[4]	656	1			T48	4		T144	18		T30	14
values[5]	627	1			T7	5		T10	26		T46	13
values[6]	804	1			T45	2		T47	1		T127	15
values[7]	882	1			T9	12		T10	7		T47	3
values[8]	1044	1			T6	3		T9	5		T12	15
values[9]	180	1			T125	5		T182	1		T213	25
minimum	17064	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	9		T46	7		T144	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	1		T11	11		T45	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T35	1		T122	12		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1501	1			T3	3		T12	2		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T29	1		T151	1		T146	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T45	18		T120	7		T212	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	1		T123	3		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	7		T47	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T48	1		T30	14		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T144	11		T214	14		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T10	13		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T121	1		T29	1		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T47	1		T145	1		T212	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T45	1		T127	15		T150	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T120	7		T128	12		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	4		T10	5		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T9	3		T12	9		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	1		T124	12		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T125	3		T182	1		T213	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T143	1		T216	9		T217	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T145	1		T218	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	9		T219	2		T184	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	9		T45	12		T17	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T122	11		T39	1		T219	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	873	1			T12	1		T48	11		T140	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	9		T151	11		T146	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T45	15		T120	3		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	7		T142	3		T133	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	5		T48	8		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	3		T220	1		T221	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	7		T135	12		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	4		T10	13		T119	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	10		T129	10		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T145	15		T122	3		T124	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	1		T150	2		T183	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T120	7		T128	11		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	8		T10	2		T129	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	2		T12	6		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	2		T124	16		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T125	2		T213	15		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T143	10		T216	7		T217	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T210	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T225	1		T226	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T145	1		T211	7		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	9		T46	7		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	1		T11	11		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T35	1		T39	3		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	2		T45	9		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T29	1		T122	12		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T120	7		T212	10		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T123	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	7		T45	18		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T30	14		T130	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	1		T144	11		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	13		T46	13		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T227	1		T228	9		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	1		T47	1		T127	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T45	1		T121	1		T129	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T120	7		T119	3		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	4		T10	5		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	436	1			T9	3		T12	9		T128	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1789	1			T3	3		T6	1		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T210	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T211	5		T230	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	9		T219	2		T184	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	9		T20	5		T37	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	1		T219	13		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T12	1		T45	12		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	9		T122	11		T219	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T120	3		T143	2		T136	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	7		T142	3		T151	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	5		T45	15		T133	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T133	7		T220	1		T221	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	8		T144	7		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T10	13		T48	3		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T227	1		T228	7		T164	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	4		T145	15		T122	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	1		T129	10		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	7		T119	14		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	8		T10	2		T231	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T9	2		T12	6		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1147	1			T6	2		T140	10		T232	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	10		T46	1		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	1		T11	10		T45	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T35	1		T122	12		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1190	1			T3	3		T12	2		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	10		T151	12		T146	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T45	16		T120	4		T212	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	8		T123	1		T142	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T14	10		T47	1		T48	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T48	4		T30	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	8		T214	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	5		T10	14		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T121	1		T29	11		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	1		T145	16		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	2		T127	1		T150	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T120	8		T128	12		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	9		T10	3		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	3		T12	9		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T6	3		T124	17		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T125	3		T182	1		T213	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T143	11		T216	8		T217	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T145	1		T218	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	8		T46	6		T144	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	10		T45	8		T17	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T122	11		T39	1		T190	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1184	1			T12	1		T44	25		T48	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	11		T171	17		T233	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T45	17		T120	6		T212	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T123	2		T158	16		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	2		T30	10		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T30	13		T158	2		T220	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	10		T214	13		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T10	12		T46	12		T127	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	10		T223	12		T235	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T212	2		T122	11		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	14		T150	4		T168	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T120	6		T128	11		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	3		T10	4		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	2		T12	6		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T124	11		T40	2		T236	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T125	2		T213	9		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T216	8		T217	10		T233	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T218	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T210	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T225	1		T226	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T145	1		T211	9		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	10		T46	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	1		T11	10		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T35	1		T39	3		T219	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	2		T45	13		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T29	10		T122	12		T219	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T120	4		T212	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	8		T123	1		T142	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T14	10		T45	16		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T30	1		T130	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T48	9		T144	8		T29	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	14		T46	1		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T227	2		T228	8		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	5		T47	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	2		T121	1		T129	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T120	8		T119	15		T39	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	9		T10	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T9	3		T12	9		T128	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1513	1			T3	3		T6	3		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T210	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T211	3		T237	17		T230	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	8		T46	6		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T11	10		T20	3		T238	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	1		T190	5		T214	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	1		T45	8		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T122	11		T150	9		T146	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T120	6		T212	9		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T123	2		T234	6		T239	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	2		T45	17		T30	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T30	13		T158	18		T220	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T144	10		T123	12		T132	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	12		T46	12		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T228	8		T164	2		T239	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T127	1		T212	2		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T129	10		T150	4		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T120	6		T119	2		T125	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	3		T10	4		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T9	2		T12	6		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1423	1			T44	25		T129	12		T124	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22436

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3751

1

T6

3

T9

12

T10

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20429

1

T1

164

T2

20

T4

12

auto[1]

5758

1

T3

3

T7

5

T9

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	223	1			T9	12		T30	14		T142	4
values[0]	5	1			T219	3		T240	1		T241	1
values[1]	696	1			T11	20		T45	21		T47	1
values[2]	681	1			T12	3		T46	13		T120	10
values[3]	802	1			T47	4		T48	32		T17	20
values[4]	647	1			T128	23		T219	11		T40	6
values[5]	2700	1			T3	3		T13	3		T38	2
values[6]	673	1			T6	8		T14	12		T121	1
values[7]	598	1			T6	1		T127	2		T144	20
values[8]	925	1			T7	5		T10	33		T127	15
values[9]	1191	1			T6	3		T9	5		T10	18
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	675	1			T45	21		T47	1		T120	14
values[1]	657	1			T12	3		T46	13		T47	1
values[2]	748	1			T47	3		T48	23		T17	20
values[3]	2857	1			T3	3		T13	3		T38	2
values[4]	497	1			T144	18		T145	16		T143	15
values[5]	617	1			T6	9		T14	12		T127	2
values[6]	769	1			T10	7		T144	35		T145	1
values[7]	829	1			T7	5		T9	5		T10	26
values[8]	1100	1			T6	3		T10	18		T12	15
values[9]	176	1			T9	12		T181	3		T30	14
minimum	17262	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T45	9		T47	1		T120	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T123	13		T190	10		T150	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	2		T46	13		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T47	1		T130	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T47	3		T214	17		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T48	12		T17	10		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T40	5		T236	7		T150	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T144	11		T143	2		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T145	1		T243	1		T238	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	2		T127	2		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	7		T123	13		T119	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	5		T144	10		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T144	15		T29	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T9	3		T127	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	13		T119	3		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T45	19		T46	7		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T6	1		T10	9		T12	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T181	1		T122	12		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T9	4		T30	14		T204	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16965	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T244	8		T200	4		T245	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T45	12		T120	7		T39	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T190	2		T150	9		T84	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T48	8		T120	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T223	1		T246	9		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T222	1		T217	4		T248	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	11		T17	10		T29	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T128	11		T140	10		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	1		T150	8		T134	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T144	7		T143	13		T242	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	15		T238	9		T249	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	7		T133	7		T213	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	5		T119	8		T39	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	2		T144	10		T124	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T29	10		T125	3		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	4		T9	2		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	13		T119	14		T151	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T45	16		T122	11		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	2		T10	9		T12	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T181	2		T122	3		T133	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T9	8		T204	4		T250	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	3		T11	9		T12	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T200	1		T245	11		T216	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T133	1		T221	21		T153	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T9	4		T30	14		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T219	1		T240	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	11		T45	9		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T123	13		T190	10		T150	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	2		T46	13		T120	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T131	1		T182	1		T214	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T47	3		T48	1		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T47	1		T48	12		T17	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T128	12		T19	1		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T219	1		T40	5		T236	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T145	1		T134	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T121	1		T213	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	7		T123	13		T119	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T127	2		T144	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	1		T125	5		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	1		T10	5		T127	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T10	13		T144	15		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	3		T45	19		T46	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T6	1		T10	9		T12	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T133	3		T221	16		T251	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T9	8		T142	3		T228	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T219	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	9		T45	12		T120	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T190	2		T150	9		T222	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T120	3		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T84	2		T223	1		T146	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	8		T132	12		T217	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	11		T17	10		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T128	11		T19	1		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T219	10		T40	1		T150	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T140	10		T144	7		T232	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T145	15		T134	5		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	7		T213	15		T79	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	5		T119	8		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	10		T133	7		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T125	3		T133	11		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	4		T10	2		T124	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	13		T29	10		T119	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	2		T45	16		T181	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	2		T10	9		T12	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2