Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20436

1

T1

164

T2

20

T4

12

auto[ADC_CTRL_FILTER_COND_OUT]

5751

1

T3

3

T6

4

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20270

1

T1

164

T2

20

T4

12

auto[1]

5917

1

T3

3

T6

3

T7

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	280	1			T9	5		T12	15		T144	20
values[0]	68	1			T211	12		T294	1		T237	18
values[1]	590	1			T6	1		T10	18		T11	20
values[2]	482	1			T12	3		T45	21		T47	1
values[3]	600	1			T120	10		T212	10		T29	10
values[4]	902	1			T6	8		T14	12		T45	33
values[5]	540	1			T48	13		T144	18		T30	14
values[6]	676	1			T7	5		T10	26		T46	13
values[7]	801	1			T45	2		T47	1		T127	2
values[8]	808	1			T9	12		T10	7		T47	3
values[9]	3394	1			T3	3		T6	3		T13	3
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	648	1			T6	1		T10	18		T11	20
values[1]	2727	1			T3	3		T12	3		T13	3
values[2]	543	1			T45	33		T120	10		T212	10
values[3]	846	1			T6	8		T14	12		T47	1
values[4]	670	1			T48	4		T144	18		T30	14
values[5]	619	1			T7	5		T10	26		T46	13
values[6]	794	1			T45	2		T47	4		T121	1
values[7]	833	1			T9	12		T10	7		T120	14
values[8]	1188	1			T6	3		T9	5		T12	15
values[9]	87	1			T125	5		T213	25		T210	16
minimum	17232	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	9		T144	15		T184	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	1		T11	11		T45	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T29	1		T35	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1510	1			T3	3		T12	2		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T212	10		T146	12		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T45	18		T120	7		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	1		T123	3		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	7		T47	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	14		T130	1		T158	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T48	1		T144	11		T214	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	1		T10	13		T46	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T29	1		T129	11		T223	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T47	1		T145	1		T212	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T45	1		T47	3		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T120	7		T128	12		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	4		T10	5		T127	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T9	3		T12	9		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T6	1		T124	12		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T125	3		T213	10		T210	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T233	12		T161	18		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16989	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T20	5		T307	1		T192	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	9		T184	8		T134	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	9		T45	12		T17	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	9		T122	11		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	886	1			T12	1		T48	11		T140	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T146	13		T148	4		T289	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T45	15		T120	3		T151	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	7		T142	3		T133	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	5		T48	8		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T220	1		T221	16		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	3		T144	7		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T7	4		T10	13		T119	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	10		T129	10		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T145	15		T122	3		T124	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	1		T150	2		T183	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T120	7		T128	11		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	8		T10	2		T129	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	2		T12	6		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	2		T124	16		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T125	2		T213	15		T210	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T20	5		T308	7		T230	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T9	3		T12	9		T144	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T19	1		T84	3		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T211	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T294	1		T237	18		T230	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	9		T46	7		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	1		T11	11		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	1		T39	3		T190	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	2		T45	9		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T212	10		T29	1		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T120	7		T215	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T123	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	7		T45	18		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	14		T130	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	2		T144	11		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	1		T10	13		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T29	1		T214	14		T223	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T47	1		T127	2		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T45	1		T121	1		T129	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T120	7		T119	3		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	4		T10	5		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T128	12		T145	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1713	1			T3	3		T6	1		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T9	2		T12	6		T144	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T19	1		T84	2		T143	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T211	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T230	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	9		T219	2		T184	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	9		T17	10		T133	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T39	1		T136	10		T254	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T12	1		T45	12		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	9		T122	11		T219	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T120	3		T143	2		T247	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	7		T142	3		T223	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T14	5		T45	15		T133	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T133	7		T220	1		T221	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	11		T144	7		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	4		T10	13		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	10		T223	9		T227	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T145	15		T122	3		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	1		T129	10		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T120	7		T119	14		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	8		T10	2		T129	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T128	11		T145	10		T181	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1095	1			T6	2		T140	10		T232	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	10		T144	1		T184	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	1		T11	10		T45	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T29	10		T35	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1203	1			T3	3		T12	2		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T212	1		T146	14		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T45	16		T120	4		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	8		T123	1		T142	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T14	10		T47	1		T48	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	1		T130	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	4		T144	8		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	5		T10	14		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	11		T129	11		T223	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	1		T145	16		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T45	2		T47	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T120	8		T128	12		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	9		T10	3		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T9	3		T12	9		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T6	3		T124	17		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T125	3		T213	16		T210	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T233	1		T161	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17088	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T20	7		T307	1		T192	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	8		T144	14		T184	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	10		T45	8		T17	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T122	11		T39	1		T190	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1193	1			T12	1		T44	25		T48	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T212	9		T146	11		T171	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T45	17		T120	6		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T123	2		T158	16		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	2		T30	10		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T30	13		T158	2		T168	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	10		T214	13		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	12		T46	12		T127	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T129	10		T223	12		T280	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T212	2		T122	11		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T47	2		T150	4		T168	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T120	6		T128	11		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	3		T10	4		T127	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T9	2		T12	6		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T124	11		T40	2		T236	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T125	2		T213	9		T210	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T233	11		T161	17		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T46	6		T292	12		T211	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T20	3		T237	17		T218	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T9	3		T12	9		T144	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T19	2		T84	3		T143	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T211	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T294	1		T237	1		T230	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	10		T46	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	1		T11	10		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T35	1		T39	3		T190	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	2		T45	13		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T212	1		T29	10		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T120	4		T215	1		T143	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	8		T123	1		T142	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T14	10		T45	16		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	1		T130	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	13		T144	8		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	5		T10	14		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	11		T214	1		T223	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T47	1		T127	1		T145	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T45	2		T121	1		T129	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T120	8		T119	15		T39	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	9		T10	3		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T128	12		T145	11		T181	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1448	1			T3	3		T6	3		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T9	2		T12	6		T144	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T84	2		T221	2		T233	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T211	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T237	17		T230	11		T251	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	8		T46	6		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T11	10		T17	5		T20	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	1		T190	5		T214	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	1		T45	8		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T212	9		T122	11		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T120	6		T169	9		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T123	2		T234	6		T170	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	2		T45	17		T30	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	13		T158	18		T220	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T144	10		T123	12		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	12		T46	12		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T214	13		T223	12		T228	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T127	1		T212	2		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T129	10		T150	4		T168	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T120	6		T119	2		T125	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	3		T10	4		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T128	11		T122	13		T213	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1360	1			T44	25		T124	11		T40	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10