Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22353

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3834

1

T6

3

T7

5

T9

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20273

1

T1

164

T2

20

T4

12

auto[1]

5914

1

T3

3

T10

26

T12

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	68	1			T228	23		T309	35		T310	2
values[0]	54	1			T240	1		T311	16		T281	14
values[1]	605	1			T11	20		T45	21		T47	1
values[2]	723	1			T12	3		T46	13		T47	3
values[3]	751	1			T47	1		T48	9		T17	20
values[4]	707	1			T48	23		T219	11		T19	2
values[5]	2692	1			T3	3		T13	3		T38	2
values[6]	626	1			T6	8		T14	12		T121	1
values[7]	646	1			T6	1		T127	2		T144	20
values[8]	882	1			T7	5		T10	33		T47	1
values[9]	1387	1			T6	3		T9	17		T10	18
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	894	1			T11	20		T45	21		T47	1
values[1]	623	1			T12	3		T48	9		T120	10
values[2]	793	1			T46	13		T47	4		T48	23
values[3]	2790	1			T3	3		T13	3		T38	2
values[4]	516	1			T6	8		T144	18		T145	16
values[5]	648	1			T6	1		T14	12		T127	2
values[6]	744	1			T10	7		T144	35		T145	1
values[7]	829	1			T7	5		T9	5		T10	26
values[8]	1044	1			T6	3		T10	18		T12	15
values[9]	234	1			T9	12		T48	4		T181	3
minimum	17072	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T11	11		T45	9		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T120	7		T123	13		T190	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	2		T48	1		T120	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	10		T123	3		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T46	13		T47	3		T214	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T47	1		T48	12		T125	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	1		T40	5		T236	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	1		T144	11		T190	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T145	1		T243	1		T252	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T127	2		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	7		T123	13		T119	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	5		T145	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T144	25		T29	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T127	15		T212	3		T30	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	1		T9	3		T10	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T45	19		T46	7		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T6	1		T10	9		T12	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T181	1		T122	12		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T9	4		T48	1		T30	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T312	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	9		T45	12		T39	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T120	7		T190	2		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T48	8		T120	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	10		T132	12		T223	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T222	1		T268	6		T217	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T48	11		T125	2		T219	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T128	11		T140	10		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	9		T40	1		T20	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T6	7		T144	7		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T145	15		T238	9		T249	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T133	7		T213	15		T79	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	5		T119	8		T39	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	2		T124	16		T313	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T144	10		T29	10		T125	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T219	13		T41	4		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	4		T9	2		T10	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T45	16		T122	11		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	2		T10	9		T12	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T181	2		T122	3		T133	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T9	8		T48	3		T204	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T312	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T228	12		T309	16		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T310	1		T314	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T240	1		T281	14		T315	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T311	1		T24	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	11		T45	9		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T120	7		T123	13		T190	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	2		T46	13		T47	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T131	1		T214	14		T84	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	1		T214	17		T168	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T47	1		T17	10		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T19	1		T222	1		T168	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T48	12		T219	1		T236	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T145	1		T243	1		T169	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	1		T121	1		T213	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	7		T123	13		T119	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	1		T127	2		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T144	10		T35	1		T119	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	5		T127	15		T212	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T7	1		T10	13		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T45	19		T46	7		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	480	1			T6	1		T9	7		T10	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T228	11		T309	19		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T310	1		T314	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T315	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T311	15		T24	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	9		T45	12		T39	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T120	7		T190	2		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T120	3		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T84	2		T223	1		T231	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	8		T217	4		T316	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	10		T29	9		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T19	1		T222	1		T183	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	11		T219	10		T150	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	894	1			T128	11		T140	10		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T145	15		T240	8		T249	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T6	7		T213	15		T79	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	5		T119	8		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T133	7		T136	15		T164	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	10		T119	14		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	2		T124	16		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	4		T10	13		T29	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T45	16		T181	2		T122	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T6	2		T9	10		T10	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T11	10		T45	13		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T120	8		T123	1		T190	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	2		T48	9		T120	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	15		T123	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	1		T47	1		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T47	1		T48	12		T125	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	10		T40	4		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	8		T144	8		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T145	16		T243	1		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	1		T127	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	10		T123	1		T119	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	3		T145	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T144	12		T29	11		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T127	1		T212	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	5		T9	3		T10	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T45	18		T46	1		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	3		T10	10		T12	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T181	3		T122	4		T133	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T9	9		T48	4		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T312	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	10		T45	8		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T120	6		T123	12		T190	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	1		T120	6		T212	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	5		T123	2		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	12		T47	2		T214	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T48	11		T125	2		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T44	25		T128	11		T122	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	2		T236	6		T20	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T144	10		T190	5		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T252	12		T238	9		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T127	1		T213	9		T79	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	2		T123	12		T119	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	4		T124	11		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T144	23		T125	4		T236	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T127	14		T212	2		T30	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	2		T10	12		T119	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T45	17		T46	6		T122	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T10	8		T12	6		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T122	11		T272	1		T153	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T9	3		T30	13		T204	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T312	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T228	12		T309	20		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T310	2		T314	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T240	1		T281	1		T315	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T311	16		T24	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	10		T45	13		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T120	8		T123	1		T190	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	2		T46	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	1		T214	1		T84	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T48	9		T214	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T47	1		T17	15		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	2		T222	2		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T48	12		T219	11		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T145	16		T243	1		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	8		T121	1		T213	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	10		T123	1		T119	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	1		T127	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T144	11		T35	1		T119	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	3		T127	1		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	5		T10	14		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T45	18		T46	1		T181	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T6	3		T9	12		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T228	11		T309	15		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T281	13		T315	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T24	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	10		T45	8		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T120	6		T123	12		T190	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	1		T46	12		T47	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T214	13		T84	2		T231	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T214	16		T168	4		T244	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	5		T123	2		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T168	11		T317	12		T248	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	11		T236	6		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T44	25		T128	11		T144	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T169	9		T252	12		T240	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T213	9		T79	10		T257	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	2		T123	12		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T127	1		T136	2		T169	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T144	9		T119	2		T125	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	4		T127	14		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	12		T144	14		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T45	17		T46	6		T122	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T9	5		T10	8		T12	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10