Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22121

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

4066

1

T6

1

T7

5

T10

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20296

1

T1

164

T2

20

T4

12

auto[1]

5891

1

T3

3

T6

9

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T145	11		T318	19		-	-
values[0]	78	1			T127	15		T147	17		T319	1
values[1]	682	1			T47	3		T145	1		T17	20
values[2]	871	1			T7	5		T47	1		T122	19
values[3]	743	1			T10	18		T46	7		T123	13
values[4]	758	1			T6	1		T127	2		T144	15
values[5]	572	1			T47	1		T121	1		T181	3
values[6]	648	1			T11	20		T12	18		T45	35
values[7]	667	1			T10	26		T45	21		T48	4
values[8]	765	1			T6	8		T9	12		T10	7
values[9]	3327	1			T3	3		T6	3		T9	5
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	955	1			T47	3		T127	15		T145	1
values[1]	925	1			T7	5		T10	18		T47	1
values[2]	719	1			T46	7		T130	2		T39	5
values[3]	554	1			T6	1		T127	2		T121	1
values[4]	666	1			T12	3		T45	2		T47	1
values[5]	632	1			T11	20		T12	15		T45	33
values[6]	2785	1			T3	3		T10	26		T13	3
values[7]	752	1			T9	12		T10	7		T144	38
values[8]	902	1			T6	8		T9	5		T47	1
values[9]	188	1			T6	3		T14	12		T46	13
minimum	17109	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T47	3		T145	1		T29	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T127	15		T17	10		T30	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T123	13		T18	1		T124	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T7	1		T10	9		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	1		T39	2		T190	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T46	7		T130	1		T150	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T127	2		T121	1		T144	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	1		T212	10		T19	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	2		T123	13		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T45	1		T47	1		T120	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	9		T48	1		T30	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	11		T45	18		T212	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T3	3		T10	13		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T120	7		T145	1		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	4		T10	5		T144	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T29	1		T129	13		T125	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T9	3		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T129	11		T39	4		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T6	1		T14	7		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T48	12		T128	12		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16941	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T244	8		T320	1		T196	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T29	10		T122	11		T133	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T17	10		T122	5		T125	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T124	16		T84	2		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	4		T10	9		T219	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T39	3		T190	2		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T150	8		T223	1		T313	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T181	2		T119	8		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	1		T222	1		T242	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T12	1		T219	10		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T45	1		T120	3		T133	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	6		T48	8		T124	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	9		T45	15		T41	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T10	13		T45	12		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T120	7		T145	15		T183	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	8		T10	2		T144	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T29	9		T129	8		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	7		T9	2		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T129	10		T39	10		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T6	2		T14	5		T305	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T48	11		T128	11		T272	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T320	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T145	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T318	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T311	1		T321	15		T322	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T127	15		T147	10		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T47	3		T145	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T17	10		T30	14		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T18	1		T124	12		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T7	1		T47	1		T122	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T123	13		T130	1		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T10	9		T46	7		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T127	2		T144	15		T119	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T212	10		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T121	1		T181	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	1		T133	1		T214	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	11		T48	1		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	11		T45	19		T120	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	13		T45	9		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T120	7		T152	1		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T9	4		T10	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T145	1		T129	13		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T3	3		T6	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T48	12		T128	12		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T145	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T318	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T311	2		T321	1		T322	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T147	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T29	10		T122	11		T150	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	10		T125	2		T79	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T124	16		T133	7		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	4		T122	5		T219	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T39	3		T190	2		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	9		T223	1		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T119	8		T259	5		T272	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	1		T150	8		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T181	2		T219	10		T84	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T133	3		T134	5		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	7		T48	8		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	9		T45	16		T120	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	13		T45	12		T48	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T120	7		T183	16		T200	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	7		T9	8		T10	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T145	15		T129	8		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T6	2		T9	2		T14	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T48	11		T128	11		T29	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T47	1		T145	1		T29	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T127	1		T17	15		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T123	1		T18	1		T124	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T7	5		T10	10		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T130	1		T39	5		T190	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T46	1		T130	1		T150	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T127	1		T121	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	1		T212	1		T19	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	2		T123	1		T219	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T45	2		T47	1		T120	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	9		T48	9		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	10		T45	16		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T3	3		T10	14		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	8		T145	16		T183	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	9		T10	3		T144	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T29	10		T129	9		T125	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	8		T9	3		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T129	11		T39	14		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T6	3		T14	10		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T48	12		T128	12		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17071	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T244	1		T320	12		T196	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	2		T122	11		T150	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T127	14		T17	5		T30	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T123	12		T124	11		T84	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	8		T135	12		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T190	9		T223	12		T146	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T46	6		T150	9		T168	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T127	1		T144	14		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T212	9		T214	16		T158	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T123	12		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T120	6		T214	13		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	6		T30	10		T124	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	10		T45	17		T212	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T10	12		T44	25		T45	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T120	6		T252	11		T200	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	3		T10	4		T144	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	12		T125	4		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	2		T119	2		T213	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T129	10		T150	7		T137	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T14	2		T46	12		T323	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T48	11		T128	11		T238	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T289	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T244	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T145	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T318	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T311	3		T321	2		T322	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T127	1		T147	8		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T47	1		T145	1		T29	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	15		T30	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T18	1		T124	17		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	5		T47	1		T122	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T123	1		T130	1		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	10		T46	1		T223	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T127	1		T144	1		T119	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	1		T212	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T121	1		T181	3		T219	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	1		T133	4		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	11		T48	9		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	10		T45	18		T120	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	14		T45	13		T48	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	8		T152	1		T183	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	8		T9	9		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T145	16		T129	9		T39	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T3	3		T6	3		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T48	12		T128	12		T29	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T318	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T321	14		T322	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T127	14		T147	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	2		T122	11		T150	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T17	5		T30	13		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T124	11		T228	8		T170	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T122	13		T132	14		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T123	12		T190	9		T84	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	8		T46	6		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T127	1		T144	14		T119	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T212	9		T214	16		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T236	6		T84	2		T259	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T214	13		T236	7		T158	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	7		T123	12		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	10		T45	17		T120	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	12		T45	8		T30	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T120	6		T252	11		T200	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	3		T10	4		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T129	12		T184	8		T228	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T9	2		T14	2		T44	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T48	11		T128	11		T129	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10