Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22425

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3762

1

T6

4

T7

5

T10

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20357

1

T1

164

T2

20

T4

12

auto[1]

5830

1

T3

3

T6

8

T9

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T40	6		T239	18		T299	3
values[0]	130	1			T6	3		T9	5		T17	20
values[1]	763	1			T7	5		T46	7		T127	15
values[2]	805	1			T47	1		T145	1		T30	14
values[3]	551	1			T10	26		T120	10		T144	20
values[4]	798	1			T6	8		T9	12		T45	33
values[5]	625	1			T14	12		T145	11		T212	3
values[6]	830	1			T12	15		T45	21		T46	13
values[7]	613	1			T6	1		T11	20		T120	14
values[8]	2880	1			T3	3		T10	18		T13	3
values[9]	1118	1			T10	7		T12	3		T47	1
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1008	1			T6	3		T7	5		T9	5
values[1]	688	1			T145	1		T30	14		T130	1
values[2]	766	1			T6	8		T10	26		T45	33
values[3]	709	1			T9	12		T128	23		T212	3
values[4]	759	1			T12	15		T14	12		T46	13
values[5]	702	1			T45	21		T48	23		T120	14
values[6]	2737	1			T3	3		T6	1		T13	3
values[7]	817	1			T10	18		T11	20		T48	4
values[8]	725	1			T10	7		T12	3		T47	1
values[9]	219	1			T29	10		T119	17		T39	14
minimum	17057	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T9	3		T47	1		T127	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	1		T7	1		T46	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T145	1		T130	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	14		T124	12		T125	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	1		T45	18		T120	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	13		T127	2		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	4		T128	12		T30	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T212	3		T219	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	7		T47	3		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	9		T46	13		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T45	9		T48	12		T120	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	1		T150	8		T244	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T3	3		T13	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T122	12		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	11		T48	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T10	9		T129	11		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	5		T47	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	2		T144	15		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T272	2		T229	1		T292	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T29	1		T119	3		T39	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T274	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	2		T39	1		T133	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	2		T7	4		T145	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T222	1		T220	1		T247	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T124	16		T125	3		T20	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	7		T45	15		T120	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	13		T219	13		T132	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	8		T128	11		T122	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T219	10		T133	11		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	5		T29	10		T143	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	6		T144	7		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T45	12		T48	11		T120	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T150	9		T238	9		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T45	1		T140	10		T232	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T122	11		T223	9		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	9		T48	3		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	9		T129	10		T142	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	2		T48	8		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	1		T181	2		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T272	5		T239	5		T21	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T29	9		T119	14		T39	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T274	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T239	13		T299	2		T324	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T40	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T9	3		T325	1		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T6	1		T17	10		T248	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T127	15		T212	10		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	1		T46	7		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T47	1		T145	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	14		T125	5		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T120	7		T144	10		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	13		T20	5		T231	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T9	4		T45	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	2		T131	1		T219	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	7		T122	14		T123	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T145	1		T212	3		T41	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T45	9		T47	3		T48	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	9		T46	13		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	11		T120	7		T119	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T122	12		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T3	3		T13	3		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	9		T129	11		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T10	5		T47	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T12	2		T144	15		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T239	5		T299	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T40	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T9	2		T227	1		T326	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T6	2		T17	10		T248	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T133	7		T150	8		T146	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	4		T145	15		T122	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T39	1		T213	15		T222	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T125	3		T79	11		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	3		T144	10		T124	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T10	13		T20	5		T231	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	7		T9	8		T45	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T219	23		T133	11		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T14	5		T122	5		T143	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T145	10		T41	4		T84	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T45	12		T48	11		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	6		T144	7		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	9		T120	7		T119	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T122	11		T184	8		T223	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T45	1		T48	3		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	9		T129	10		T19	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	2		T48	8		T151	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T12	1		T181	2		T29	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	3		T47	1		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	3		T7	5		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T145	1		T130	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	1		T124	17		T125	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	8		T45	16		T120	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	14		T127	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	9		T128	12		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T212	1		T219	11		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	10		T47	1		T29	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	9		T46	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	13		T48	12		T120	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T130	1		T150	10		T244	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T3	3		T13	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T122	12		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	10		T48	4		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T10	10		T129	11		T142	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	3		T47	1		T48	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	2		T144	1		T181	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T272	6		T229	1		T292	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T29	10		T119	15		T39	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T274	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	2		T127	14		T212	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	6		T17	5		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T220	1		T247	14		T234	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T30	13		T124	11		T125	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T45	17		T120	6		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	12		T127	1		T132	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	3		T128	11		T30	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T212	2		T158	16		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T47	2		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	6		T46	12		T144	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T45	8		T48	11		T120	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T150	7		T244	15		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T44	25		T119	2		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T122	11		T223	12		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	10		T123	24		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	8		T129	10		T184	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	4		T158	2		T258	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T144	14		T40	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T272	1		T292	12		T239	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T119	2		T210	11		T211	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T274	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T239	6		T299	3		T324	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T40	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T9	3		T325	1		T227	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T6	3		T17	15		T248	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T127	1		T212	1		T133	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	5		T46	1		T145	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T47	1		T145	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	1		T125	4		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T120	4		T144	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T10	14		T20	7		T231	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	8		T9	9		T45	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T127	1		T131	1		T219	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	10		T122	6		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	11		T212	1		T41	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	13		T47	1		T48	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	9		T46	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	10		T120	8		T119	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T122	12		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T3	3		T13	3		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	10		T129	11		T19	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	3		T47	1		T48	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	397	1			T12	2		T144	1		T181	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T239	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T40	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T9	2		T255	10		T322	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T17	5		T248	8		T274	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T127	14		T212	9		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T46	6		T122	11		T124	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T39	1		T213	9		T247	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T30	13		T125	4		T79	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T120	6		T144	9		T124	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T10	12		T20	3		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	3		T45	17		T128	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T127	1		T132	14		T158	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	2		T122	13		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T212	2		T41	2		T84	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T45	8		T47	2		T48	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	6		T46	12		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	10		T120	6		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T122	11		T184	8		T223	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T44	25		T123	12		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	8		T129	10		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	4		T123	12		T158	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T12	1		T144	14		T119	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10