Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22070

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

4117

1

T6

1

T7

5

T10

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20296

1

T1

164

T2

20

T4

12

auto[1]

5891

1

T3

3

T6

9

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	317	1			T327	1		T272	21		T257	9
values[0]	49	1			T127	15		T147	17		T319	1
values[1]	736	1			T47	3		T145	1		T17	20
values[2]	848	1			T7	5		T47	1		T122	19
values[3]	772	1			T10	18		T46	7		T123	13
values[4]	724	1			T6	1		T127	2		T144	15
values[5]	567	1			T47	1		T121	1		T181	3
values[6]	662	1			T11	20		T12	18		T45	35
values[7]	617	1			T10	26		T45	21		T48	4
values[8]	779	1			T6	8		T9	12		T10	7
values[9]	3070	1			T3	3		T6	3		T9	5
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	758	1			T47	3		T17	20		T30	14
values[1]	872	1			T7	5		T47	1		T123	13
values[2]	689	1			T10	18		T46	7		T130	2
values[3]	624	1			T6	1		T127	2		T121	1
values[4]	699	1			T12	3		T45	35		T47	1
values[5]	570	1			T11	20		T12	15		T48	9
values[6]	2809	1			T3	3		T10	26		T13	3
values[7]	803	1			T9	12		T10	7		T144	38
values[8]	865	1			T6	8		T9	5		T14	12
values[9]	185	1			T6	3		T48	23		T128	23
minimum	17313	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T47	3		T133	1		T150	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T17	10		T30	14		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T123	13		T124	12		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	1		T47	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T130	1		T39	2		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T10	9		T46	7		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T127	2		T121	1		T119	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T144	15		T212	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	2		T47	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T45	19		T120	7		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	11		T12	9		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T212	3		T35	1		T41	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T3	3		T10	13		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T120	7		T145	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	4		T10	5		T144	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T29	1		T129	13		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	1		T9	3		T46	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T14	7		T145	1		T129	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T6	1		T328	3		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T48	12		T128	12		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16953	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T127	15		T125	3		T147	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T133	7		T150	2		T147	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	10		T122	16		T132	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T124	16		T136	12		T227	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	4		T219	2		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T39	3		T84	2		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	9		T150	8		T223	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T119	8		T190	2		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	1		T133	3		T222	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T12	1		T181	2		T219	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T45	16		T120	3		T134	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	9		T12	6		T48	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T41	4		T257	2		T207	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T10	13		T45	12		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T120	7		T145	15		T146	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	8		T10	2		T144	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T29	9		T129	8		T39	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	7		T9	2		T119	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	5		T145	10		T129	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T6	2		T328	2		T305	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T48	11		T128	11		T272	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T125	2		T147	7		T247	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T327	1		T328	3		T294	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T272	10		T257	7		T234	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T321	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T127	15		T147	10		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T47	3		T145	1		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	10		T30	14		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T124	12		T182	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T7	1		T47	1		T122	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T123	13		T130	1		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T10	9		T46	7		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T127	2		T119	3		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	1		T144	15		T212	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	1		T121	1		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T19	1		T214	14		T236	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	11		T12	11		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	19		T120	7		T212	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	13		T45	9		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T120	7		T146	12		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	1		T9	4		T10	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T145	1		T129	13		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T3	3		T6	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T14	7		T48	12		T128	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T328	2		T316	12		T329	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T272	11		T257	2		T234	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T321	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T147	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	10		T150	2		T147	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	10		T122	11		T125	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T124	16		T133	7		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	4		T122	5		T219	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T39	3		T84	2		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	9		T223	1		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T119	8		T190	2		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	1		T133	3		T150	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T181	2		T219	10		T259	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T134	5		T143	10		T275	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	9		T12	7		T48	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	16		T120	3		T41	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	13		T45	12		T48	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T120	7		T146	13		T183	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	7		T9	8		T10	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T145	15		T129	8		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T6	2		T9	2		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	5		T48	11		T128	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T47	1		T133	8		T150	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T17	15		T30	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T123	1		T124	17		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	5		T47	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T130	1		T39	5		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	10		T46	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T127	1		T121	1		T119	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	1		T144	1		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	2		T47	1		T181	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T45	18		T120	4		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	10		T12	9		T48	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T212	1		T35	1		T41	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T3	3		T10	14		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T120	8		T145	16		T146	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	9		T10	3		T144	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T29	10		T129	9		T39	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	8		T9	3		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T14	10		T145	11		T129	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T6	3		T328	4		T305	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T48	12		T128	12		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17108	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T127	1		T125	3		T147	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T47	2		T150	4		T147	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	5		T30	13		T122	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T123	12		T124	11		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T135	12		T136	10		T220	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T84	1		T223	12		T267	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T10	8		T46	6		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T127	1		T119	2		T190	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T144	14		T212	9		T214	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T40	2		T236	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	17		T120	6		T214	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	10		T12	6		T30	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T212	2		T41	2		T257	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T10	12		T44	25		T45	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T120	6		T146	11		T200	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	3		T10	4		T144	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	12		T125	4		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	2		T46	12		T119	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	2		T129	10		T150	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T328	1		T323	12		T330	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T48	11		T128	11		T272	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T244	7		T321	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T127	14		T125	2		T147	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T327	1		T328	4		T294	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T272	12		T257	3		T234	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T321	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T127	1		T147	8		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	1		T145	1		T29	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T17	15		T30	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T124	17		T182	1		T133	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	5		T47	1		T122	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T123	1		T130	1		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T10	10		T46	1		T223	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T127	1		T119	9		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	1		T144	1		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T47	1		T121	1		T181	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	1		T214	1		T236	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	10		T12	11		T48	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T45	18		T120	4		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	14		T45	13		T48	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T120	8		T146	14		T183	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	8		T9	9		T10	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T145	16		T129	9		T39	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T3	3		T6	3		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T14	10		T48	12		T128	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T328	1		T316	10		T323	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T272	9		T257	6		T234	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T321	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T127	14		T147	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	2		T150	4		T147	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T17	5		T30	13		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T124	11		T228	8		T170	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T122	13		T132	14		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T123	12		T84	1		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T10	8		T46	6		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T127	1		T119	2		T190	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T144	14		T212	9		T214	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T236	6		T259	9		T171	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T214	13		T236	7		T158	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	10		T12	7		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T45	17		T120	6		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	12		T45	8		T30	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T120	6		T146	11		T200	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	3		T10	4		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T129	12		T125	4		T184	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T9	2		T44	25		T46	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	2		T48	11		T128	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10