Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22881

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3306

1

T7

5

T9

5

T11

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20027

1

T1

164

T2

20

T4

12

auto[1]

6160

1

T3

3

T6

3

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T46	13		T125	8		T19	2
values[0]	64	1			T132	1		T168	5		T171	10
values[1]	751	1			T7	5		T12	15		T46	7
values[2]	666	1			T45	33		T47	1		T144	35
values[3]	839	1			T6	3		T11	20		T12	3
values[4]	643	1			T6	8		T10	7		T181	3
values[5]	2966	1			T3	3		T13	3		T38	2
values[6]	611	1			T9	17		T14	12		T47	3
values[7]	764	1			T6	1		T120	10		T35	1
values[8]	526	1			T10	44		T45	2		T29	11
values[9]	1040	1			T47	1		T48	9		T145	11
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	740	1			T7	5		T46	7		T127	2
values[1]	716	1			T45	33		T47	1		T144	53
values[2]	858	1			T6	3		T11	20		T12	3
values[3]	2870	1			T3	3		T6	8		T10	7
values[4]	635	1			T9	12		T48	4		T150	7
values[5]	737	1			T9	5		T14	12		T47	3
values[6]	661	1			T6	1		T30	14		T130	1
values[7]	640	1			T10	44		T45	2		T48	9
values[8]	934	1			T46	13		T47	1		T145	11
values[9]	111	1			T142	4		T125	8		T150	17
minimum	17285	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T127	2		T219	1		T223	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	1		T46	7		T212	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T47	1		T144	10		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T45	18		T144	26		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T12	2		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	11		T120	7		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T3	3		T6	1		T10	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T45	9		T47	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	4		T150	5		T184	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	1		T168	4		T147	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T14	7		T120	7		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	3		T47	3		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	1		T30	14		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T124	4		T19	1		T214	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	22		T45	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T124	12		T182	1		T236	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T46	13		T145	1		T17	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T47	1		T212	10		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T125	5		T150	8		T272	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T142	1		T331	1		T332	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17025	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T132	1		T217	1		T333	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T219	13		T223	9		T231	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	4		T259	4		T248	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T144	10		T134	5		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	15		T144	7		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	2		T12	1		T48	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	9		T120	7		T145	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T6	7		T10	2		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T45	12		T181	2		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	8		T150	2		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T48	3		T147	7		T183	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	5		T120	3		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	2		T133	11		T213	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	1		T133	7		T41	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T124	2		T257	2		T154	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	22		T45	1		T48	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T124	16		T20	5		T183	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T145	10		T17	10		T122	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	9		T129	8		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T125	3		T150	9		T272	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T142	3		T332	13		T334	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	3		T12	8		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T217	1		T333	7		T310	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T46	13		T125	5		T19	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T37	1		T148	4		T335	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T168	5		T171	10		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T132	1		T95	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	9		T127	2		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	1		T46	7		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T47	1		T144	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	18		T144	15		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T12	2		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	11		T120	7		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T10	5		T30	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T181	1		T129	11		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	9		T47	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	4		T14	7		T39	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	3		T47	3		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T6	1		T120	7		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T124	4		T133	1		T214	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	22		T45	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	12		T19	1		T20	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T48	1		T145	1		T17	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T47	1		T212	10		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T125	3		T19	1		T150	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T148	6		T336	8		T337	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T250	5		T260	9		T262	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T95	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	6		T122	3		T84	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	4		T144	7		T259	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T144	10		T219	13		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	15		T122	11		T234	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	2		T12	1		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	9		T120	7		T145	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	7		T10	2		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T181	2		T129	10		T119	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T128	11		T140	10		T232	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T45	12		T48	3		T143	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	8		T14	5		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	2		T213	15		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T120	3		T40	1		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T124	2		T133	11		T222	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	22		T45	1		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T124	16		T20	5		T228	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T48	8		T145	10		T17	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	9		T129	8		T39	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T127	1		T219	14		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	5		T46	1		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	1		T144	11		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	16		T144	9		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	3		T12	2		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T11	10		T120	8		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T3	3		T6	8		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T45	13		T47	1		T181	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	9		T150	3		T184	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T48	4		T168	1		T147	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	10		T120	4		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	3		T47	1		T133	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	1		T30	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T124	3		T19	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	24		T45	2		T48	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T124	17		T182	1		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T46	1		T145	11		T17	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T47	1		T212	1		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T125	4		T150	10		T272	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T142	4		T331	1		T332	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17107	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T132	1		T217	2		T333	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T127	1		T223	12		T231	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	6		T212	2		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T144	9		T231	2		T37	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	17		T144	24		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T48	11		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	10		T120	6		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T10	4		T44	25		T127	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T45	8		T129	10		T267	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	3		T150	4		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T168	3		T147	9		T252	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	2		T120	6		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T9	2		T47	2		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T30	13		T40	2		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T124	3		T214	16		T244	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T10	20		T84	1		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T124	11		T236	13		T20	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T46	12		T17	5		T122	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T212	9		T129	12		T168	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T125	4		T150	7		T272	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T332	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	6		T122	11		T123	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T333	9		T310	13		T338	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T46	1		T125	4		T19	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T37	1		T148	7		T335	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T168	1		T171	1		T250	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T132	1		T95	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	9		T127	1		T122	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	5		T46	1		T144	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	1		T144	11		T219	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T45	16		T144	1		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	3		T12	2		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	10		T120	8		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	8		T10	3		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T181	3		T129	11		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T45	13		T47	1		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	9		T14	10		T39	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	3		T47	1		T213	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	1		T120	4		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T124	3		T133	12		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	24		T45	2		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	17		T19	1		T20	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T48	9		T145	11		T17	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T47	1		T212	1		T29	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T46	12		T125	4		T214	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T148	3		T336	9		T90	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T168	4		T171	9		T260	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T95	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	6		T127	1		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T46	6		T144	10		T212	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T144	9		T169	12		T37	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	17		T144	14		T122	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	1		T48	11		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	10		T120	6		T190	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	4		T30	10		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T129	10		T119	2		T221	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T44	25		T127	14		T128	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T45	8		T168	3		T252	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	3		T14	2		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T9	2		T47	2		T213	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T120	6		T40	2		T236	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T124	3		T214	16		T244	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T10	20		T30	13		T164	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T124	11		T20	3		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T17	5		T122	13		T84	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T212	9		T129	12		T236	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10