Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22332

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3855

1

T6

4

T9

17

T10

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20255

1

T1

164

T2

20

T4

12

auto[1]

5932

1

T3

3

T6

3

T9

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T9	12		T145	16		T35	1
values[0]	67	1			T151	12		T327	1		T252	14
values[1]	686	1			T7	5		T47	3		T48	9
values[2]	688	1			T6	4		T10	18		T46	13
values[3]	708	1			T9	5		T10	7		T12	3
values[4]	3020	1			T3	3		T10	26		T12	15
values[5]	682	1			T11	20		T45	33		T46	7
values[6]	678	1			T48	27		T128	23		T144	15
values[7]	680	1			T6	8		T127	2		T212	3
values[8]	790	1			T120	14		T144	20		T29	11
values[9]	915	1			T14	12		T45	2		T47	1
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	771	1			T7	5		T47	3		T48	9
values[1]	627	1			T6	4		T10	18		T46	13
values[2]	858	1			T9	5		T10	7		T12	3
values[3]	2913	1			T3	3		T10	26		T12	15
values[4]	673	1			T11	20		T45	33		T46	7
values[5]	590	1			T6	8		T48	27		T144	15
values[6]	843	1			T127	2		T144	20		T212	3
values[7]	690	1			T120	10		T29	11		T119	17
values[8]	757	1			T9	12		T14	12		T45	2
values[9]	240	1			T145	16		T212	10		T131	1
minimum	17225	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T7	1		T47	3		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T145	1		T182	1		T84	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	9		T145	1		T124	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	2		T46	13		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	5		T12	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T9	3		T45	9		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	13		T12	9		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	7		T128	12		T123	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	11		T45	18		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	1		T48	1		T122	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	12		T144	15		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T127	2		T122	12		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T144	10		T212	3		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T120	7		T29	1		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T119	3		T219	1		T132	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T45	1		T47	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	4		T14	7		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T145	1		T131	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T212	10		T125	5		T222	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16957	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T150	5		T151	1		T327	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	4		T48	8		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T145	10		T84	2		T223	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T10	9		T124	16		T133	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	2		T17	10		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	2		T12	1		T124	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	2		T45	12		T246	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T140	10		T232	14		T264	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	13		T12	6		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T128	11		T40	1		T213	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	9		T45	15		T119	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	7		T48	3		T122	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T48	11		T129	8		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T122	3		T223	1		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T144	10		T129	10		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T120	3		T29	10		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T119	14		T219	10		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T45	1		T29	9		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	8		T14	5		T120	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T145	15		T228	9		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T125	3		T222	11		T235	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T150	2		T151	11		T295	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T145	1		T35	1		T152	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T9	4		T222	15		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T252	14		T271	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T151	1		T327	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T7	1		T47	3		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T182	1		T150	5		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T10	9		T124	12		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T6	2		T46	13		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	5		T12	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	3		T35	1		T123	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T3	3		T13	3		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T10	13		T12	9		T45	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T46	7		T181	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	11		T45	18		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	1		T128	12		T122	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T48	12		T144	15		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T127	2		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T212	3		T129	11		T236	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T29	1		T39	3		T214	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T120	7		T144	10		T119	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T45	1		T47	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T14	7		T212	10		T30	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T145	15		T216	7		T250	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T9	8		T222	11		T268	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T271	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T151	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	4		T48	8		T144	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	2		T84	2		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T10	9		T124	16		T164	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	2		T145	10		T17	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	2		T12	1		T124	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	2		T136	10		T234	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T140	10		T232	14		T264	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	13		T12	6		T45	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T181	2		T219	2		T213	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	9		T45	15		T119	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T48	3		T128	11		T122	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T48	11		T129	8		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	7		T122	3		T223	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T129	10		T313	10		T221	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T29	10		T39	1		T143	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T120	7		T144	10		T119	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	1		T120	3		T29	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	5		T125	3		T219	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	5		T47	1		T48	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T145	11		T182	1		T84	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	10		T145	1		T124	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	4		T46	1		T17	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	3		T12	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	3		T45	13		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	14		T12	9		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T46	1		T128	12		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	10		T45	16		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	8		T48	4		T122	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	12		T144	1		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T127	1		T122	4		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T144	11		T212	1		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T120	4		T29	11		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T119	15		T219	11		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T45	2		T47	1		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	9		T14	10		T120	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T145	16		T131	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T212	1		T125	4		T222	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17089	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T150	3		T151	12		T327	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T47	2		T144	10		T125	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T84	2		T223	12		T168	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	8		T124	11		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T46	12		T17	5		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	4		T12	1		T124	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	2		T45	8		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T44	25		T127	14		T190	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	12		T12	6		T238	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T46	6		T128	11		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	10		T45	17		T119	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T122	13		T147	14		T289	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	11		T144	14		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	1		T122	11		T158	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	9		T212	2		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T120	6		T39	1		T214	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T119	2		T132	14		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	13		T257	6		T171	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	3		T14	2		T120	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T228	2		T216	8		T155	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T212	9		T125	4		T222	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T252	13		T271	6		T262	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T150	4		T295	7		T240	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T145	16		T35	1		T152	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T9	9		T222	12		T268	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T252	1		T271	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T151	12		T327	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	5		T47	1		T48	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T182	1		T150	3		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	10		T124	17		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	4		T46	1		T145	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	3		T12	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	3		T35	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T3	3		T13	3		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	14		T12	9		T45	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T46	1		T181	3		T219	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	10		T45	16		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	4		T128	12		T122	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T48	12		T144	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	8		T127	1		T122	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T212	1		T129	11		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	11		T39	3		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T120	8		T144	11		T119	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T45	2		T47	1		T120	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T14	10		T212	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T171	17		T255	15		T216	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T9	3		T222	14		T170	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T252	13		T271	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T270	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T47	2		T144	10		T125	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T150	4		T84	2		T223	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	8		T124	11		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	12		T17	5		T122	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	4		T12	1		T124	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	2		T123	2		T236	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T44	25		T127	14		T190	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	12		T12	6		T45	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T46	6		T213	9		T20	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	10		T45	17		T119	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T128	11		T122	13		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	11		T144	14		T123	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T127	1		T122	11		T158	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T212	2		T129	10		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	1		T214	13		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T120	6		T144	9		T119	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T120	6		T30	13		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	2		T212	9		T30	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10