Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T45	13		T47	1		T120	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T123	1		T190	3		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	2		T46	1		T48	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	1		T130	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	1		T214	1		T222	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	12		T17	15		T29	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T40	4		T236	1		T150	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T144	8		T143	15		T242	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T145	16		T243	1		T238	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	9		T127	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	10		T123	1		T119	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	3		T144	11		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T144	1		T29	11		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	5		T9	3		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	14		T119	15		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T45	18		T46	1		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T6	3		T10	10		T12	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T181	3		T122	4		T133	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T9	9		T30	1		T204	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17068	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T244	1		T200	4		T245	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T45	8		T120	6		T147	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T123	12		T190	9		T150	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T46	12		T120	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T214	13		T246	9		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T47	2		T214	16		T168	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	11		T17	5		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T44	25		T128	11		T122	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	2		T236	6		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T144	10		T252	12		T253	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T238	9		T249	2		T254	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T127	1		T213	9		T79	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	2		T123	12		T119	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	4		T144	9		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	14		T125	4		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	2		T127	14		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	12		T119	2		T231	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T45	17		T46	6		T122	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T10	8		T12	6		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T122	11		T228	2		T153	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T9	3		T30	13		T204	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T11	10		T39	1		T255	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T244	7		T200	1		T216	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T133	4		T221	17		T153	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T9	9		T30	1		T142	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T219	3		T240	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	10		T45	13		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T123	1		T190	3		T150	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	2		T46	1		T120	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T131	1		T182	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T47	1		T48	9		T132	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T47	1		T48	12		T17	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T128	12		T19	2		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T219	11		T40	4		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	16		T134	6		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	8		T121	1		T213	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	10		T123	1		T119	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	1		T127	1		T144	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T35	1		T125	4		T133	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	5		T10	3		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T10	14		T144	1		T29	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T9	3		T45	18		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	3		T10	10		T12	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T221	20		T153	2		T256	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T9	3		T30	13		T228	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	10		T45	8		T120	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T123	12		T190	9		T150	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T46	12		T120	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T214	13		T84	2		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	2		T132	14		T214	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	11		T17	5		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T128	11		T135	12		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	2		T236	6		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T44	25		T144	10		T122	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T169	9		T238	9		T240	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T213	9		T79	10		T257	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	2		T123	12		T119	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T127	1		T144	9		T136	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T125	4		T158	2		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	4		T127	14		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	12		T144	14		T119	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	2		T45	17		T46	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T10	8		T12	6		T129	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10