Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22867

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3320

1

T7

5

T9

5

T11

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20048

1

T1

164

T2

20

T4

12

auto[1]

6139

1

T3

3

T6

3

T9

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T19	2		T258	18		-	-
values[0]	54	1			T132	1		T259	9		T260	19
values[1]	714	1			T7	5		T12	15		T46	7
values[2]	762	1			T45	33		T47	1		T144	38
values[3]	843	1			T6	3		T11	20		T12	3
values[4]	688	1			T6	8		T10	7		T128	23
values[5]	2831	1			T3	3		T13	3		T38	2
values[6]	656	1			T9	17		T14	12		T47	3
values[7]	781	1			T6	1		T10	18		T120	10
values[8]	457	1			T10	26		T45	2		T212	10
values[9]	1335	1			T46	13		T47	1		T48	9
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	944	1			T7	5		T12	15		T46	7
values[1]	733	1			T11	20		T45	33		T47	1
values[2]	845	1			T6	3		T12	3		T48	23
values[3]	2865	1			T3	3		T6	8		T10	7
values[4]	669	1			T9	17		T48	4		T150	7
values[5]	676	1			T14	12		T47	3		T120	10
values[6]	710	1			T6	1		T30	14		T130	1
values[7]	609	1			T10	18		T45	2		T48	9
values[8]	832	1			T10	26		T46	13		T47	1
values[9]	227	1			T145	11		T142	4		T125	8
minimum	17077	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T12	9		T127	2		T122	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	1		T46	7		T212	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T47	1		T39	2		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T11	11		T45	18		T144	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	1		T12	2		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T120	7		T121	1		T145	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T3	3		T6	1		T10	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T45	9		T47	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T9	4		T150	5		T184	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	3		T48	1		T168	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T14	7		T120	7		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T47	3		T133	1		T213	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T30	14		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T124	4		T19	1		T214	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	9		T45	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T124	12		T236	14		T20	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T10	13		T46	13		T17	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	1		T212	10		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T145	1		T125	5		T150	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T142	1		T146	6		T244	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16931	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T261	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	6		T122	3		T219	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	4		T259	4		T217	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	3		T134	5		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	9		T45	15		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	2		T12	1		T48	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T120	7		T145	15		T119	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T6	7		T10	2		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T45	12		T181	2		T129	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	8		T150	2		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T9	2		T48	3		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	5		T120	3		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T133	11		T213	15		T143	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T40	1		T133	7		T41	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T124	2		T257	2		T154	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	9		T45	1		T48	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T124	16		T20	5		T183	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	13		T17	10		T122	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	9		T129	8		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T145	10		T125	3		T150	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T142	3		T146	3		T257	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T261	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T19	1		T258	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T260	10		T262	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T132	1		T259	5		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	9		T127	2		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T46	7		T212	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T47	1		T144	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T45	18		T144	11		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	1		T12	2		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	11		T120	7		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	1		T10	5		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T181	1		T129	11		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	9		T47	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	4		T14	7		T39	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	3		T47	3		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	1		T10	9		T120	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T124	4		T133	1		T214	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	13		T45	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T212	10		T19	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T46	13		T48	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T47	1		T29	1		T129	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T19	1		T258	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T260	9		T262	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	4		T95	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	6		T122	3		T84	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	4		T217	1		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T144	10		T219	13		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T45	15		T144	7		T122	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	2		T12	1		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	9		T120	7		T145	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	7		T10	2		T128	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T181	2		T129	10		T119	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T140	10		T232	14		T264	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T45	12		T48	3		T143	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	8		T14	5		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	2		T213	15		T143	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	9		T120	3		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T124	2		T133	11		T257	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	13		T45	1		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T20	5		T228	9		T265	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T48	8		T145	10		T17	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T29	9		T129	8		T124	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	9		T127	1		T122	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	5		T46	1		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T47	1		T39	5		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	10		T45	16		T144	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	3		T12	2		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T120	8		T121	1		T145	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T3	3		T6	8		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	13		T47	1		T181	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	9		T150	3		T184	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	3		T48	4		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	10		T120	4		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	1		T133	12		T213	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	1		T30	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T124	3		T19	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	10		T45	2		T48	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T124	17		T236	1		T20	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	14		T46	1		T17	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T47	1		T212	1		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T145	11		T125	4		T150	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T142	4		T146	4		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17063	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	6		T127	1		T122	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	6		T212	2		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T231	2		T37	7		T266	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	10		T45	17		T144	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T48	11		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T120	6		T119	2		T190	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T10	4		T44	25		T127	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T45	8		T129	10		T267	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	3		T150	4		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	2		T168	3		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	2		T120	6		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T47	2		T213	9		T238	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	13		T40	2		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T124	3		T214	16		T244	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T10	8		T84	1		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T124	11		T236	13		T20	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T10	12		T46	12		T17	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T212	9		T129	12		T168	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T125	4		T150	7		T222	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T146	5		T244	8		T257	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T168	4		T262	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T19	2		T258	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T260	10		T262	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T132	1		T259	5		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	9		T127	1		T122	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	5		T46	1		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	1		T144	11		T219	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T45	16		T144	8		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	3		T12	2		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	10		T120	8		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	8		T10	3		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T181	3		T129	11		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T3	3		T13	3		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T45	13		T47	1		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	9		T14	10		T39	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	3		T47	1		T213	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	1		T10	10		T120	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T124	3		T133	12		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	14		T45	2		T29	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T212	1		T19	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T46	1		T48	9		T145	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T47	1		T29	10		T129	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T258	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T260	9		T262	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T259	4		T95	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	6		T127	1		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	6		T212	2		T171	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T144	9		T169	12		T37	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	17		T144	10		T122	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T48	11		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	10		T120	6		T144	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	4		T128	11		T30	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T129	10		T119	2		T252	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T44	25		T127	14		T119	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T45	8		T168	3		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	3		T14	2		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T9	2		T47	2		T213	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	8		T120	6		T40	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	3		T214	16		T244	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T10	12		T30	13		T164	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T212	9		T20	3		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T46	12		T17	5		T122	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T129	12		T124	11		T236	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10