Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22328

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3859

1

T6

4

T9

17

T10

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20237

1

T1

164

T2

20

T4

12

auto[1]

5950

1

T3

3

T6

3

T9

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T35	1		T268	7		-	-
values[0]	110	1			T151	12		T252	14		T229	1
values[1]	648	1			T7	5		T10	18		T47	3
values[2]	672	1			T6	4		T145	11		T17	20
values[3]	701	1			T9	5		T10	7		T12	3
values[4]	3045	1			T3	3		T12	15		T13	3
values[5]	681	1			T10	26		T45	33		T46	7
values[6]	694	1			T11	20		T48	4		T128	23
values[7]	684	1			T6	8		T48	23		T127	2
values[8]	768	1			T120	14		T144	20		T29	11
values[9]	1130	1			T9	12		T14	12		T45	2
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	901	1			T6	1		T7	5		T47	3
values[1]	608	1			T6	3		T10	18		T46	13
values[2]	869	1			T9	5		T10	7		T12	3
values[3]	2927	1			T3	3		T10	26		T12	15
values[4]	713	1			T11	20		T45	33		T46	7
values[5]	546	1			T6	8		T48	23		T144	15
values[6]	831	1			T127	2		T144	20		T212	3
values[7]	647	1			T120	10		T29	11		T119	17
values[8]	853	1			T9	12		T14	12		T45	2
values[9]	206	1			T145	16		T212	10		T131	1
minimum	17086	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	1		T47	3		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T6	1		T145	1		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	9		T145	1		T124	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	1		T46	13		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	5		T12	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T9	3		T45	9		T123	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	13		T12	9		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T46	7		T48	1		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	11		T45	18		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	1		T122	14		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	12		T144	15		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T127	2		T122	12		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T144	10		T212	3		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T120	7		T29	1		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T119	3		T219	1		T150	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T45	1		T47	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T9	4		T14	7		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T145	1		T131	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T212	10		T125	5		T222	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T269	11		T270	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	4		T48	8		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T145	10		T150	2		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	9		T124	16		T133	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	2		T17	10		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	2		T12	1		T124	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	2		T45	12		T246	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T140	10		T232	14		T264	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	13		T12	6		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	3		T128	11		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	9		T45	15		T119	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T6	7		T122	5		T147	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	11		T129	8		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T122	3		T223	1		T136	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	10		T129	10		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T120	3		T29	10		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T119	14		T219	10		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	1		T29	9		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	8		T14	5		T120	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T145	15		T228	9		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T125	3		T222	11		T272	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T269	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T35	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T268	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T252	14		T271	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T151	1		T229	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T7	1		T10	9		T47	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T182	1		T150	5		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T124	12		T215	1		T164	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	2		T145	1		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T10	5		T12	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	3		T46	13		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T3	3		T13	3		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	9		T45	9		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T46	7		T181	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	13		T45	18		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	1		T128	12		T122	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	11		T129	13		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T127	2		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	12		T144	15		T212	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T29	1		T39	3		T214	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T120	7		T144	10		T119	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T45	1		T47	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T9	4		T14	7		T212	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T268	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T271	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T151	11		T274	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	4		T10	9		T48	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T150	2		T84	2		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T124	16		T164	3		T217	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	2		T145	10		T17	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	2		T12	1		T124	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T9	2		T136	10		T275	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T140	10		T232	14		T264	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	6		T45	12		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T181	2		T219	2		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	13		T45	15		T119	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	3		T128	11		T122	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	9		T129	8		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	7		T122	3		T220	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	11		T129	10		T84	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	10		T39	1		T143	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T120	7		T144	10		T119	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T45	1		T120	3		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	8		T14	5		T125	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	5		T47	1		T48	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T6	1		T145	11		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	10		T145	1		T124	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	3		T46	1		T17	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	3		T12	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	3		T45	13		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T3	3		T13	3		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	14		T12	9		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T46	1		T48	4		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	10		T45	16		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	8		T122	6		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	12		T144	1		T129	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T127	1		T122	4		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T144	11		T212	1		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T120	4		T29	11		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T119	15		T219	11		T150	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T45	2		T47	1		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	9		T14	10		T120	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T145	16		T131	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T212	1		T125	4		T222	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T269	14		T270	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T47	2		T144	10		T125	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T150	4		T84	2		T223	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T10	8		T124	11		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T46	12		T17	5		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	4		T12	1		T124	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	2		T45	8		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T44	25		T127	14		T190	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	12		T12	6		T238	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	6		T128	11		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	10		T45	17		T119	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T122	13		T123	12		T147	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	11		T144	14		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T127	1		T122	11		T158	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T144	9		T212	2		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T120	6		T39	1		T214	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T119	2		T150	9		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	13		T257	6		T171	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	3		T14	2		T120	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T228	2		T276	12		T271	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T212	9		T125	4		T222	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T269	10		T270	15		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T35	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T268	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T252	1		T271	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T151	12		T229	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	5		T10	10		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T182	1		T150	3		T84	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T124	17		T215	1		T164	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T6	4		T145	11		T17	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	3		T12	2		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	3		T46	1		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T3	3		T13	3		T38	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	9		T45	13		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T46	1		T181	3		T219	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	14		T45	16		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T48	4		T128	12		T122	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	10		T129	9		T39	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	8		T127	1		T122	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T48	12		T144	1		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	11		T39	3		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T120	8		T144	11		T119	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T45	2		T47	1		T120	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T9	9		T14	10		T212	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T252	13		T271	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T237	17		T270	15		T274	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T10	8		T47	2		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T150	4		T84	2		T223	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T124	11		T164	2		T170	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T17	5		T122	11		T214	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	4		T12	1		T124	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	2		T46	12		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T44	25		T127	14		T190	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	6		T45	8		T246	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	6		T40	2		T213	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	12		T45	17		T119	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T128	11		T122	13		T123	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	10		T129	12		T190	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T127	1		T122	11		T158	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	11		T144	14		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T39	1		T214	13		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T120	6		T144	9		T119	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T120	6		T30	13		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T9	3		T14	2		T212	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10