Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22857

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3330

1

T6

3

T7

5

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20225

1

T1

163

T2

20

T4

12

auto[1]

5962

1

T1

1

T3

3

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	474	1			T1	1		T5	9		T12	2
values[0]	39	1			T45	21		T277	1		T210	16
values[1]	739	1			T10	18		T47	5		T145	11
values[2]	2892	1			T3	3		T10	26		T13	3
values[3]	747	1			T9	5		T11	20		T48	23
values[4]	534	1			T6	8		T10	7		T46	7
values[5]	638	1			T45	33		T145	16		T212	10
values[6]	907	1			T6	1		T12	3		T128	23
values[7]	564	1			T9	12		T122	15		T18	1
values[8]	626	1			T121	1		T181	3		T30	14
values[9]	1436	1			T6	3		T7	5		T12	15
minimum	16591	1			T1	163		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	852	1			T10	44		T45	21		T47	5
values[1]	2983	1			T3	3		T13	3		T38	2
values[2]	689	1			T6	8		T9	5		T11	20
values[3]	547	1			T10	7		T46	7		T127	15
values[4]	726	1			T6	1		T45	33		T128	23
values[5]	823	1			T9	12		T12	3		T123	3
values[6]	621	1			T121	1		T35	1		T122	15
values[7]	761	1			T12	15		T48	9		T181	3
values[8]	887	1			T45	2		T47	1		T48	4
values[9]	209	1			T6	3		T7	5		T14	12
minimum	17089	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	13		T45	9		T47	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	9		T47	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T212	3		T133	1		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T9	3		T11	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T130	1		T142	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	5		T17	10		T124	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T46	7		T127	15		T123	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T6	1		T45	18		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T212	10		T35	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T123	3		T219	1		T150	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	4		T12	2		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T121	1		T122	12		T190	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	1		T125	3		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	1		T181	1		T18	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	9		T30	14		T125	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T45	1		T47	1		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T48	1		T144	26		T30	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T79	11		T20	5		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T6	1		T7	1		T14	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16939	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	13		T45	12		T120	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	9		T145	10		T124	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T48	11		T140	10		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T133	7		T132	12		T143	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	7		T9	2		T11	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T142	3		T134	5		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	2		T17	10		T124	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T223	1		T259	5		T222	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T45	15		T128	11		T145	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T136	15		T220	1		T257	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T219	2		T150	2		T231	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	8		T12	1		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T122	3		T190	2		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T125	2		T133	11		T183	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T48	8		T181	2		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	6		T125	3		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T45	1		T120	7		T129	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	3		T144	7		T122	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T79	11		T20	5		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T6	2		T7	4		T14	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T278	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	456	1			T1	1		T5	9		T12	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T165	1		T279	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T45	9		T149	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T277	1		T210	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T47	4		T122	14		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	9		T47	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T3	3		T10	13		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T133	1		T236	14		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	3		T11	11		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T212	3		T19	1		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	1		T10	5		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	7		T127	15		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	18		T145	1		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T212	10		T123	13		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T6	1		T128	12		T123	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	2		T35	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T122	12		T18	1		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	4		T125	3		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T121	1		T181	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T30	14		T35	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T45	1		T47	1		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	433	1			T6	1		T7	1		T12	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16467	1			T1	163		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T279	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T45	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T210	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T122	5		T19	1		T150	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	9		T145	10		T124	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T10	13		T120	3		T140	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T133	7		T143	2		T146	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	2		T11	9		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T132	12		T223	9		T272	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	7		T10	2		T29	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T142	3		T134	5		T223	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T45	15		T145	15		T17	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T136	15		T220	1		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T128	11		T119	8		T150	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T133	3		T239	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T122	3		T219	2		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T9	8		T125	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T181	2		T151	14		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T219	13		T183	13		T272	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T45	1		T48	8		T120	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	2		T7	4		T12	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	14		T45	13		T47	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	10		T47	1		T145	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T212	1		T133	8		T132	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	8		T9	3		T11	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T130	1		T142	4		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	3		T17	15		T124	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T46	1		T127	1		T123	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	1		T45	16		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T212	1		T35	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T123	1		T219	3		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	9		T12	2		T40	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T121	1		T122	4		T190	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T35	1		T125	3		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T48	9		T181	3		T18	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	9		T30	1		T125	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T45	2		T47	1		T120	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T48	4		T144	9		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T79	12		T20	7		T227	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T6	3		T7	5		T14	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17064	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T278	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	12		T45	8		T47	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	8		T124	11		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T44	25		T48	11		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T212	2		T132	14		T280	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	2		T11	10		T84	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T223	12		T238	7		T272	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	4		T17	5		T124	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	6		T127	14		T123	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	17		T128	11		T119	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T212	9		T136	2		T220	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T123	2		T150	4		T158	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	3		T12	1		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T122	11		T190	9		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T125	2		T252	11		T281	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T158	2		T222	14		T221	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	6		T30	13		T125	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T120	6		T127	1		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T144	24		T30	10		T122	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T79	10		T20	3		T282	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T14	2		T46	12		T283	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T25	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	456	1			T1	1		T5	9		T12	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T165	1		T279	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T45	13		T149	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T277	1		T210	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	2		T122	6		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	10		T47	1		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T3	3		T10	14		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T133	8		T236	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	3		T11	10		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T212	1		T19	1		T132	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	8		T10	3		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T46	1		T127	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T45	16		T145	16		T17	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T212	1		T123	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T6	1		T128	12		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	2		T35	1		T133	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T122	4		T18	1		T219	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	9		T125	3		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T121	1		T181	3		T151	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T30	1		T35	1		T219	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T45	2		T47	1		T48	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T6	3		T7	5		T12	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16591	1			T1	163		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T279	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T45	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T210	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T47	2		T122	13		T150	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	8		T124	11		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T10	12		T44	25		T120	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T236	13		T146	5		T200	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	2		T11	10		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T212	2		T132	14		T223	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	4		T124	3		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T46	6		T127	14		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T45	17		T17	5		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T212	9		T123	12		T136	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T128	11		T123	2		T119	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T239	12		T217	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T122	11		T190	9		T236	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	3		T125	2		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T169	12		T164	6		T171	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T30	13		T252	11		T164	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T120	6		T127	1		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T12	6		T14	2		T46	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10