Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22770

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3417

1

T7

5

T9

12

T10

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20050

1

T1

163

T2

20

T4

12

auto[1]

6137

1

T1

1

T3

3

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	670	1			T1	1		T5	9		T6	3
values[0]	32	1			T277	1		T149	1		T25	30
values[1]	754	1			T10	18		T45	21		T47	5
values[2]	2890	1			T3	3		T10	26		T13	3
values[3]	753	1			T9	5		T11	20		T48	23
values[4]	574	1			T6	8		T10	7		T46	7
values[5]	571	1			T45	33		T145	16		T130	2
values[6]	936	1			T6	1		T12	3		T128	23
values[7]	578	1			T9	12		T181	3		T122	15
values[8]	653	1			T48	9		T121	1		T30	14
values[9]	1185	1			T12	15		T14	12		T45	2
minimum	16591	1			T1	163		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	696	1			T10	44		T47	5		T120	10
values[1]	2966	1			T3	3		T13	3		T38	2
values[2]	703	1			T6	8		T9	5		T11	20
values[3]	493	1			T10	7		T46	7		T127	15
values[4]	741	1			T6	1		T45	33		T128	23
values[5]	837	1			T9	12		T12	3		T123	3
values[6]	653	1			T121	1		T181	3		T35	1
values[7]	650	1			T48	9		T30	14		T18	1
values[8]	995	1			T12	15		T45	2		T46	13
values[9]	185	1			T6	3		T7	5		T14	12
minimum	17268	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	13		T47	4		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	9		T47	1		T120	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	1		T132	15		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	1		T9	3		T11	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	1		T123	13		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	5		T46	7		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T127	15		T17	10		T123	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	1		T145	1		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	18		T128	12		T212	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T123	3		T219	1		T150	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	4		T12	2		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T121	1		T181	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T125	3		T252	26		T272	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T48	1		T30	14		T18	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T219	1		T19	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T47	1		T120	7		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T12	9		T45	1		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T6	1		T129	13		T79	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T7	1		T14	7		T144	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16976	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T45	9		T184	9		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	13		T19	1		T143	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	9		T120	3		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T48	11		T140	10		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T133	7		T132	12		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	7		T9	2		T11	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T29	9		T134	5		T272	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T10	2		T219	10		T213	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T17	10		T124	2		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	15		T119	8		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T45	15		T128	11		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T219	2		T150	2		T231	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	8		T12	1		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T181	2		T122	3		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T125	2		T272	1		T37	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	8		T125	3		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T219	13		T84	2		T183	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T120	7		T144	7		T222	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	6		T45	1		T48	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T6	2		T129	8		T79	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T7	4		T14	5		T227	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T45	12		T184	8		T228	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	491	1			T1	1		T5	9		T6	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T7	1		T39	3		T214	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T149	1		T25	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	4		T122	14		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	9		T45	9		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T3	3		T10	13		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T120	7		T133	1		T150	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	3		T11	11		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T19	1		T132	15		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	1		T10	5		T46	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T127	15		T17	10		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T145	1		T130	2		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	18		T39	4		T136	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T6	1		T35	1		T123	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	2		T128	12		T212	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T181	1		T122	12		T18	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	4		T125	3		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	1		T121	1		T30	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T219	1		T19	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T47	1		T144	11		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T12	9		T14	7		T45	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16467	1			T1	163		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T6	2		T120	7		T129	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T7	4		T39	1		T146	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T25	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T122	5		T19	1		T143	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	9		T45	12		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T10	13		T140	10		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T120	3		T133	7		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	2		T11	9		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T132	12		T272	11		T234	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	7		T10	2		T219	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T17	10		T29	9		T124	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T145	15		T213	15		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T45	15		T39	10		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T119	8		T219	2		T150	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T128	11		T183	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T181	2		T122	3		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T9	8		T125	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	8		T133	11		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T219	13		T183	13		T194	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T144	7		T125	3		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	6		T14	5		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	14		T47	2		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	10		T47	1		T120	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T133	8		T132	13		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	8		T9	3		T11	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T29	10		T123	1		T19	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	3		T46	1		T219	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T127	1		T17	15		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	1		T145	16		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T45	16		T128	12		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T123	1		T219	3		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T9	9		T12	2		T40	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T121	1		T181	3		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T125	3		T252	2		T272	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	9		T30	1		T18	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T219	14		T19	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T47	1		T120	8		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	9		T45	2		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T6	3		T129	9		T79	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T7	5		T14	10		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17091	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T45	13		T184	9		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T10	12		T47	2		T244	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	8		T120	6		T124	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T44	25		T48	11		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T132	14		T150	7		T234	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	2		T11	10		T84	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T123	12		T238	7		T272	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	4		T46	6		T190	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T127	14		T17	5		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T119	2		T236	7		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T45	17		T128	11		T212	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T123	2		T150	4		T158	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	3		T12	1		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T122	11		T190	9		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T125	2		T252	24		T37	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T30	13		T125	4		T41	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T214	16		T84	2		T204	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T120	6		T144	10		T30	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	6		T46	12		T127	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T129	12		T79	10		T284	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T14	2		T144	14		T192	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T122	13		T285	1		T25	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T45	8		T184	8		T228	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	497	1			T1	1		T5	9		T6	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	5		T39	3		T214	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T149	1		T25	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	2		T122	6		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	10		T45	13		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T3	3		T10	14		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T120	4		T133	8		T150	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	3		T11	10		T48	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T19	1		T132	13		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	8		T10	3		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T127	1		T17	15		T29	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T145	16		T130	2		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T45	16		T39	14		T136	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T35	1		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	2		T128	12		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T181	3		T122	4		T18	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	9		T125	3		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	9		T121	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T219	14		T19	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T47	1		T144	8		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	9		T14	10		T45	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16591	1			T1	163		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T120	6		T129	12		T286	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T39	1		T214	13		T137	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T25	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T47	2		T122	13		T200	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	8		T45	8		T124	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T10	12		T44	25		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T120	6		T150	7		T146	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	2		T11	10		T48	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T132	14		T238	7		T272	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	4		T46	6		T190	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T127	14		T17	5		T123	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T236	7		T213	9		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T45	17		T136	2		T252	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T123	2		T119	2		T150	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T128	11		T212	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T122	11		T190	9		T236	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T9	3		T125	2		T40	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	13		T169	12		T203	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T252	11		T239	7		T148	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T144	10		T30	10		T125	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	6		T14	2		T46	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10