Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22385

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3802

1

T6

3

T7

5

T9

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20160

1

T1

164

T2

20

T4

12

auto[1]

6027

1

T3

3

T10

51

T11

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	61	1			T168	12		T287	9		T288	10
values[0]	39	1			T252	12		T170	9		T148	6
values[1]	813	1			T6	8		T45	21		T47	1
values[2]	2907	1			T3	3		T10	18		T13	3
values[3]	751	1			T6	1		T14	12		T127	15
values[4]	698	1			T7	5		T10	26		T48	9
values[5]	574	1			T9	5		T12	18		T127	2
values[6]	657	1			T10	7		T46	13		T144	33
values[7]	584	1			T11	20		T48	4		T29	10
values[8]	689	1			T46	7		T47	4		T212	10
values[9]	1368	1			T6	3		T9	12		T45	2
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1039	1			T6	8		T45	21		T47	1
values[1]	2806	1			T3	3		T10	18		T13	3
values[2]	907	1			T6	1		T7	5		T10	26
values[3]	589	1			T48	9		T145	12		T130	1
values[4]	622	1			T9	5		T12	18		T127	2
values[5]	592	1			T10	7		T46	13		T48	4
values[6]	637	1			T11	20		T46	7		T47	4
values[7]	725	1			T9	12		T121	1		T145	16
values[8]	948	1			T6	3		T120	24		T144	20
values[9]	245	1			T45	2		T48	23		T18	1
minimum	17077	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	1		T47	1		T122	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T45	9		T17	10		T123	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	9		T47	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	1		T10	13		T127	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T14	7		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	1		T145	1		T119	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T145	1		T130	1		T119	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T127	2		T212	3		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	3		T12	11		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	5		T48	1		T144	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T46	13		T19	1		T150	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	4		T212	10		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	11		T46	7		T30	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	4		T121	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T190	10		T236	14		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T120	14		T144	10		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T6	1		T122	14		T123	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T48	12		T18	1		T125	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T45	1		T184	9		T172	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16923	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T220	3		T289	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	7		T122	11		T151	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T45	12		T17	10		T39	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	894	1			T45	15		T128	11		T140	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	9		T219	2		T150	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	13		T181	2		T133	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	4		T14	5		T41	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T48	8		T145	10		T119	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T119	14		T84	2		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T19	1		T84	2		T143	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	2		T12	7		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	2		T48	3		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T150	2		T223	1		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T29	9		T39	1		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	9		T39	3		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	8		T145	15		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T190	2		T151	11		T258	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T120	10		T144	10		T20	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	2		T122	5		T124	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T48	11		T125	3		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T45	1		T184	8		T172	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T220	1		T289	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T168	12		T290	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T287	1		T288	10		T291	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T170	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T252	12		T148	2		T197	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T47	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T45	9		T123	3		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T3	3		T13	3		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	9		T47	1		T17	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	1		T127	15		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	7		T130	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	13		T48	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T84	3		T246	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T127	2		T212	3		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	3		T12	11		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	5		T144	26		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T46	13		T125	3		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T29	1		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	11		T30	14		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T47	4		T212	10		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T46	7		T123	13		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T9	4		T48	12		T120	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T6	1		T45	1		T122	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T290	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T287	8		T291	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T148	4		T197	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	7		T122	11		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	12		T39	10		T222	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T45	15		T128	11		T140	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	9		T17	10		T219	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	3		T183	16		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	5		T150	17		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	13		T48	8		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	4		T84	2		T246	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T19	1		T234	11		T266	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	2		T12	7		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	2		T144	7		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T125	2		T150	2		T257	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T48	3		T29	9		T122	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	9		T219	13		T213	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T219	10		T79	11		T223	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	3		T190	2		T272	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T9	8		T48	11		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T6	2		T45	1		T122	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T6	8		T47	1		T122	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T45	13		T17	15		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	10		T47	1		T219	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	1		T10	14		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	5		T14	10		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	9		T145	11		T119	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T145	1		T130	1		T119	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T127	1		T212	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	3		T12	11		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	3		T48	4		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	1		T19	1		T150	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	2		T212	1		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	10		T46	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	9		T121	1		T145	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T190	3		T236	1		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T120	12		T144	11		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	3		T122	6		T123	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T48	12		T18	1		T125	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T45	2		T184	9		T172	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17047	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T220	3		T289	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T122	11		T259	5		T231	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	8		T17	5		T123	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T44	25		T45	17		T128	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	8		T150	16		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	12		T127	14		T214	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	2		T41	2		T222	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T119	2		T236	6		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T119	2		T84	2		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T127	1		T212	2		T84	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	2		T12	7		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	4		T144	24		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T46	12		T150	4		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T47	2		T212	9		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	10		T46	6		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	3		T30	10		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T190	9		T236	13		T292	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T120	12		T144	9		T214	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T122	13		T123	24		T124	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T48	11		T125	4		T40	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T184	8		T172	13		T293	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T220	1		T289	16		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T168	1		T290	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T287	9		T288	1		T291	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T170	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T252	1		T148	5		T197	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	8		T47	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T45	13		T123	1		T39	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T3	3		T13	3		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	10		T47	1		T17	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T127	1		T133	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	10		T130	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	14		T48	9		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	5		T84	3		T246	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T127	1		T212	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	3		T12	11		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	3		T144	9		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	1		T125	3		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	4		T29	10		T122	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	10		T30	1		T219	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	2		T212	1		T219	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	1		T123	1		T39	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T9	9		T48	12		T120	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T6	3		T45	2		T122	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T168	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T288	9		T291	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T170	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T252	11		T148	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T122	11		T231	1		T244	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	8		T123	2		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T44	25		T45	17		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	8		T17	5		T200	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T127	14		T158	2		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	2		T150	16		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	12		T119	2		T214	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T84	2		T246	9		T37	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T127	1		T212	2		T168	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	2		T12	7		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	4		T144	24		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T46	12		T125	2		T150	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T122	11		T272	1		T153	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	10		T30	13		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T47	2		T212	9		T79	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	6		T123	12		T190	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	3		T48	11		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T122	13		T123	12		T124	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10