Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22400

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3787

1

T6

4

T7

5

T9

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20395

1

T1

164

T2

20

T4

12

auto[1]

5792

1

T3

3

T6

8

T9

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T10	7		T48	9		T29	10
values[0]	52	1			T255	11		T248	21		T294	1
values[1]	726	1			T6	3		T7	5		T9	5
values[2]	871	1			T47	1		T145	1		T30	14
values[3]	565	1			T10	26		T120	10		T144	20
values[4]	761	1			T6	8		T9	12		T45	33
values[5]	707	1			T14	12		T47	1		T145	11
values[6]	834	1			T12	15		T45	21		T46	13
values[7]	560	1			T6	1		T122	23		T119	11
values[8]	2904	1			T3	3		T10	18		T11	20
values[9]	911	1			T12	3		T47	1		T144	15
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	792	1			T6	3		T7	5		T9	5
values[1]	746	1			T145	1		T30	14		T130	1
values[2]	676	1			T10	26		T120	10		T127	2
values[3]	760	1			T6	8		T9	12		T45	33
values[4]	770	1			T12	15		T14	12		T47	4
values[5]	642	1			T45	21		T46	13		T48	23
values[6]	2822	1			T3	3		T6	1		T13	3
values[7]	798	1			T10	18		T11	20		T48	4
values[8]	817	1			T10	7		T12	3		T47	1
values[9]	128	1			T119	17		T272	7		T292	13
minimum	17236	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	3		T47	1		T127	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	1		T7	1		T46	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T130	1		T39	3		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T145	1		T30	14		T124	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T120	7		T144	10		T124	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	13		T127	2		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	1		T45	18		T128	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	4		T123	3		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	9		T14	7		T47	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T47	1		T145	1		T212	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T45	9		T46	13		T48	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T144	11		T130	1		T190	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T3	3		T13	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T122	12		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	11		T48	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T10	9		T129	11		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	1		T48	1		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	5		T12	2		T144	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T272	2		T292	13		T239	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T119	3		T240	1		T211	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16956	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T143	1		T295	8		T248	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	2		T133	7		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	2		T7	4		T145	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T39	1		T222	1		T220	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T124	16		T125	3		T20	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T120	3		T144	10		T124	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	13		T219	13		T132	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	7		T45	15		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	8		T219	10		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	6		T14	5		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	10		T84	2		T147	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T45	12		T48	11		T120	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T144	7		T190	2		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T45	1		T140	10		T232	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T122	11		T223	9		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	9		T48	3		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	9		T129	10		T142	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T48	8		T223	1		T258	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	2		T12	1		T181	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T272	5		T239	5		T21	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T119	14		T211	8		T296	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T143	2		T295	2		T248	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T48	1		T35	1		T297	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T10	5		T29	1		T119	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T255	11		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T248	9		T294	1		T298	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	3		T127	15		T212	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	1		T7	1		T46	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T47	1		T35	1		T39	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T145	1		T30	14		T124	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T120	7		T144	10		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	13		T20	5		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	1		T45	18		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	4		T127	2		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T14	7		T122	14		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	1		T145	1		T212	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T12	9		T45	9		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T144	11		T130	1		T190	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T119	3		T219	1		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T122	12		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1555	1			T3	3		T11	11		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	9		T129	11		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T47	1		T123	13		T18	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T12	2		T144	15		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T48	8		T297	3		T299	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T10	2		T29	9		T119	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T248	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	2		T133	7		T150	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	2		T7	4		T145	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	1		T222	1		T247	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T124	16		T125	3		T79	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T120	3		T144	10		T124	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T10	13		T20	5		T136	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	7		T45	15		T128	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	8		T219	23		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	5		T122	5		T143	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T145	10		T41	4		T84	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	6		T45	12		T48	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	7		T190	2		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T119	8		T219	2		T183	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T122	11		T223	9		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	918	1			T11	9		T45	1		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	9		T129	10		T19	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T223	1		T272	5		T239	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T181	2		T39	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	3		T47	1		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	3		T7	5		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T130	1		T39	3		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T145	1		T30	1		T124	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T120	4		T144	11		T124	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	14		T127	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	8		T45	16		T128	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	9		T123	1		T219	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	9		T14	10		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T47	1		T145	11		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T45	13		T46	1		T48	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	8		T130	1		T190	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T3	3		T13	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	1		T122	12		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	10		T48	4		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T10	10		T129	11		T142	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T47	1		T48	9		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T10	3		T12	2		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T272	6		T292	1		T239	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T119	15		T240	1		T211	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17087	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T143	3		T295	3		T248	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	2		T127	14		T212	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	6		T17	5		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	1		T220	1		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T30	13		T124	11		T125	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T120	6		T144	9		T124	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	12		T127	1		T132	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T45	17		T128	11		T30	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	3		T123	2		T158	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	6		T14	2		T47	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T212	2		T84	1		T147	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	8		T46	12		T48	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T144	10		T190	9		T150	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T44	25		T119	2		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T122	11		T223	12		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	10		T123	24		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	8		T129	10		T184	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T258	15		T233	16		T24	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	4		T12	1		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T272	1		T292	12		T239	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T119	2		T211	1		T296	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T87	10		T300	2		T251	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T295	7		T248	8		T254	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T48	9		T35	1		T297	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T10	3		T29	10		T119	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T255	1		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T248	13		T294	1		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	3		T127	1		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	3		T7	5		T46	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T47	1		T35	1		T39	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T145	1		T30	1		T124	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T120	4		T144	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	14		T20	7		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	8		T45	16		T128	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T9	9		T127	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	10		T122	6		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	1		T145	11		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	9		T45	13		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T144	8		T130	1		T190	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T119	9		T219	3		T182	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	1		T122	12		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T3	3		T11	10		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	10		T129	11		T19	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T47	1		T123	1		T18	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T12	2		T144	1		T181	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T301	5		T302	3		T303	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T10	4		T119	2		T252	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T255	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T248	8		T298	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	2		T127	14		T212	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	6		T17	5		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T39	1		T247	14		T234	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	13		T124	11		T125	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T120	6		T144	9		T124	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T10	12		T20	3		T231	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	17		T128	11		T30	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	3		T127	1		T132	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	2		T122	13		T214	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T212	2		T123	2		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	6		T45	8		T46	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T144	10		T190	9		T150	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T119	2		T214	16		T244	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T122	11		T223	12		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T11	10		T44	25		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	8		T129	10		T184	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T123	12		T272	1		T153	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	1		T144	14		T40	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10