Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26187

1

T1

164

T2

20

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22406

1

T1

164

T2

20

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3781

1

T6

3

T7

5

T9

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20191

1

T1

164

T2

20

T4

12

auto[1]

5996

1

T3

3

T10

51

T11

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22259

1

T1

164

T2

20

T3

3

auto[1]

3928

1

T5

3

T6

9

T7

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	343	1			T45	2		T48	23		T120	10
values[0]	68	1			T123	3		T252	12		T170	9
values[1]	773	1			T6	8		T45	21		T47	1
values[2]	2911	1			T3	3		T10	18		T13	3
values[3]	758	1			T6	1		T14	12		T127	15
values[4]	706	1			T7	5		T10	26		T48	9
values[5]	621	1			T9	5		T12	18		T127	2
values[6]	512	1			T10	7		T46	13		T144	33
values[7]	730	1			T11	20		T48	4		T29	10
values[8]	692	1			T9	12		T46	7		T47	4
values[9]	1027	1			T6	3		T120	14		T121	1
minimum	17046	1			T1	164		T2	20		T4	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	845	1			T6	8		T45	21		T47	1
values[1]	2860	1			T3	3		T10	18		T13	3
values[2]	846	1			T6	1		T7	5		T10	26
values[3]	606	1			T48	9		T145	12		T130	1
values[4]	605	1			T9	5		T12	18		T127	2
values[5]	579	1			T10	7		T46	13		T48	4
values[6]	708	1			T11	20		T46	7		T47	4
values[7]	733	1			T9	12		T121	1		T145	16
values[8]	1032	1			T6	3		T48	23		T120	24
values[9]	131	1			T45	2		T18	1		T124	6
minimum	17242	1			T1	164		T2	20		T4	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

4241

1

T9

5

T10

24

T11

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	1		T47	1		T122	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T45	9		T17	10		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	9		T47	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	1		T10	13		T127	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	1		T14	7		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	1		T145	1		T119	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	1		T130	1		T119	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T127	2		T212	3		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	3		T12	11		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	5		T48	1		T144	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T46	13		T19	1		T150	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	4		T212	10		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	11		T46	7		T30	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	4		T121	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T123	13		T190	10		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T48	12		T120	14		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T6	1		T122	14		T123	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T18	1		T125	5		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T45	1		T124	4		T184	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16963	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T123	3		T220	3		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	7		T122	11		T259	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	12		T17	10		T39	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T45	15		T128	11		T140	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	9		T219	2		T150	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	13		T133	3		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	4		T14	5		T41	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	8		T145	10		T119	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T119	14		T84	2		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T19	1		T84	2		T143	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	2		T12	7		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	2		T48	3		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T150	2		T223	1		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T29	9		T122	3		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	9		T39	3		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	8		T145	15		T129	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T190	2		T151	11		T221	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	11		T120	10		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	2		T122	5		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T125	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T45	1		T124	2		T184	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	3		T12	2		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T220	1		T148	4		T289	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T48	12		T120	7		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	1		T124	4		T236	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T170	9		T281	12		T304	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T123	3		T252	12		T148	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	1		T47	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T45	9		T17	10		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T3	3		T13	3		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	9		T47	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	1		T127	15		T128	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	7		T182	1		T150	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	13		T48	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	1		T130	1		T84	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T127	2		T212	3		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	3		T12	11		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	5		T144	26		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T46	13		T125	3		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	1		T29	1		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	11		T30	14		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	4		T47	4		T212	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T46	7		T123	13		T190	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T120	7		T121	1		T144	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	1		T122	14		T123	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T48	11		T120	3		T305	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T45	1		T124	2		T184	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T148	4		T197	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	7		T122	11		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	12		T17	10		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T45	15		T140	10		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	9		T219	2		T200	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T128	11		T133	3		T183	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	5		T150	17		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	13		T48	8		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	4		T84	2		T246	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T19	1		T234	11		T164	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	2		T12	7		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T10	2		T144	7		T84	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T125	2		T150	2		T257	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	3		T29	9		T122	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	9		T39	3		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	8		T129	8		T219	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T190	2		T221	1		T258	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T120	7		T144	10		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	2		T122	5		T133	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	3		T12	2		T14	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	8		T47	1		T122	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T45	13		T17	15		T39	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T3	3		T13	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	10		T47	1		T219	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T10	14		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	5		T14	10		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	9		T145	11		T119	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	1		T130	1		T119	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T127	1		T212	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	3		T12	11		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	3		T48	4		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T46	1		T19	1		T150	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T47	2		T212	1		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	10		T46	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T9	9		T121	1		T145	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T123	1		T190	3		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T48	12		T120	12		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	3		T122	6		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T18	1		T125	4		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T45	2		T124	3		T184	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17095	1			T1	164		T2	20		T4	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T123	1		T220	3		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T122	11		T259	5		T231	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T45	8		T17	5		T231	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T44	25		T45	17		T128	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	8		T150	16		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	12		T127	14		T214	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	2		T41	2		T222	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T119	2		T236	6		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T119	2		T84	2		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T127	1		T212	2		T84	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	2		T12	7		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	4		T144	24		T272	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T46	12		T150	4		T168	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T47	2		T212	9		T122	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	10		T46	6		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	3		T30	10		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T123	12		T190	9		T292	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T48	11		T120	12		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T122	13		T123	12		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T125	4		T298	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T124	3		T184	8		T306	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T170	8		T281	11		T304	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T123	2		T220	1		T252	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T48	12		T120	4		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	2		T124	3		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T170	1		T281	1		T304	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T123	1		T252	1		T148	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	8		T47	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T45	13		T17	15		T39	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T3	3		T13	3		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	10		T47	1		T219	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T127	1		T128	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	10		T182	1		T150	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	14		T48	9		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	5		T130	1		T84	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T127	1		T212	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	3		T12	11		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	3		T144	9		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	1		T125	3		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	4		T29	10		T122	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	10		T30	1		T39	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	9		T47	2		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	1		T123	1		T190	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T120	8		T121	1		T144	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	3		T122	6		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17046	1			T1	164		T2	20		T4	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T48	11		T120	6		T137	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T124	3		T236	7		T184	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T170	8		T281	11		T304	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T123	2		T252	11		T148	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T122	11		T231	1		T244	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	8		T17	5		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T44	25		T45	17		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	8		T200	1		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T127	14		T128	11		T214	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	2		T150	16		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	12		T119	2		T236	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T84	2		T246	9		T37	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T127	1		T212	2		T168	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	2		T12	7		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	4		T144	24		T84	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T46	12		T125	2		T150	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T122	11		T39	1		T272	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	10		T30	13		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	3		T47	2		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T46	6		T123	12		T190	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T120	6		T144	9		T30	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T122	13		T123	12		T135	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21946

1

T1

164

T2

20

T3

3

auto[1]

auto[0]

4241

1

T9

5

T10

24

T11

10