Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 99.07 96.67 100.00 100.00 98.83 98.33 92.09


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T793 /workspace/coverage/default/39.adc_ctrl_filters_polled.756694010 Apr 23 02:29:45 PM PDT 24 Apr 23 02:32:55 PM PDT 24 167711484764 ps
T794 /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3104683161 Apr 23 02:30:44 PM PDT 24 Apr 23 02:49:42 PM PDT 24 503171524213 ps
T312 /workspace/coverage/default/7.adc_ctrl_clock_gating.4237245786 Apr 23 02:26:08 PM PDT 24 Apr 23 02:45:09 PM PDT 24 497660721521 ps
T795 /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2552690666 Apr 23 02:29:38 PM PDT 24 Apr 23 02:40:55 PM PDT 24 326839254748 ps
T53 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3547330907 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:32 PM PDT 24 2208134945 ps
T796 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4114491228 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:30 PM PDT 24 463293809 ps
T54 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3399460258 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:39 PM PDT 24 4689509889 ps
T59 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2963206672 Apr 23 02:25:17 PM PDT 24 Apr 23 02:25:19 PM PDT 24 475222045 ps
T797 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.358159037 Apr 23 02:25:16 PM PDT 24 Apr 23 02:25:18 PM PDT 24 294768546 ps
T55 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.748528527 Apr 23 02:25:14 PM PDT 24 Apr 23 02:25:33 PM PDT 24 4574148176 ps
T798 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2354152736 Apr 23 02:25:32 PM PDT 24 Apr 23 02:25:33 PM PDT 24 375387141 ps
T799 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2872147478 Apr 23 02:25:10 PM PDT 24 Apr 23 02:25:12 PM PDT 24 553559861 ps
T101 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1274137461 Apr 23 02:25:16 PM PDT 24 Apr 23 02:25:22 PM PDT 24 774217916 ps
T56 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2896122223 Apr 23 02:25:25 PM PDT 24 Apr 23 02:25:48 PM PDT 24 8401660994 ps
T800 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3537091286 Apr 23 02:25:32 PM PDT 24 Apr 23 02:25:33 PM PDT 24 344865598 ps
T801 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2886524007 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:31 PM PDT 24 559706289 ps
T60 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3959356820 Apr 23 02:25:25 PM PDT 24 Apr 23 02:25:28 PM PDT 24 426846506 ps
T65 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1115703137 Apr 23 02:25:16 PM PDT 24 Apr 23 02:25:18 PM PDT 24 498498354 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3144035214 Apr 23 02:25:17 PM PDT 24 Apr 23 02:25:18 PM PDT 24 511880508 ps
T66 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3562767193 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:30 PM PDT 24 423767047 ps
T57 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2190726098 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:33 PM PDT 24 4212568575 ps
T114 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2990430239 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:32 PM PDT 24 4174177648 ps
T58 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.4236684583 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:36 PM PDT 24 8791163004 ps
T102 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2847966036 Apr 23 02:25:14 PM PDT 24 Apr 23 02:25:44 PM PDT 24 52772573766 ps
T802 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1830906181 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:21 PM PDT 24 478903193 ps
T67 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2362752394 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:21 PM PDT 24 699128289 ps
T115 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2547796417 Apr 23 02:25:21 PM PDT 24 Apr 23 02:25:35 PM PDT 24 4914569605 ps
T803 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1525162882 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:29 PM PDT 24 431315195 ps
T73 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3182259405 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:51 PM PDT 24 605507824 ps
T61 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1492747447 Apr 23 02:25:23 PM PDT 24 Apr 23 02:25:31 PM PDT 24 8235054692 ps
T804 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2666456444 Apr 23 02:25:31 PM PDT 24 Apr 23 02:25:33 PM PDT 24 328901568 ps
T805 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2798121821 Apr 23 02:25:30 PM PDT 24 Apr 23 02:25:32 PM PDT 24 389415363 ps
T86 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1737642095 Apr 23 02:25:25 PM PDT 24 Apr 23 02:25:27 PM PDT 24 437207293 ps
T806 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4260772673 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:29 PM PDT 24 509468137 ps
T70 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3063773301 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:28 PM PDT 24 432152206 ps
T97 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.712642381 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:15 PM PDT 24 632756217 ps
T807 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2085659369 Apr 23 02:25:34 PM PDT 24 Apr 23 02:25:36 PM PDT 24 428463298 ps
T808 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3098960352 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:20 PM PDT 24 371471105 ps
T809 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2035995964 Apr 23 02:25:33 PM PDT 24 Apr 23 02:25:34 PM PDT 24 465716240 ps
T69 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1900631208 Apr 23 02:25:12 PM PDT 24 Apr 23 02:25:31 PM PDT 24 8549776801 ps
T810 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.585444932 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:29 PM PDT 24 384429342 ps
T811 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1060360045 Apr 23 02:25:31 PM PDT 24 Apr 23 02:25:33 PM PDT 24 506971488 ps
T103 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2441344846 Apr 23 02:25:09 PM PDT 24 Apr 23 02:25:13 PM PDT 24 1268354315 ps
T812 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1027812531 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:31 PM PDT 24 341994715 ps
T813 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1185165954 Apr 23 02:25:34 PM PDT 24 Apr 23 02:25:35 PM PDT 24 320146736 ps
T814 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.951393246 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:14 PM PDT 24 474718663 ps
T815 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.563421780 Apr 23 02:25:35 PM PDT 24 Apr 23 02:25:36 PM PDT 24 406297438 ps
T104 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3553176656 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:21 PM PDT 24 568027221 ps
T816 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.353968509 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:32 PM PDT 24 4202611798 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.313296194 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:18 PM PDT 24 2140307127 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1211944097 Apr 23 02:25:21 PM PDT 24 Apr 23 02:25:22 PM PDT 24 635789055 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1843803963 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:52 PM PDT 24 4667376968 ps
T118 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1212917381 Apr 23 02:25:14 PM PDT 24 Apr 23 02:25:16 PM PDT 24 408815428 ps
T818 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3388574244 Apr 23 02:25:22 PM PDT 24 Apr 23 02:25:32 PM PDT 24 5409412442 ps
T74 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1912773100 Apr 23 02:25:09 PM PDT 24 Apr 23 02:25:11 PM PDT 24 530456499 ps
T105 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3938792406 Apr 23 02:25:12 PM PDT 24 Apr 23 02:25:15 PM PDT 24 1196380557 ps
T68 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3543535354 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:31 PM PDT 24 361837403 ps
T819 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3165755707 Apr 23 02:25:17 PM PDT 24 Apr 23 02:25:26 PM PDT 24 2834507923 ps
T820 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.791819266 Apr 23 02:25:23 PM PDT 24 Apr 23 02:25:25 PM PDT 24 290937494 ps
T72 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3092010195 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:29 PM PDT 24 698046471 ps
T821 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3647297766 Apr 23 02:25:12 PM PDT 24 Apr 23 02:25:14 PM PDT 24 345969030 ps
T822 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.102566313 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:32 PM PDT 24 8771392017 ps
T823 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4165720401 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:31 PM PDT 24 2617035013 ps
T824 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.242886130 Apr 23 02:25:16 PM PDT 24 Apr 23 02:25:18 PM PDT 24 559527781 ps
T825 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.122903486 Apr 23 02:25:17 PM PDT 24 Apr 23 02:25:19 PM PDT 24 538219272 ps
T826 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1244757044 Apr 23 02:25:35 PM PDT 24 Apr 23 02:25:37 PM PDT 24 350092679 ps
T827 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2847600551 Apr 23 02:25:20 PM PDT 24 Apr 23 02:25:23 PM PDT 24 2205044682 ps
T828 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1410530484 Apr 23 02:25:10 PM PDT 24 Apr 23 02:25:34 PM PDT 24 8580235443 ps
T106 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1710007920 Apr 23 02:25:20 PM PDT 24 Apr 23 02:25:22 PM PDT 24 405378916 ps
T107 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.204944670 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:30 PM PDT 24 702364566 ps
T108 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.973974963 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:56 PM PDT 24 26495532670 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3640900551 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:31 PM PDT 24 375915765 ps
T830 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.824856792 Apr 23 02:25:10 PM PDT 24 Apr 23 02:25:18 PM PDT 24 8927630216 ps
T75 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4049789212 Apr 23 02:25:30 PM PDT 24 Apr 23 02:25:32 PM PDT 24 676393941 ps
T339 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.143733167 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:24 PM PDT 24 4918329087 ps
T831 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2413366692 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:34 PM PDT 24 2255296367 ps
T832 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3745871403 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:22 PM PDT 24 4820854767 ps
T833 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2367230066 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:41 PM PDT 24 4689645140 ps
T834 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.646250231 Apr 23 02:25:31 PM PDT 24 Apr 23 02:25:33 PM PDT 24 354879951 ps
T835 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3204002149 Apr 23 02:25:08 PM PDT 24 Apr 23 02:25:11 PM PDT 24 658730024 ps
T836 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3250639742 Apr 23 02:25:24 PM PDT 24 Apr 23 02:25:26 PM PDT 24 360666708 ps
T837 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2037479775 Apr 23 02:25:31 PM PDT 24 Apr 23 02:25:33 PM PDT 24 343464295 ps
T838 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.164626476 Apr 23 02:25:33 PM PDT 24 Apr 23 02:25:35 PM PDT 24 414733404 ps
T839 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3820362087 Apr 23 02:25:17 PM PDT 24 Apr 23 02:25:21 PM PDT 24 679198200 ps
T840 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.939871255 Apr 23 02:25:20 PM PDT 24 Apr 23 02:25:22 PM PDT 24 1023160065 ps
T841 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.638000715 Apr 23 02:25:23 PM PDT 24 Apr 23 02:25:27 PM PDT 24 639325650 ps
T842 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.303760529 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:16 PM PDT 24 500356055 ps
T109 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3083671621 Apr 23 02:25:08 PM PDT 24 Apr 23 02:25:12 PM PDT 24 984475289 ps
T843 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3917439421 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:24 PM PDT 24 4312324129 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.155971361 Apr 23 02:25:16 PM PDT 24 Apr 23 02:25:27 PM PDT 24 4849532271 ps
T845 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1961116798 Apr 23 02:25:32 PM PDT 24 Apr 23 02:25:33 PM PDT 24 389743912 ps
T846 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.301865120 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:22 PM PDT 24 466922734 ps
T847 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1864927664 Apr 23 02:25:17 PM PDT 24 Apr 23 02:25:19 PM PDT 24 389534001 ps
T848 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1039674928 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:34 PM PDT 24 8978016553 ps
T110 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1448066071 Apr 23 02:25:25 PM PDT 24 Apr 23 02:25:26 PM PDT 24 531084557 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.161603766 Apr 23 02:25:24 PM PDT 24 Apr 23 02:25:25 PM PDT 24 526426182 ps
T850 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3725683149 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:30 PM PDT 24 1091117610 ps
T851 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1005952209 Apr 23 02:25:34 PM PDT 24 Apr 23 02:25:36 PM PDT 24 453391981 ps
T852 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3205505827 Apr 23 02:25:21 PM PDT 24 Apr 23 02:25:23 PM PDT 24 480444627 ps
T111 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3315964166 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:29 PM PDT 24 430180662 ps
T853 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.12918859 Apr 23 02:25:17 PM PDT 24 Apr 23 02:25:20 PM PDT 24 592017409 ps
T854 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.877351992 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:19 PM PDT 24 300024929 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3152298676 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:50 PM PDT 24 409083649 ps
T856 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3266025794 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:21 PM PDT 24 467293225 ps
T857 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2483784111 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:21 PM PDT 24 490824871 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2456293136 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:15 PM PDT 24 478719332 ps
T859 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2291403228 Apr 23 02:25:30 PM PDT 24 Apr 23 02:25:32 PM PDT 24 547007887 ps
T860 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1169745696 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:36 PM PDT 24 2307041031 ps
T861 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3222979870 Apr 23 02:25:30 PM PDT 24 Apr 23 02:25:32 PM PDT 24 291743604 ps
T862 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.415295973 Apr 23 02:25:16 PM PDT 24 Apr 23 02:25:19 PM PDT 24 1352064214 ps
T863 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3783454520 Apr 23 02:25:25 PM PDT 24 Apr 23 02:25:28 PM PDT 24 521525929 ps
T864 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.304379249 Apr 23 02:25:24 PM PDT 24 Apr 23 02:25:27 PM PDT 24 563289729 ps
T865 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.756298830 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:28 PM PDT 24 392380176 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.912259072 Apr 23 02:25:15 PM PDT 24 Apr 23 02:25:32 PM PDT 24 6099256899 ps
T112 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.253018420 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:31 PM PDT 24 348990565 ps
T867 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4121371826 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:20 PM PDT 24 531356403 ps
T868 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2751550918 Apr 23 02:25:48 PM PDT 24 Apr 23 02:25:51 PM PDT 24 760896069 ps
T869 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.810687390 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:44 PM PDT 24 3714442771 ps
T870 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1684894394 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:29 PM PDT 24 540040146 ps
T871 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2441917711 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:30 PM PDT 24 502843467 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1760460984 Apr 23 02:25:11 PM PDT 24 Apr 23 02:25:29 PM PDT 24 26635036267 ps
T873 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.52126509 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:23 PM PDT 24 605039699 ps
T874 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3233534162 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:21 PM PDT 24 4403314558 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2054036200 Apr 23 02:25:11 PM PDT 24 Apr 23 02:25:13 PM PDT 24 439659954 ps
T876 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1379840517 Apr 23 02:25:25 PM PDT 24 Apr 23 02:25:27 PM PDT 24 488698138 ps
T877 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2209491915 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:29 PM PDT 24 529334829 ps
T878 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3008383050 Apr 23 02:25:47 PM PDT 24 Apr 23 02:25:48 PM PDT 24 481588189 ps
T879 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3850742298 Apr 23 02:25:22 PM PDT 24 Apr 23 02:25:43 PM PDT 24 8540634070 ps
T880 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1638892755 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:30 PM PDT 24 374707941 ps
T881 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1419906976 Apr 23 02:25:16 PM PDT 24 Apr 23 02:27:57 PM PDT 24 40701601342 ps
T882 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3954118852 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:31 PM PDT 24 317744791 ps
T883 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3542222260 Apr 23 02:25:31 PM PDT 24 Apr 23 02:25:33 PM PDT 24 328345833 ps
T884 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2412831250 Apr 23 02:25:21 PM PDT 24 Apr 23 02:25:26 PM PDT 24 4838343463 ps
T885 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2712463465 Apr 23 02:25:22 PM PDT 24 Apr 23 02:25:23 PM PDT 24 675776307 ps
T886 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1149728341 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:30 PM PDT 24 480671089 ps
T887 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1088675462 Apr 23 02:25:15 PM PDT 24 Apr 23 02:25:22 PM PDT 24 4310412226 ps
T888 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4108235261 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:26 PM PDT 24 2270325053 ps
T889 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3190989924 Apr 23 02:25:33 PM PDT 24 Apr 23 02:25:35 PM PDT 24 509815261 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4250269647 Apr 23 02:25:15 PM PDT 24 Apr 23 02:25:19 PM PDT 24 1157691347 ps
T891 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2803622803 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:31 PM PDT 24 391542388 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1260091400 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:20 PM PDT 24 458829827 ps
T893 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1720113569 Apr 23 02:25:23 PM PDT 24 Apr 23 02:25:25 PM PDT 24 554945458 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1217986746 Apr 23 02:25:11 PM PDT 24 Apr 23 02:25:12 PM PDT 24 799351753 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.693526744 Apr 23 02:25:16 PM PDT 24 Apr 23 02:25:19 PM PDT 24 519967878 ps
T896 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1903329231 Apr 23 02:25:21 PM PDT 24 Apr 23 02:25:23 PM PDT 24 571023126 ps
T897 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3327833556 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:31 PM PDT 24 279433705 ps
T898 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2829338302 Apr 23 02:25:26 PM PDT 24 Apr 23 02:25:28 PM PDT 24 666389164 ps
T899 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1725054816 Apr 23 02:25:21 PM PDT 24 Apr 23 02:25:24 PM PDT 24 541694901 ps
T900 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2351178407 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:24 PM PDT 24 2280596109 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3538353698 Apr 23 02:25:27 PM PDT 24 Apr 23 02:25:30 PM PDT 24 443063650 ps
T902 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3472940025 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:35 PM PDT 24 4248421422 ps
T903 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2095834387 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:32 PM PDT 24 407087907 ps
T904 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3149323992 Apr 23 02:25:12 PM PDT 24 Apr 23 02:25:15 PM PDT 24 897184609 ps
T905 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4112244581 Apr 23 02:25:14 PM PDT 24 Apr 23 02:25:17 PM PDT 24 503241756 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1028873786 Apr 23 02:25:12 PM PDT 24 Apr 23 02:25:16 PM PDT 24 477580123 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.985837595 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:31 PM PDT 24 517874971 ps
T76 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3882044287 Apr 23 02:25:18 PM PDT 24 Apr 23 02:25:22 PM PDT 24 4413746539 ps
T908 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2781575286 Apr 23 02:25:13 PM PDT 24 Apr 23 02:25:33 PM PDT 24 8308498277 ps
T909 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4137420133 Apr 23 02:25:23 PM PDT 24 Apr 23 02:25:25 PM PDT 24 375792691 ps
T910 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1998908944 Apr 23 02:25:28 PM PDT 24 Apr 23 02:25:31 PM PDT 24 507921143 ps
T911 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.479898592 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:39 PM PDT 24 4369065379 ps
T912 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.764115605 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:21 PM PDT 24 363391088 ps
T913 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1289228579 Apr 23 02:25:33 PM PDT 24 Apr 23 02:25:35 PM PDT 24 434345897 ps
T914 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2095168640 Apr 23 02:25:29 PM PDT 24 Apr 23 02:25:31 PM PDT 24 425093853 ps
T915 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2273883979 Apr 23 02:25:19 PM PDT 24 Apr 23 02:25:22 PM PDT 24 621453357 ps
T916 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1943883582 Apr 23 02:25:23 PM PDT 24 Apr 23 02:25:25 PM PDT 24 474195024 ps
T917 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2647956469 Apr 23 02:25:23 PM PDT 24 Apr 23 02:25:46 PM PDT 24 7946818491 ps
T918 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1478428305 Apr 23 02:25:14 PM PDT 24 Apr 23 02:25:16 PM PDT 24 484636102 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3055879454 Apr 23 02:25:14 PM PDT 24 Apr 23 02:25:16 PM PDT 24 457533478 ps

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3551410944
Short name T9
Test name
Test status
Simulation time 328313851019 ps
CPU time 51.38 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:27:11 PM PDT 24
Peak memory 202256 kb
Host smart-59c64122-e5a9-4b7d-8c8e-d6854aff6292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551410944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3551410944
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.4010667724
Short name T14
Test name
Test status
Simulation time 193309856302 ps
CPU time 381.09 seconds
Started Apr 23 02:31:39 PM PDT 24
Finished Apr 23 02:38:00 PM PDT 24
Peak memory 210900 kb
Host smart-4070e8b6-336a-4a7d-b7b6-d1bb619bae16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010667724 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.4010667724
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4287491999
Short name T17
Test name
Test status
Simulation time 169452121010 ps
CPU time 235.04 seconds
Started Apr 23 02:26:21 PM PDT 24
Finished Apr 23 02:30:17 PM PDT 24
Peak memory 210928 kb
Host smart-5d93213d-80ad-4dee-8e2c-d485ac2187aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287491999 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.4287491999
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.815426534
Short name T10
Test name
Test status
Simulation time 552425355338 ps
CPU time 646.3 seconds
Started Apr 23 02:31:08 PM PDT 24
Finished Apr 23 02:41:55 PM PDT 24
Peak memory 202264 kb
Host smart-9fde66f8-96b1-46ab-9670-ed5e0fb6848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815426534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.815426534
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3986644271
Short name T84
Test name
Test status
Simulation time 107753962556 ps
CPU time 246.85 seconds
Started Apr 23 02:31:10 PM PDT 24
Finished Apr 23 02:35:17 PM PDT 24
Peak memory 218900 kb
Host smart-d0ac1fa7-f216-4634-8f12-e60f2fdbaade
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986644271 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3986644271
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2345126173
Short name T45
Test name
Test status
Simulation time 559543519683 ps
CPU time 451.23 seconds
Started Apr 23 02:26:21 PM PDT 24
Finished Apr 23 02:33:54 PM PDT 24
Peak memory 202228 kb
Host smart-ef323a26-0634-478b-9c99-eb13a3e324e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345126173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2345126173
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1984811458
Short name T150
Test name
Test status
Simulation time 586696257642 ps
CPU time 317.47 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:31:23 PM PDT 24
Peak memory 202276 kb
Host smart-4bd9db9e-8b3f-40cd-836f-debdc8f279c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984811458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1984811458
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1051900139
Short name T48
Test name
Test status
Simulation time 484573457891 ps
CPU time 254.01 seconds
Started Apr 23 02:27:49 PM PDT 24
Finished Apr 23 02:32:03 PM PDT 24
Peak memory 202212 kb
Host smart-d772edf3-a72b-4b5b-b386-00ff6d1c6fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051900139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1051900139
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.906658105
Short name T122
Test name
Test status
Simulation time 498164420925 ps
CPU time 1103.1 seconds
Started Apr 23 02:30:46 PM PDT 24
Finished Apr 23 02:49:09 PM PDT 24
Peak memory 202216 kb
Host smart-abc37cfc-8ea2-44fc-852d-e63e055fd3b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906658105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.906658105
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1977243704
Short name T39
Test name
Test status
Simulation time 517505754682 ps
CPU time 673.5 seconds
Started Apr 23 02:26:07 PM PDT 24
Finished Apr 23 02:37:21 PM PDT 24
Peak memory 218284 kb
Host smart-32b4a72a-57e7-432b-b858-7a3b3c4d0e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977243704 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1977243704
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3562767193
Short name T66
Test name
Test status
Simulation time 423767047 ps
CPU time 1.63 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201428 kb
Host smart-598c0dd7-c780-4100-8c18-2b0b76553b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562767193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3562767193
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2647846421
Short name T62
Test name
Test status
Simulation time 7984445989 ps
CPU time 18.65 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:26:20 PM PDT 24
Peak memory 218872 kb
Host smart-c0d06fa2-28b4-44ec-beae-35f374570375
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647846421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2647846421
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3593864369
Short name T133
Test name
Test status
Simulation time 487372725258 ps
CPU time 105.98 seconds
Started Apr 23 02:26:52 PM PDT 24
Finished Apr 23 02:28:39 PM PDT 24
Peak memory 202304 kb
Host smart-64b2f8c5-2525-4839-8a16-77f351cd201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593864369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3593864369
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3955101384
Short name T252
Test name
Test status
Simulation time 512455402146 ps
CPU time 1156.99 seconds
Started Apr 23 02:30:28 PM PDT 24
Finished Apr 23 02:49:46 PM PDT 24
Peak memory 202248 kb
Host smart-f7b54dc4-102b-4990-977e-7e58e38c42ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955101384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3955101384
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.845344656
Short name T212
Test name
Test status
Simulation time 342430835539 ps
CPU time 193.29 seconds
Started Apr 23 02:26:42 PM PDT 24
Finished Apr 23 02:29:56 PM PDT 24
Peak memory 202268 kb
Host smart-82b9db33-e0a8-4cac-af24-d15e87453cc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845344656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.845344656
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.193210605
Short name T144
Test name
Test status
Simulation time 487420052425 ps
CPU time 288.77 seconds
Started Apr 23 02:28:37 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 202268 kb
Host smart-f3383eb6-1c59-4d7c-8f47-0f83b50163c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193210605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.193210605
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.362644720
Short name T228
Test name
Test status
Simulation time 504936757248 ps
CPU time 580.84 seconds
Started Apr 23 02:28:01 PM PDT 24
Finished Apr 23 02:37:42 PM PDT 24
Peak memory 202280 kb
Host smart-30ba4ce8-643b-4584-96ff-5a3ff44f4024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362644720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.362644720
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2847966036
Short name T102
Test name
Test status
Simulation time 52772573766 ps
CPU time 28.96 seconds
Started Apr 23 02:25:14 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 201444 kb
Host smart-9d458f24-2ef6-4009-821b-a05ef73a438e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847966036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2847966036
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.84528534
Short name T257
Test name
Test status
Simulation time 435661913877 ps
CPU time 455.65 seconds
Started Apr 23 02:26:23 PM PDT 24
Finished Apr 23 02:34:00 PM PDT 24
Peak memory 202184 kb
Host smart-6ea098a6-6790-4eac-9be2-e2eaa3d74010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84528534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.84528534
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2172010746
Short name T259
Test name
Test status
Simulation time 401525345262 ps
CPU time 871.39 seconds
Started Apr 23 02:26:11 PM PDT 24
Finished Apr 23 02:40:43 PM PDT 24
Peak memory 202332 kb
Host smart-f561c521-d7da-4704-b2e5-afc7010ef9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172010746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2172010746
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2421449969
Short name T239
Test name
Test status
Simulation time 333451900155 ps
CPU time 505.6 seconds
Started Apr 23 02:28:23 PM PDT 24
Finished Apr 23 02:36:49 PM PDT 24
Peak memory 202276 kb
Host smart-80e6a626-363b-4404-b900-f4bd23755197
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421449969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2421449969
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1748897405
Short name T151
Test name
Test status
Simulation time 332974851169 ps
CPU time 742.38 seconds
Started Apr 23 02:26:30 PM PDT 24
Finished Apr 23 02:38:53 PM PDT 24
Peak memory 202284 kb
Host smart-53ac18cc-5adc-4f08-bd1a-5d3af4371fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748897405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1748897405
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2009363233
Short name T127
Test name
Test status
Simulation time 434894013689 ps
CPU time 236.53 seconds
Started Apr 23 02:28:35 PM PDT 24
Finished Apr 23 02:32:32 PM PDT 24
Peak memory 202344 kb
Host smart-43ed0a73-6f44-45e0-8cc3-2d041a32d2b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009363233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2009363233
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2919251968
Short name T210
Test name
Test status
Simulation time 494444430641 ps
CPU time 286.68 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:30:51 PM PDT 24
Peak memory 202228 kb
Host smart-115219d2-6e27-4afd-9239-9ed287afd63b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919251968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2919251968
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3358682461
Short name T217
Test name
Test status
Simulation time 512573683449 ps
CPU time 83.18 seconds
Started Apr 23 02:25:54 PM PDT 24
Finished Apr 23 02:27:18 PM PDT 24
Peak memory 202268 kb
Host smart-407ac492-021b-42a9-a1a0-427ac2a488cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358682461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3358682461
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2524674914
Short name T145
Test name
Test status
Simulation time 488259551499 ps
CPU time 286.57 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:30:48 PM PDT 24
Peak memory 202292 kb
Host smart-a2e21b92-ed1e-4bae-8aa7-f4a46c53fbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524674914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2524674914
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3866897302
Short name T129
Test name
Test status
Simulation time 323391439676 ps
CPU time 204.05 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:29:45 PM PDT 24
Peak memory 202200 kb
Host smart-1c0cb6da-310c-4c60-bb0b-9a474cf03ca8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866897302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3866897302
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1807252774
Short name T168
Test name
Test status
Simulation time 606290708775 ps
CPU time 1372.74 seconds
Started Apr 23 02:25:57 PM PDT 24
Finished Apr 23 02:48:50 PM PDT 24
Peak memory 202260 kb
Host smart-c8a538b9-8785-4e22-963b-47eb1a09ed9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807252774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1807252774
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2896122223
Short name T56
Test name
Test status
Simulation time 8401660994 ps
CPU time 22.88 seconds
Started Apr 23 02:25:25 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 201488 kb
Host smart-0a6d0580-6296-430a-8b89-4053047ef43f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896122223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2896122223
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3590542662
Short name T345
Test name
Test status
Simulation time 444544339 ps
CPU time 0.79 seconds
Started Apr 23 02:25:52 PM PDT 24
Finished Apr 23 02:25:54 PM PDT 24
Peak memory 201952 kb
Host smart-c10b8213-321e-4671-a674-4402ec90a305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590542662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3590542662
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1121305363
Short name T244
Test name
Test status
Simulation time 516270327244 ps
CPU time 325.78 seconds
Started Apr 23 02:30:14 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 202268 kb
Host smart-0f0f65b0-5aa3-41b9-8732-d981b0279ca8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121305363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1121305363
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2226428342
Short name T211
Test name
Test status
Simulation time 157330517536 ps
CPU time 512.6 seconds
Started Apr 23 02:26:27 PM PDT 24
Finished Apr 23 02:35:00 PM PDT 24
Peak memory 218016 kb
Host smart-352090f5-d4c0-488a-82a8-72791bb69377
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226428342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2226428342
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.511424401
Short name T140
Test name
Test status
Simulation time 322623467745 ps
CPU time 699.05 seconds
Started Apr 23 02:26:57 PM PDT 24
Finished Apr 23 02:38:36 PM PDT 24
Peak memory 202288 kb
Host smart-3d71274a-3c9a-4907-8dcc-3bae9155c1bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=511424401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.511424401
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3516069119
Short name T125
Test name
Test status
Simulation time 339917330837 ps
CPU time 206.11 seconds
Started Apr 23 02:30:40 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 202364 kb
Host smart-e94663e1-c378-43ae-a32a-b25e78fbc0df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516069119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3516069119
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3553176656
Short name T104
Test name
Test status
Simulation time 568027221 ps
CPU time 1.49 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 201264 kb
Host smart-b7127a0f-cbb3-41f8-9c7c-18d236a1b615
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553176656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3553176656
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.638000715
Short name T841
Test name
Test status
Simulation time 639325650 ps
CPU time 4.11 seconds
Started Apr 23 02:25:23 PM PDT 24
Finished Apr 23 02:25:27 PM PDT 24
Peak memory 210692 kb
Host smart-9bd83d4b-d895-45d5-a971-7c949389da5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638000715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.638000715
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.4260008971
Short name T271
Test name
Test status
Simulation time 362899025005 ps
CPU time 859.89 seconds
Started Apr 23 02:30:08 PM PDT 24
Finished Apr 23 02:44:28 PM PDT 24
Peak memory 202084 kb
Host smart-b8b0fb36-87c3-4f7c-b8bc-c26e2248cbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260008971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4260008971
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2718892854
Short name T19
Test name
Test status
Simulation time 53727872910 ps
CPU time 132 seconds
Started Apr 23 02:28:28 PM PDT 24
Finished Apr 23 02:30:41 PM PDT 24
Peak memory 210988 kb
Host smart-5e1c8837-7bf2-4a07-9cf5-3e086661a023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718892854 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2718892854
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.380930183
Short name T170
Test name
Test status
Simulation time 512195975522 ps
CPU time 215.9 seconds
Started Apr 23 02:28:12 PM PDT 24
Finished Apr 23 02:31:49 PM PDT 24
Peak memory 202300 kb
Host smart-f29eed37-2796-4539-8f26-cc346c0f51f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380930183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.380930183
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.213483102
Short name T328
Test name
Test status
Simulation time 503179355280 ps
CPU time 91.23 seconds
Started Apr 23 02:28:20 PM PDT 24
Finished Apr 23 02:29:52 PM PDT 24
Peak memory 210548 kb
Host smart-0bd4942a-8ba6-4903-b835-5d3060b22f17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213483102 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.213483102
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.924744333
Short name T190
Test name
Test status
Simulation time 852034241607 ps
CPU time 905.5 seconds
Started Apr 23 02:27:14 PM PDT 24
Finished Apr 23 02:42:20 PM PDT 24
Peak memory 212868 kb
Host smart-094efb9a-5eef-4d50-8e85-8a8490a8a481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924744333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
924744333
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.865393413
Short name T230
Test name
Test status
Simulation time 358926874984 ps
CPU time 225.26 seconds
Started Apr 23 02:27:48 PM PDT 24
Finished Apr 23 02:31:34 PM PDT 24
Peak memory 202268 kb
Host smart-9c55aa06-cf58-42af-ae1a-85861a7e12fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865393413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.865393413
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2132400042
Short name T318
Test name
Test status
Simulation time 355145744461 ps
CPU time 758.81 seconds
Started Apr 23 02:28:50 PM PDT 24
Finished Apr 23 02:41:29 PM PDT 24
Peak memory 202288 kb
Host smart-e7ad4e82-f1f9-4251-8752-a1bf15f4b990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132400042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2132400042
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1642975120
Short name T148
Test name
Test status
Simulation time 512950684472 ps
CPU time 336.85 seconds
Started Apr 23 02:31:07 PM PDT 24
Finished Apr 23 02:36:44 PM PDT 24
Peak memory 202268 kb
Host smart-5777bec9-684a-4874-84e5-c64ee731a3c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642975120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1642975120
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3495791406
Short name T321
Test name
Test status
Simulation time 336726528124 ps
CPU time 720.84 seconds
Started Apr 23 02:29:37 PM PDT 24
Finished Apr 23 02:41:38 PM PDT 24
Peak memory 202360 kb
Host smart-f45ec5de-c59f-464f-aa33-9e8fe7865093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495791406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3495791406
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1095446264
Short name T219
Test name
Test status
Simulation time 492511686394 ps
CPU time 462.23 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 202280 kb
Host smart-4b264b00-5ea1-4765-9592-cd4258dd6014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095446264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1095446264
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1765652755
Short name T255
Test name
Test status
Simulation time 536758882330 ps
CPU time 647.1 seconds
Started Apr 23 02:26:08 PM PDT 24
Finished Apr 23 02:36:56 PM PDT 24
Peak memory 202292 kb
Host smart-c2dd2471-75bd-4a39-920c-e51bdcedb264
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765652755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1765652755
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.66919492
Short name T315
Test name
Test status
Simulation time 139316848941 ps
CPU time 116.64 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:27:50 PM PDT 24
Peak memory 209912 kb
Host smart-b3022b13-d295-4ba3-83e2-7510bbcbb9b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66919492 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.66919492
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3223855615
Short name T40
Test name
Test status
Simulation time 77460890577 ps
CPU time 329.71 seconds
Started Apr 23 02:27:49 PM PDT 24
Finished Apr 23 02:33:19 PM PDT 24
Peak memory 210816 kb
Host smart-7977624e-7589-4e27-bff2-839dbfdebe4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223855615 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3223855615
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.51917588
Short name T25
Test name
Test status
Simulation time 1153737185971 ps
CPU time 287.54 seconds
Started Apr 23 02:28:04 PM PDT 24
Finished Apr 23 02:32:52 PM PDT 24
Peak memory 210916 kb
Host smart-457f43d3-23c7-4d87-9e98-212188cd487a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51917588 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.51917588
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3694785270
Short name T289
Test name
Test status
Simulation time 488556945040 ps
CPU time 380.13 seconds
Started Apr 23 02:29:07 PM PDT 24
Finished Apr 23 02:35:27 PM PDT 24
Peak memory 202296 kb
Host smart-30ee7a7e-1ca8-4344-bccc-0fb50cafa2c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694785270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3694785270
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.435147485
Short name T291
Test name
Test status
Simulation time 165308133028 ps
CPU time 251.9 seconds
Started Apr 23 02:26:12 PM PDT 24
Finished Apr 23 02:30:25 PM PDT 24
Peak memory 202336 kb
Host smart-07498435-18da-4c35-92e7-cd5a88719ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435147485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.435147485
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1973435573
Short name T270
Test name
Test status
Simulation time 339721911172 ps
CPU time 104.39 seconds
Started Apr 23 02:26:21 PM PDT 24
Finished Apr 23 02:28:07 PM PDT 24
Peak memory 202292 kb
Host smart-0d75f6c1-7c12-4449-a998-fcb5d09a4e2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973435573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1973435573
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2668748179
Short name T268
Test name
Test status
Simulation time 334540349189 ps
CPU time 188.33 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:29:35 PM PDT 24
Peak memory 202400 kb
Host smart-7e5305e1-4ddf-4b45-b91d-53e188919180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668748179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2668748179
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1294907594
Short name T189
Test name
Test status
Simulation time 109663751407 ps
CPU time 455.45 seconds
Started Apr 23 02:26:45 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 202572 kb
Host smart-773fd9a6-6cb9-4def-8592-c2771b9932b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294907594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1294907594
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4226025436
Short name T142
Test name
Test status
Simulation time 164182813483 ps
CPU time 50.2 seconds
Started Apr 23 02:27:05 PM PDT 24
Finished Apr 23 02:27:56 PM PDT 24
Peak memory 202264 kb
Host smart-0d26e780-20ed-4220-a883-d7f4174b46d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226025436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4226025436
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1793155106
Short name T260
Test name
Test status
Simulation time 337419609733 ps
CPU time 767.48 seconds
Started Apr 23 02:28:04 PM PDT 24
Finished Apr 23 02:40:52 PM PDT 24
Peak memory 202332 kb
Host smart-181b687e-89c7-4df9-8343-556ebbce4f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793155106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1793155106
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.4182686574
Short name T310
Test name
Test status
Simulation time 507130605947 ps
CPU time 243.27 seconds
Started Apr 23 02:26:15 PM PDT 24
Finished Apr 23 02:30:19 PM PDT 24
Peak memory 202328 kb
Host smart-873ce7fc-8434-44a0-a7ac-1ea282bc117d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182686574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.4182686574
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.789083085
Short name T246
Test name
Test status
Simulation time 171934974196 ps
CPU time 24.69 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:26:45 PM PDT 24
Peak memory 202264 kb
Host smart-62374af7-8804-4210-926a-b3c0bdf6600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789083085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.789083085
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3300475906
Short name T279
Test name
Test status
Simulation time 352470612002 ps
CPU time 747.58 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:38:32 PM PDT 24
Peak memory 202192 kb
Host smart-84e04b6c-23d2-4e28-9bf8-2b8f928d8d63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300475906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3300475906
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2413744845
Short name T95
Test name
Test status
Simulation time 167897171416 ps
CPU time 75.11 seconds
Started Apr 23 02:27:31 PM PDT 24
Finished Apr 23 02:28:47 PM PDT 24
Peak memory 202268 kb
Host smart-123d6f58-6fc5-4365-b23c-fbd06123430c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413744845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2413744845
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2550807017
Short name T248
Test name
Test status
Simulation time 494040242579 ps
CPU time 321.26 seconds
Started Apr 23 02:27:30 PM PDT 24
Finished Apr 23 02:32:51 PM PDT 24
Peak memory 202328 kb
Host smart-74c77574-5341-4af6-b2ce-bc2489784470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550807017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2550807017
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1748550983
Short name T274
Test name
Test status
Simulation time 329156407967 ps
CPU time 684.24 seconds
Started Apr 23 02:30:00 PM PDT 24
Finished Apr 23 02:41:25 PM PDT 24
Peak memory 202400 kb
Host smart-a8805aaa-87ab-4699-bd0b-0e81d5f83a32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748550983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1748550983
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4237245786
Short name T312
Test name
Test status
Simulation time 497660721521 ps
CPU time 1138.94 seconds
Started Apr 23 02:26:08 PM PDT 24
Finished Apr 23 02:45:09 PM PDT 24
Peak memory 202284 kb
Host smart-875673a4-0444-4a2f-9034-0c19939fe6f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237245786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4237245786
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3471076143
Short name T24
Test name
Test status
Simulation time 194408400908 ps
CPU time 113.36 seconds
Started Apr 23 02:26:24 PM PDT 24
Finished Apr 23 02:28:18 PM PDT 24
Peak memory 211712 kb
Host smart-d929fba8-568a-4c71-9b1a-fce454bf04cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471076143 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3471076143
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1908625778
Short name T278
Test name
Test status
Simulation time 326866073397 ps
CPU time 133.86 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:28:36 PM PDT 24
Peak memory 202200 kb
Host smart-7d0c884e-bd1f-412c-b0da-bdb4f8a0f488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908625778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1908625778
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4044983806
Short name T233
Test name
Test status
Simulation time 530819281912 ps
CPU time 323.01 seconds
Started Apr 23 02:27:42 PM PDT 24
Finished Apr 23 02:33:06 PM PDT 24
Peak memory 202276 kb
Host smart-d2c956ce-ca54-4bc2-9f4d-d006a3957e00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044983806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4044983806
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2724817451
Short name T261
Test name
Test status
Simulation time 496818808329 ps
CPU time 598.57 seconds
Started Apr 23 02:30:07 PM PDT 24
Finished Apr 23 02:40:06 PM PDT 24
Peak memory 202320 kb
Host smart-d473a91c-ce20-445b-a113-55fab22eaad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724817451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2724817451
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3755369924
Short name T192
Test name
Test status
Simulation time 1416984809486 ps
CPU time 1217.67 seconds
Started Apr 23 02:30:22 PM PDT 24
Finished Apr 23 02:50:40 PM PDT 24
Peak memory 218636 kb
Host smart-7c19f413-51e0-489c-a6dd-9f79d2434f18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755369924 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3755369924
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2354734557
Short name T35
Test name
Test status
Simulation time 324261223738 ps
CPU time 767.26 seconds
Started Apr 23 02:26:21 PM PDT 24
Finished Apr 23 02:39:10 PM PDT 24
Peak memory 202176 kb
Host smart-52bf490e-b995-48a4-85cd-dda94edf9ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354734557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2354734557
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3343799929
Short name T225
Test name
Test status
Simulation time 492756268231 ps
CPU time 1087.6 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:44:31 PM PDT 24
Peak memory 202172 kb
Host smart-07a3cf4b-423c-464b-a0d3-7755ca19a36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343799929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3343799929
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2026301470
Short name T200
Test name
Test status
Simulation time 239694157710 ps
CPU time 388.04 seconds
Started Apr 23 02:26:53 PM PDT 24
Finished Apr 23 02:33:21 PM PDT 24
Peak memory 210896 kb
Host smart-09ff2ba4-e546-490a-8671-ba735344be09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026301470 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2026301470
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3336263837
Short name T332
Test name
Test status
Simulation time 338574464290 ps
CPU time 794.22 seconds
Started Apr 23 02:25:59 PM PDT 24
Finished Apr 23 02:39:14 PM PDT 24
Peak memory 202188 kb
Host smart-e7e6d5dc-a28a-4606-84ec-e28d5ff9ccc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336263837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3336263837
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.554430880
Short name T251
Test name
Test status
Simulation time 332675624055 ps
CPU time 75.62 seconds
Started Apr 23 02:28:20 PM PDT 24
Finished Apr 23 02:29:36 PM PDT 24
Peak memory 202248 kb
Host smart-57d2afeb-2b42-4002-ba6a-1203e06df8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554430880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.554430880
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1357222266
Short name T147
Test name
Test status
Simulation time 342198725047 ps
CPU time 221.93 seconds
Started Apr 23 02:30:19 PM PDT 24
Finished Apr 23 02:34:01 PM PDT 24
Peak memory 202220 kb
Host smart-8c9ec20a-284b-462e-a59c-abfeb3213140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357222266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1357222266
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.812357798
Short name T277
Test name
Test status
Simulation time 328380862914 ps
CPU time 757.72 seconds
Started Apr 23 02:26:08 PM PDT 24
Finished Apr 23 02:38:48 PM PDT 24
Peak memory 202332 kb
Host smart-cc270324-b90d-4d8e-8fe8-e85fdefd39a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812357798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.812357798
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3882044287
Short name T76
Test name
Test status
Simulation time 4413746539 ps
CPU time 3.94 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201532 kb
Host smart-0ff6d469-f4b3-4166-bb40-e848c2ab84a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882044287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3882044287
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.204981674
Short name T301
Test name
Test status
Simulation time 340674694068 ps
CPU time 779.81 seconds
Started Apr 23 02:25:56 PM PDT 24
Finished Apr 23 02:38:56 PM PDT 24
Peak memory 202244 kb
Host smart-be66c913-298c-4cb6-9b20-a5d8a08b3fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204981674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.204981674
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2602085864
Short name T208
Test name
Test status
Simulation time 75293415061 ps
CPU time 244.67 seconds
Started Apr 23 02:26:42 PM PDT 24
Finished Apr 23 02:30:47 PM PDT 24
Peak memory 202588 kb
Host smart-277279c0-47d4-462b-8c2a-32e76d85fa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602085864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2602085864
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3464733223
Short name T269
Test name
Test status
Simulation time 163782355020 ps
CPU time 97.8 seconds
Started Apr 23 02:26:47 PM PDT 24
Finished Apr 23 02:28:25 PM PDT 24
Peak memory 202252 kb
Host smart-cc629eb9-d0f6-4249-b3f8-7057ba64cf51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464733223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3464733223
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.8582411
Short name T198
Test name
Test status
Simulation time 96337778704 ps
CPU time 324.8 seconds
Started Apr 23 02:27:02 PM PDT 24
Finished Apr 23 02:32:27 PM PDT 24
Peak memory 202540 kb
Host smart-20f916f5-5983-420e-a2b8-cc8413e47bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8582411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.8582411
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.4031239055
Short name T314
Test name
Test status
Simulation time 51314213606 ps
CPU time 152.42 seconds
Started Apr 23 02:27:28 PM PDT 24
Finished Apr 23 02:30:01 PM PDT 24
Peak memory 211276 kb
Host smart-ee8cee16-d02e-4065-b52a-943aa2dcfd87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031239055 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.4031239055
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3654216044
Short name T194
Test name
Test status
Simulation time 391876275656 ps
CPU time 982.84 seconds
Started Apr 23 02:27:32 PM PDT 24
Finished Apr 23 02:43:55 PM PDT 24
Peak memory 213180 kb
Host smart-2be76c79-b97f-470e-93f0-6b57af0ec951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654216044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3654216044
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.341843529
Short name T196
Test name
Test status
Simulation time 18950729908 ps
CPU time 76.09 seconds
Started Apr 23 02:26:07 PM PDT 24
Finished Apr 23 02:27:24 PM PDT 24
Peak memory 210988 kb
Host smart-5e996f55-9a26-4184-967f-9b002563c1a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341843529 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.341843529
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4050175662
Short name T218
Test name
Test status
Simulation time 532661287810 ps
CPU time 495.52 seconds
Started Apr 23 02:29:32 PM PDT 24
Finished Apr 23 02:37:48 PM PDT 24
Peak memory 202296 kb
Host smart-75d62ad9-ef16-4409-a67d-8d5f91250947
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050175662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4050175662
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.601087024
Short name T290
Test name
Test status
Simulation time 492645082480 ps
CPU time 576.09 seconds
Started Apr 23 02:30:35 PM PDT 24
Finished Apr 23 02:40:12 PM PDT 24
Peak memory 202260 kb
Host smart-4c4ceef4-20ef-45d2-9bf3-2f94a9219bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601087024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.601087024
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2518791249
Short name T187
Test name
Test status
Simulation time 125448550530 ps
CPU time 559.55 seconds
Started Apr 23 02:31:09 PM PDT 24
Finished Apr 23 02:40:29 PM PDT 24
Peak memory 202624 kb
Host smart-2fdb8334-fe03-4091-8279-37fe00f5d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518791249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2518791249
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1335282505
Short name T320
Test name
Test status
Simulation time 491530663379 ps
CPU time 87.57 seconds
Started Apr 23 02:26:02 PM PDT 24
Finished Apr 23 02:27:31 PM PDT 24
Peak memory 202328 kb
Host smart-02170b0e-a3ae-48f6-b4e9-5371a7d89e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335282505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1335282505
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.484282822
Short name T258
Test name
Test status
Simulation time 194703855036 ps
CPU time 119.41 seconds
Started Apr 23 02:26:15 PM PDT 24
Finished Apr 23 02:28:15 PM PDT 24
Peak memory 202212 kb
Host smart-c40e69f6-f56c-4326-b2b9-de6419a9c039
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484282822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.484282822
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3938792406
Short name T105
Test name
Test status
Simulation time 1196380557 ps
CPU time 2.89 seconds
Started Apr 23 02:25:12 PM PDT 24
Finished Apr 23 02:25:15 PM PDT 24
Peak memory 201456 kb
Host smart-00abc276-ec0b-4b1b-bdfd-416bcf106613
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938792406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3938792406
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1760460984
Short name T872
Test name
Test status
Simulation time 26635036267 ps
CPU time 17.3 seconds
Started Apr 23 02:25:11 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201468 kb
Host smart-94dcb86d-e68b-4a93-aa40-744335afd81c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760460984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1760460984
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2441344846
Short name T103
Test name
Test status
Simulation time 1268354315 ps
CPU time 3.57 seconds
Started Apr 23 02:25:09 PM PDT 24
Finished Apr 23 02:25:13 PM PDT 24
Peak memory 201208 kb
Host smart-3a7d925d-0543-4852-931a-21dd25fb7945
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441344846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2441344846
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1912773100
Short name T74
Test name
Test status
Simulation time 530456499 ps
CPU time 1.64 seconds
Started Apr 23 02:25:09 PM PDT 24
Finished Apr 23 02:25:11 PM PDT 24
Peak memory 201324 kb
Host smart-d4496911-eb5e-434c-92c3-0d65a1f38738
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912773100 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1912773100
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2054036200
Short name T875
Test name
Test status
Simulation time 439659954 ps
CPU time 1.35 seconds
Started Apr 23 02:25:11 PM PDT 24
Finished Apr 23 02:25:13 PM PDT 24
Peak memory 201224 kb
Host smart-aa2a89d8-ee3d-466c-9eb8-267eda862ee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054036200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2054036200
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2872147478
Short name T799
Test name
Test status
Simulation time 553559861 ps
CPU time 0.98 seconds
Started Apr 23 02:25:10 PM PDT 24
Finished Apr 23 02:25:12 PM PDT 24
Peak memory 201220 kb
Host smart-ab9e0d9b-fe30-4f7f-9317-61d5974da13c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872147478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2872147478
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1843803963
Short name T117
Test name
Test status
Simulation time 4667376968 ps
CPU time 2.85 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:52 PM PDT 24
Peak memory 201228 kb
Host smart-9baed24b-7c29-4561-893a-987e2710bcaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843803963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1843803963
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1028873786
Short name T906
Test name
Test status
Simulation time 477580123 ps
CPU time 3.58 seconds
Started Apr 23 02:25:12 PM PDT 24
Finished Apr 23 02:25:16 PM PDT 24
Peak memory 217860 kb
Host smart-d17e220d-1418-4e09-bbb2-fb4b76eaa29d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028873786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1028873786
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1410530484
Short name T828
Test name
Test status
Simulation time 8580235443 ps
CPU time 23.09 seconds
Started Apr 23 02:25:10 PM PDT 24
Finished Apr 23 02:25:34 PM PDT 24
Peak memory 201532 kb
Host smart-49358a35-9714-499d-86fd-4ef7b4a2d1de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410530484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1410530484
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3083671621
Short name T109
Test name
Test status
Simulation time 984475289 ps
CPU time 3.44 seconds
Started Apr 23 02:25:08 PM PDT 24
Finished Apr 23 02:25:12 PM PDT 24
Peak memory 201372 kb
Host smart-2beeb4fd-83c3-4731-a1d5-36faf8eb7a12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083671621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3083671621
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.973974963
Short name T108
Test name
Test status
Simulation time 26495532670 ps
CPU time 42.78 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:56 PM PDT 24
Peak memory 201440 kb
Host smart-e983b201-54ca-432a-8aa1-731669265533
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973974963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.973974963
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3204002149
Short name T835
Test name
Test status
Simulation time 658730024 ps
CPU time 2.22 seconds
Started Apr 23 02:25:08 PM PDT 24
Finished Apr 23 02:25:11 PM PDT 24
Peak memory 201204 kb
Host smart-021a9a0a-8703-41cc-b919-5c8234b73846
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204002149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3204002149
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3055879454
Short name T919
Test name
Test status
Simulation time 457533478 ps
CPU time 1.01 seconds
Started Apr 23 02:25:14 PM PDT 24
Finished Apr 23 02:25:16 PM PDT 24
Peak memory 201264 kb
Host smart-149293ab-0cb9-41e7-be7e-b9ae21845d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055879454 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3055879454
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3152298676
Short name T855
Test name
Test status
Simulation time 409083649 ps
CPU time 0.91 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:50 PM PDT 24
Peak memory 200992 kb
Host smart-50277826-b18e-48f9-a48f-3943beed8d42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152298676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3152298676
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.951393246
Short name T814
Test name
Test status
Simulation time 474718663 ps
CPU time 0.89 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:14 PM PDT 24
Peak memory 201216 kb
Host smart-3da8b598-90bc-4993-8b98-42ea6e161890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951393246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.951393246
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.155971361
Short name T844
Test name
Test status
Simulation time 4849532271 ps
CPU time 10.19 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:25:27 PM PDT 24
Peak memory 201496 kb
Host smart-1b964eba-f38f-4c06-bed8-ed13bf635feb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155971361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.155971361
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2751550918
Short name T868
Test name
Test status
Simulation time 760896069 ps
CPU time 1.98 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:51 PM PDT 24
Peak memory 201276 kb
Host smart-736152ce-b77b-4525-ae7c-331ff92fb825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751550918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2751550918
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.824856792
Short name T830
Test name
Test status
Simulation time 8927630216 ps
CPU time 7.36 seconds
Started Apr 23 02:25:10 PM PDT 24
Finished Apr 23 02:25:18 PM PDT 24
Peak memory 201496 kb
Host smart-29c82349-5671-4009-816c-6095004dc2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824856792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.824856792
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1379840517
Short name T876
Test name
Test status
Simulation time 488698138 ps
CPU time 2.08 seconds
Started Apr 23 02:25:25 PM PDT 24
Finished Apr 23 02:25:27 PM PDT 24
Peak memory 201276 kb
Host smart-cd2cbc04-48d7-4917-bd6c-1d2657548601
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379840517 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1379840517
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4121371826
Short name T867
Test name
Test status
Simulation time 531356403 ps
CPU time 1.82 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:20 PM PDT 24
Peak memory 201232 kb
Host smart-7c01bc4e-5c86-48d7-abc0-df71d1becfc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121371826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4121371826
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3098960352
Short name T808
Test name
Test status
Simulation time 371471105 ps
CPU time 1.01 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:20 PM PDT 24
Peak memory 201264 kb
Host smart-ece5f3b7-0f7f-48d4-b876-d9654983c274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098960352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3098960352
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2547796417
Short name T115
Test name
Test status
Simulation time 4914569605 ps
CPU time 12.77 seconds
Started Apr 23 02:25:21 PM PDT 24
Finished Apr 23 02:25:35 PM PDT 24
Peak memory 201444 kb
Host smart-14e25235-5219-4f83-be4c-16fc0f9121a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547796417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2547796417
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3182259405
Short name T73
Test name
Test status
Simulation time 605507824 ps
CPU time 1.65 seconds
Started Apr 23 02:25:48 PM PDT 24
Finished Apr 23 02:25:51 PM PDT 24
Peak memory 201248 kb
Host smart-6ee6fe67-ceac-4908-a96e-4cc493f33352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182259405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3182259405
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3850742298
Short name T879
Test name
Test status
Simulation time 8540634070 ps
CPU time 20.23 seconds
Started Apr 23 02:25:22 PM PDT 24
Finished Apr 23 02:25:43 PM PDT 24
Peak memory 201428 kb
Host smart-b10c0aee-7965-41ac-9849-994d84b322d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850742298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3850742298
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4137420133
Short name T909
Test name
Test status
Simulation time 375792691 ps
CPU time 1.81 seconds
Started Apr 23 02:25:23 PM PDT 24
Finished Apr 23 02:25:25 PM PDT 24
Peak memory 201292 kb
Host smart-b60ae3c7-b0a5-4a0c-96a3-ad1affee8e77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137420133 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4137420133
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1710007920
Short name T106
Test name
Test status
Simulation time 405378916 ps
CPU time 1.68 seconds
Started Apr 23 02:25:20 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201252 kb
Host smart-99a4d7e6-2e9c-46fc-a6b9-a3c680c37f35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710007920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1710007920
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1943883582
Short name T916
Test name
Test status
Simulation time 474195024 ps
CPU time 1.67 seconds
Started Apr 23 02:25:23 PM PDT 24
Finished Apr 23 02:25:25 PM PDT 24
Peak memory 201220 kb
Host smart-088e2534-1afe-4cda-86fb-f227a4c7c801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943883582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1943883582
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4165720401
Short name T823
Test name
Test status
Simulation time 2617035013 ps
CPU time 2.9 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201280 kb
Host smart-970d6663-81b3-4434-b5c0-3845192f2523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165720401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4165720401
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.985837595
Short name T907
Test name
Test status
Simulation time 517874971 ps
CPU time 1.73 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201476 kb
Host smart-64c6eeb1-7587-4134-a345-2c42c2e4b531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985837595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.985837595
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2647956469
Short name T917
Test name
Test status
Simulation time 7946818491 ps
CPU time 22.23 seconds
Started Apr 23 02:25:23 PM PDT 24
Finished Apr 23 02:25:46 PM PDT 24
Peak memory 201500 kb
Host smart-917bb696-7f75-4e5d-b4a4-e122c0f370d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647956469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2647956469
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3725683149
Short name T850
Test name
Test status
Simulation time 1091117610 ps
CPU time 1.11 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201232 kb
Host smart-329ca8d1-dd45-4e7b-b34c-cbcaf2a14be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725683149 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3725683149
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2712463465
Short name T885
Test name
Test status
Simulation time 675776307 ps
CPU time 0.81 seconds
Started Apr 23 02:25:22 PM PDT 24
Finished Apr 23 02:25:23 PM PDT 24
Peak memory 201224 kb
Host smart-612bf8fa-5864-48ba-8dc8-d42cbc90c272
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712463465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2712463465
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3250639742
Short name T836
Test name
Test status
Simulation time 360666708 ps
CPU time 1.48 seconds
Started Apr 23 02:25:24 PM PDT 24
Finished Apr 23 02:25:26 PM PDT 24
Peak memory 201232 kb
Host smart-9284e6c4-7fbb-40df-8b5b-20f9998f7d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250639742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3250639742
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3388574244
Short name T818
Test name
Test status
Simulation time 5409412442 ps
CPU time 9.92 seconds
Started Apr 23 02:25:22 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201408 kb
Host smart-e1775396-7d3d-444a-9094-dc6f3649a79f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388574244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3388574244
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.353968509
Short name T816
Test name
Test status
Simulation time 4202611798 ps
CPU time 4.15 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201480 kb
Host smart-37e70bde-b9a2-4822-9fd9-3c0d4e77c4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353968509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.353968509
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2441917711
Short name T871
Test name
Test status
Simulation time 502843467 ps
CPU time 1.14 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201316 kb
Host smart-13803665-807a-4daa-b355-4a30153fa904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441917711 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2441917711
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.253018420
Short name T112
Test name
Test status
Simulation time 348990565 ps
CPU time 1.21 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201200 kb
Host smart-51603a6a-9903-4ec7-b08e-649134a6e2f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253018420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.253018420
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1998908944
Short name T910
Test name
Test status
Simulation time 507921143 ps
CPU time 1.89 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201200 kb
Host smart-a665f63f-f562-48ad-9625-13a54de1c83f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998908944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1998908944
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3399460258
Short name T54
Test name
Test status
Simulation time 4689509889 ps
CPU time 11.44 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:39 PM PDT 24
Peak memory 201468 kb
Host smart-9256279b-19e8-4a11-b237-a5bdba1abb1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399460258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3399460258
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.304379249
Short name T864
Test name
Test status
Simulation time 563289729 ps
CPU time 2.57 seconds
Started Apr 23 02:25:24 PM PDT 24
Finished Apr 23 02:25:27 PM PDT 24
Peak memory 217616 kb
Host smart-fc33cbea-2361-44bd-9d21-addeac5a98fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304379249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.304379249
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.102566313
Short name T822
Test name
Test status
Simulation time 8771392017 ps
CPU time 12.42 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201492 kb
Host smart-d9a44536-9e05-4aee-9bd0-87b26186f519
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102566313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.102566313
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1149728341
Short name T886
Test name
Test status
Simulation time 480671089 ps
CPU time 1.11 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201308 kb
Host smart-e7922176-9d89-4560-8319-1831fe390750
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149728341 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1149728341
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2803622803
Short name T891
Test name
Test status
Simulation time 391542388 ps
CPU time 1.23 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201240 kb
Host smart-9469a6db-7948-4dff-aff5-a841abfffd9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803622803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2803622803
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1211944097
Short name T817
Test name
Test status
Simulation time 635789055 ps
CPU time 0.7 seconds
Started Apr 23 02:25:21 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201224 kb
Host smart-c35c2c48-32be-4b99-acb8-c801d3b57b10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211944097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1211944097
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.810687390
Short name T869
Test name
Test status
Simulation time 3714442771 ps
CPU time 15.03 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:44 PM PDT 24
Peak memory 201392 kb
Host smart-15cec1c1-3e85-4593-a324-e648797a5456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810687390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.810687390
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1720113569
Short name T893
Test name
Test status
Simulation time 554945458 ps
CPU time 1.51 seconds
Started Apr 23 02:25:23 PM PDT 24
Finished Apr 23 02:25:25 PM PDT 24
Peak memory 201464 kb
Host smart-4c46d08b-87c5-4ca7-9dae-0fb73cc6e0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720113569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1720113569
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1737642095
Short name T86
Test name
Test status
Simulation time 437207293 ps
CPU time 1.34 seconds
Started Apr 23 02:25:25 PM PDT 24
Finished Apr 23 02:25:27 PM PDT 24
Peak memory 201296 kb
Host smart-b1859974-029f-45d9-ab39-f1827076efe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737642095 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1737642095
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.204944670
Short name T107
Test name
Test status
Simulation time 702364566 ps
CPU time 0.96 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201252 kb
Host smart-c94be207-4aa7-4266-8c04-8122becf5d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204944670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.204944670
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.791819266
Short name T820
Test name
Test status
Simulation time 290937494 ps
CPU time 1.11 seconds
Started Apr 23 02:25:23 PM PDT 24
Finished Apr 23 02:25:25 PM PDT 24
Peak memory 201172 kb
Host smart-be85d0ce-590d-417c-b0c6-627cba879b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791819266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.791819266
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3547330907
Short name T53
Test name
Test status
Simulation time 2208134945 ps
CPU time 3.17 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201280 kb
Host smart-8881b86b-548b-4456-913a-2d6e1a888a2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547330907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3547330907
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3063773301
Short name T70
Test name
Test status
Simulation time 432152206 ps
CPU time 1.5 seconds
Started Apr 23 02:25:26 PM PDT 24
Finished Apr 23 02:25:28 PM PDT 24
Peak memory 201560 kb
Host smart-a7a1fb08-83aa-4f53-b176-202f564868c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063773301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3063773301
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2190726098
Short name T57
Test name
Test status
Simulation time 4212568575 ps
CPU time 4.09 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201468 kb
Host smart-15fee88e-c445-4a40-8dfc-95a9a1f058c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190726098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2190726098
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3959356820
Short name T60
Test name
Test status
Simulation time 426846506 ps
CPU time 1.84 seconds
Started Apr 23 02:25:25 PM PDT 24
Finished Apr 23 02:25:28 PM PDT 24
Peak memory 201260 kb
Host smart-2fa7f35e-c072-460c-ae1d-ea6ee68558ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959356820 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3959356820
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1448066071
Short name T110
Test name
Test status
Simulation time 531084557 ps
CPU time 0.95 seconds
Started Apr 23 02:25:25 PM PDT 24
Finished Apr 23 02:25:26 PM PDT 24
Peak memory 201216 kb
Host smart-3da9f661-21c8-49b0-a8c0-99397aec93f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448066071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1448066071
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.585444932
Short name T810
Test name
Test status
Simulation time 384429342 ps
CPU time 1.55 seconds
Started Apr 23 02:25:26 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201228 kb
Host smart-1b967eef-a6f3-4883-82fa-c966c12a8358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585444932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.585444932
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2413366692
Short name T831
Test name
Test status
Simulation time 2255296367 ps
CPU time 5.87 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:34 PM PDT 24
Peak memory 201316 kb
Host smart-9e122d5a-0af9-44ea-8a98-197d60873cbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413366692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2413366692
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2829338302
Short name T898
Test name
Test status
Simulation time 666389164 ps
CPU time 1.68 seconds
Started Apr 23 02:25:26 PM PDT 24
Finished Apr 23 02:25:28 PM PDT 24
Peak memory 201524 kb
Host smart-d1826589-a9d2-4b76-bed7-c0a1580a26fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829338302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2829338302
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2367230066
Short name T833
Test name
Test status
Simulation time 4689645140 ps
CPU time 12.97 seconds
Started Apr 23 02:25:26 PM PDT 24
Finished Apr 23 02:25:41 PM PDT 24
Peak memory 201456 kb
Host smart-e8194253-d887-4a99-91fc-06f37bcdfc6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367230066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2367230066
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.756298830
Short name T865
Test name
Test status
Simulation time 392380176 ps
CPU time 1.08 seconds
Started Apr 23 02:25:26 PM PDT 24
Finished Apr 23 02:25:28 PM PDT 24
Peak memory 201336 kb
Host smart-cda09068-5c6e-4bb2-b783-f39955562e8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756298830 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.756298830
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3315964166
Short name T111
Test name
Test status
Simulation time 430180662 ps
CPU time 1.76 seconds
Started Apr 23 02:25:26 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201244 kb
Host smart-40900d49-b543-4b95-afab-bc8c157c4817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315964166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3315964166
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.161603766
Short name T849
Test name
Test status
Simulation time 526426182 ps
CPU time 0.9 seconds
Started Apr 23 02:25:24 PM PDT 24
Finished Apr 23 02:25:25 PM PDT 24
Peak memory 201248 kb
Host smart-a954b6e6-531e-4c54-9b48-5a316db455c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161603766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.161603766
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1169745696
Short name T860
Test name
Test status
Simulation time 2307041031 ps
CPU time 6.5 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:36 PM PDT 24
Peak memory 201284 kb
Host smart-eebfcf2b-6a38-4aa2-bfbe-d2e06156e322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169745696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1169745696
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3092010195
Short name T72
Test name
Test status
Simulation time 698046471 ps
CPU time 2.36 seconds
Started Apr 23 02:25:26 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201512 kb
Host smart-8b6d291c-4e8a-4107-95c1-0fe1c2046e08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092010195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3092010195
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1039674928
Short name T848
Test name
Test status
Simulation time 8978016553 ps
CPU time 5.13 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:34 PM PDT 24
Peak memory 201480 kb
Host smart-11522392-4386-4030-9dd1-39f97208713e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039674928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1039674928
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2291403228
Short name T859
Test name
Test status
Simulation time 547007887 ps
CPU time 1.46 seconds
Started Apr 23 02:25:30 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201412 kb
Host smart-bd8a3923-72b7-4ef5-9551-3b49e5e57d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291403228 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2291403228
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3538353698
Short name T901
Test name
Test status
Simulation time 443063650 ps
CPU time 1.06 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201244 kb
Host smart-7e672fab-5c33-403e-8a13-01fc9cbb9081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538353698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3538353698
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2209491915
Short name T877
Test name
Test status
Simulation time 529334829 ps
CPU time 0.93 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201248 kb
Host smart-e94815b3-0508-4530-8754-bc3e221f35c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209491915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2209491915
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.479898592
Short name T911
Test name
Test status
Simulation time 4369065379 ps
CPU time 9.58 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:39 PM PDT 24
Peak memory 201444 kb
Host smart-860344e7-a627-474c-95ca-e7db706f84c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479898592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.479898592
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3543535354
Short name T68
Test name
Test status
Simulation time 361837403 ps
CPU time 2.69 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201484 kb
Host smart-35a90b09-83a4-440f-a708-292a17ac252f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543535354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3543535354
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.4236684583
Short name T58
Test name
Test status
Simulation time 8791163004 ps
CPU time 6.15 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:36 PM PDT 24
Peak memory 201548 kb
Host smart-a0de7d53-1f8b-4232-8b9a-c1d96096d9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236684583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.4236684583
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.4049789212
Short name T75
Test name
Test status
Simulation time 676393941 ps
CPU time 1.38 seconds
Started Apr 23 02:25:30 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201304 kb
Host smart-2f02cc37-704b-4970-9009-fb54abfbafa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049789212 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.4049789212
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3640900551
Short name T829
Test name
Test status
Simulation time 375915765 ps
CPU time 1.18 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201240 kb
Host smart-2c282af0-b4e1-47e8-940a-3a4890c51b25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640900551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3640900551
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4114491228
Short name T796
Test name
Test status
Simulation time 463293809 ps
CPU time 0.87 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201180 kb
Host smart-c34afe27-3d41-4ad0-8982-780751e9352b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114491228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.4114491228
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2990430239
Short name T114
Test name
Test status
Simulation time 4174177648 ps
CPU time 2.97 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201444 kb
Host smart-ea187674-bf1c-4115-9fc1-ad296841177f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990430239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2990430239
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3472940025
Short name T902
Test name
Test status
Simulation time 4248421422 ps
CPU time 4.35 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:35 PM PDT 24
Peak memory 201476 kb
Host smart-32b85c0f-9d80-4fb4-bd76-5350a7e78125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472940025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3472940025
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.415295973
Short name T862
Test name
Test status
Simulation time 1352064214 ps
CPU time 2.81 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 201440 kb
Host smart-0cf9108b-055d-4967-9765-cb3028f545f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415295973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.415295973
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1217986746
Short name T894
Test name
Test status
Simulation time 799351753 ps
CPU time 1.13 seconds
Started Apr 23 02:25:11 PM PDT 24
Finished Apr 23 02:25:12 PM PDT 24
Peak memory 201224 kb
Host smart-ebd227b4-11b8-4512-bf8d-ea190ee24a50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217986746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1217986746
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.712642381
Short name T97
Test name
Test status
Simulation time 632756217 ps
CPU time 1.28 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:15 PM PDT 24
Peak memory 201292 kb
Host smart-cc9b9186-d951-4da4-b344-9f1acafbcff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712642381 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.712642381
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3647297766
Short name T821
Test name
Test status
Simulation time 345969030 ps
CPU time 1.11 seconds
Started Apr 23 02:25:12 PM PDT 24
Finished Apr 23 02:25:14 PM PDT 24
Peak memory 201260 kb
Host smart-3399ac56-dfc9-4eec-ad5d-44c8cb0e57d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647297766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3647297766
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.303760529
Short name T842
Test name
Test status
Simulation time 500356055 ps
CPU time 1.52 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:16 PM PDT 24
Peak memory 201264 kb
Host smart-b8fa2697-b01e-43b9-b7ff-3012dccc85c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303760529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.303760529
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.313296194
Short name T116
Test name
Test status
Simulation time 2140307127 ps
CPU time 4.66 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:18 PM PDT 24
Peak memory 201232 kb
Host smart-ac006be0-abc3-41ea-bb6a-2cd5be1cb891
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313296194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.313296194
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.52126509
Short name T873
Test name
Test status
Simulation time 605039699 ps
CPU time 4.1 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:23 PM PDT 24
Peak memory 210700 kb
Host smart-a7c9c961-9672-4888-b23e-31a4e2d47748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52126509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.52126509
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1900631208
Short name T69
Test name
Test status
Simulation time 8549776801 ps
CPU time 18.33 seconds
Started Apr 23 02:25:12 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201512 kb
Host smart-07573d70-f433-482e-946a-0a2eb90b0f83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900631208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1900631208
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1525162882
Short name T803
Test name
Test status
Simulation time 431315195 ps
CPU time 0.74 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201216 kb
Host smart-cc5383f0-d9af-464e-ac11-7c495c5bbd4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525162882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1525162882
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3783454520
Short name T863
Test name
Test status
Simulation time 521525929 ps
CPU time 1.85 seconds
Started Apr 23 02:25:25 PM PDT 24
Finished Apr 23 02:25:28 PM PDT 24
Peak memory 201204 kb
Host smart-c84ba5ff-9b42-4666-8014-fa01b60c8051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783454520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3783454520
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4260772673
Short name T806
Test name
Test status
Simulation time 509468137 ps
CPU time 0.88 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201256 kb
Host smart-30523796-4ca5-40f1-9012-6680d137b738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260772673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4260772673
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1638892755
Short name T880
Test name
Test status
Simulation time 374707941 ps
CPU time 0.89 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:30 PM PDT 24
Peak memory 201224 kb
Host smart-ce8af29a-6833-45ca-9708-fa7cdcb1529f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638892755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1638892755
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1684894394
Short name T870
Test name
Test status
Simulation time 540040146 ps
CPU time 1.22 seconds
Started Apr 23 02:25:27 PM PDT 24
Finished Apr 23 02:25:29 PM PDT 24
Peak memory 201232 kb
Host smart-decce83f-6047-4c0f-9c1c-8ef9a4b9b871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684894394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1684894394
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2095168640
Short name T914
Test name
Test status
Simulation time 425093853 ps
CPU time 1.22 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201240 kb
Host smart-f0308974-3dbe-4a2b-86a3-295c1d430f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095168640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2095168640
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2354152736
Short name T798
Test name
Test status
Simulation time 375387141 ps
CPU time 1.08 seconds
Started Apr 23 02:25:32 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201228 kb
Host smart-ff5a2a21-ec3b-43a8-9e98-83474f1b4575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354152736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2354152736
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1060360045
Short name T811
Test name
Test status
Simulation time 506971488 ps
CPU time 0.93 seconds
Started Apr 23 02:25:31 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201236 kb
Host smart-4e1f2050-a934-44db-8e05-fcfed1e51514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060360045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1060360045
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2798121821
Short name T805
Test name
Test status
Simulation time 389415363 ps
CPU time 1.5 seconds
Started Apr 23 02:25:30 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201236 kb
Host smart-2ceb153d-68d4-44c1-b8a8-db42b721b7ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798121821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2798121821
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3542222260
Short name T883
Test name
Test status
Simulation time 328345833 ps
CPU time 1.41 seconds
Started Apr 23 02:25:31 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201236 kb
Host smart-5aa284fb-4b5f-41c1-be16-d278a0fa4cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542222260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3542222260
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1274137461
Short name T101
Test name
Test status
Simulation time 774217916 ps
CPU time 4.84 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201424 kb
Host smart-e9d375dc-f618-4559-9786-7a039b122ba3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274137461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1274137461
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1419906976
Short name T881
Test name
Test status
Simulation time 40701601342 ps
CPU time 160.51 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:27:57 PM PDT 24
Peak memory 201492 kb
Host smart-20f392ff-b2e0-4cd9-acc2-a0005cda7c21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419906976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1419906976
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3149323992
Short name T904
Test name
Test status
Simulation time 897184609 ps
CPU time 2.68 seconds
Started Apr 23 02:25:12 PM PDT 24
Finished Apr 23 02:25:15 PM PDT 24
Peak memory 201200 kb
Host smart-6c88f9d7-5e74-4219-8a8d-3df225d064a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149323992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3149323992
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.122903486
Short name T825
Test name
Test status
Simulation time 538219272 ps
CPU time 1.45 seconds
Started Apr 23 02:25:17 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 201264 kb
Host smart-622a6a45-2362-4a5f-a5c0-e019f0bb3595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122903486 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.122903486
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1212917381
Short name T118
Test name
Test status
Simulation time 408815428 ps
CPU time 1.67 seconds
Started Apr 23 02:25:14 PM PDT 24
Finished Apr 23 02:25:16 PM PDT 24
Peak memory 201192 kb
Host smart-1d40972e-5c12-4b3e-a5b7-5a2bbc97eaf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212917381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1212917381
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1478428305
Short name T918
Test name
Test status
Simulation time 484636102 ps
CPU time 0.95 seconds
Started Apr 23 02:25:14 PM PDT 24
Finished Apr 23 02:25:16 PM PDT 24
Peak memory 201220 kb
Host smart-b35d45e1-7078-4e51-979f-6ae622655859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478428305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1478428305
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2351178407
Short name T900
Test name
Test status
Simulation time 2280596109 ps
CPU time 6.03 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:24 PM PDT 24
Peak memory 201312 kb
Host smart-1f2ae49c-a11b-486f-8686-35ccc0085b18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351178407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2351178407
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2456293136
Short name T858
Test name
Test status
Simulation time 478719332 ps
CPU time 1.83 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:15 PM PDT 24
Peak memory 201476 kb
Host smart-7624747f-3ee0-4838-bf2d-c5d61bf69116
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456293136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2456293136
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2781575286
Short name T908
Test name
Test status
Simulation time 8308498277 ps
CPU time 19.87 seconds
Started Apr 23 02:25:13 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201504 kb
Host smart-ebed605e-ea42-4ad5-8451-b1d9ac0f81f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781575286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2781575286
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2037479775
Short name T837
Test name
Test status
Simulation time 343464295 ps
CPU time 1.47 seconds
Started Apr 23 02:25:31 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201248 kb
Host smart-9abd4d40-6e1d-444a-92da-3dfa1e6c3fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037479775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2037479775
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1185165954
Short name T813
Test name
Test status
Simulation time 320146736 ps
CPU time 0.77 seconds
Started Apr 23 02:25:34 PM PDT 24
Finished Apr 23 02:25:35 PM PDT 24
Peak memory 201224 kb
Host smart-24e1cb4a-4518-4176-bdac-ab384cb313f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185165954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1185165954
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2886524007
Short name T801
Test name
Test status
Simulation time 559706289 ps
CPU time 0.76 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201176 kb
Host smart-af7bbffa-fdc0-46e3-b9dd-35f7de1a5e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886524007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2886524007
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1027812531
Short name T812
Test name
Test status
Simulation time 341994715 ps
CPU time 1.05 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201188 kb
Host smart-73a47692-4adc-49f8-a046-e1f05f41a495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027812531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1027812531
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2666456444
Short name T804
Test name
Test status
Simulation time 328901568 ps
CPU time 1.34 seconds
Started Apr 23 02:25:31 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201240 kb
Host smart-f310d867-c516-401b-9b6e-0a937eb63604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666456444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2666456444
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3954118852
Short name T882
Test name
Test status
Simulation time 317744791 ps
CPU time 1.36 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201244 kb
Host smart-1b2bd1e7-5a55-4745-8303-0f35022750d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954118852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3954118852
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1289228579
Short name T913
Test name
Test status
Simulation time 434345897 ps
CPU time 1.17 seconds
Started Apr 23 02:25:33 PM PDT 24
Finished Apr 23 02:25:35 PM PDT 24
Peak memory 201216 kb
Host smart-bff1ee5a-69c2-4eec-a3cd-dbb9d454bb26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289228579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1289228579
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2095834387
Short name T903
Test name
Test status
Simulation time 407087907 ps
CPU time 1.55 seconds
Started Apr 23 02:25:29 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201220 kb
Host smart-b9cd925b-96c6-473b-82ed-e8aaceb962e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095834387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2095834387
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3190989924
Short name T889
Test name
Test status
Simulation time 509815261 ps
CPU time 1.8 seconds
Started Apr 23 02:25:33 PM PDT 24
Finished Apr 23 02:25:35 PM PDT 24
Peak memory 201232 kb
Host smart-21726c70-ce4f-43a6-88b5-922bc9f3a7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190989924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3190989924
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3222979870
Short name T861
Test name
Test status
Simulation time 291743604 ps
CPU time 1.28 seconds
Started Apr 23 02:25:30 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201156 kb
Host smart-3e6396d5-8887-45fa-a615-a37c4ea51e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222979870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3222979870
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.939871255
Short name T840
Test name
Test status
Simulation time 1023160065 ps
CPU time 1.8 seconds
Started Apr 23 02:25:20 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201404 kb
Host smart-6645a04c-73dc-495d-83b9-bcf92ac6d303
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939871255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.939871255
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.912259072
Short name T866
Test name
Test status
Simulation time 6099256899 ps
CPU time 16.11 seconds
Started Apr 23 02:25:15 PM PDT 24
Finished Apr 23 02:25:32 PM PDT 24
Peak memory 201500 kb
Host smart-f808681a-5d24-4967-ab8b-2a055faa05f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912259072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.912259072
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4250269647
Short name T890
Test name
Test status
Simulation time 1157691347 ps
CPU time 2.69 seconds
Started Apr 23 02:25:15 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 201268 kb
Host smart-fc221696-b5c5-4a31-a47a-54fbf6f849b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250269647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4250269647
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.693526744
Short name T895
Test name
Test status
Simulation time 519967878 ps
CPU time 2.15 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 201296 kb
Host smart-959c81a3-0307-437f-b839-55ab8e9f05dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693526744 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.693526744
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3144035214
Short name T113
Test name
Test status
Simulation time 511880508 ps
CPU time 1.12 seconds
Started Apr 23 02:25:17 PM PDT 24
Finished Apr 23 02:25:18 PM PDT 24
Peak memory 201228 kb
Host smart-8d5ea338-a5d8-4fe7-bd86-fdc59846266f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144035214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3144035214
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.877351992
Short name T854
Test name
Test status
Simulation time 300024929 ps
CPU time 1.31 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 201240 kb
Host smart-f524a161-edec-4387-bca4-5f6047d11a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877351992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.877351992
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3165755707
Short name T819
Test name
Test status
Simulation time 2834507923 ps
CPU time 9.29 seconds
Started Apr 23 02:25:17 PM PDT 24
Finished Apr 23 02:25:26 PM PDT 24
Peak memory 201292 kb
Host smart-50e026a4-c1b8-4372-85e4-66882561d6a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165755707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3165755707
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3820362087
Short name T839
Test name
Test status
Simulation time 679198200 ps
CPU time 3.6 seconds
Started Apr 23 02:25:17 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 210660 kb
Host smart-6d856628-b6c5-4b6b-a33b-7c359b09f194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820362087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3820362087
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3327833556
Short name T897
Test name
Test status
Simulation time 279433705 ps
CPU time 1.21 seconds
Started Apr 23 02:25:28 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201196 kb
Host smart-674801cd-bfb3-4dc8-9e4d-c646a02d3bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327833556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3327833556
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2085659369
Short name T807
Test name
Test status
Simulation time 428463298 ps
CPU time 0.84 seconds
Started Apr 23 02:25:34 PM PDT 24
Finished Apr 23 02:25:36 PM PDT 24
Peak memory 201204 kb
Host smart-770fc3c8-944c-4fe5-86a2-67cdfa3109e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085659369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2085659369
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.646250231
Short name T834
Test name
Test status
Simulation time 354879951 ps
CPU time 1.06 seconds
Started Apr 23 02:25:31 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201264 kb
Host smart-bf32b5f7-cb5a-45c9-8355-8151e47f2627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646250231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.646250231
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2035995964
Short name T809
Test name
Test status
Simulation time 465716240 ps
CPU time 0.94 seconds
Started Apr 23 02:25:33 PM PDT 24
Finished Apr 23 02:25:34 PM PDT 24
Peak memory 201248 kb
Host smart-d56551f3-18ea-41ce-b08c-e19f6661e493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035995964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2035995964
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1961116798
Short name T845
Test name
Test status
Simulation time 389743912 ps
CPU time 1.05 seconds
Started Apr 23 02:25:32 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201240 kb
Host smart-70d43425-c9c3-4536-b471-1e65eaaba643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961116798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1961116798
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.563421780
Short name T815
Test name
Test status
Simulation time 406297438 ps
CPU time 1.13 seconds
Started Apr 23 02:25:35 PM PDT 24
Finished Apr 23 02:25:36 PM PDT 24
Peak memory 201208 kb
Host smart-7dd0d01a-fb5a-43cf-824b-708725c8da25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563421780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.563421780
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1244757044
Short name T826
Test name
Test status
Simulation time 350092679 ps
CPU time 1.44 seconds
Started Apr 23 02:25:35 PM PDT 24
Finished Apr 23 02:25:37 PM PDT 24
Peak memory 201184 kb
Host smart-39c5a30c-0f14-4e8a-aa65-54b720604f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244757044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1244757044
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3537091286
Short name T800
Test name
Test status
Simulation time 344865598 ps
CPU time 0.92 seconds
Started Apr 23 02:25:32 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201152 kb
Host smart-1ae13087-87ca-400b-b29b-b0a0ecfb50dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537091286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3537091286
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.164626476
Short name T838
Test name
Test status
Simulation time 414733404 ps
CPU time 0.82 seconds
Started Apr 23 02:25:33 PM PDT 24
Finished Apr 23 02:25:35 PM PDT 24
Peak memory 201268 kb
Host smart-339bccdc-916f-4866-984d-0a7bf39ece44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164626476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.164626476
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1005952209
Short name T851
Test name
Test status
Simulation time 453391981 ps
CPU time 1.77 seconds
Started Apr 23 02:25:34 PM PDT 24
Finished Apr 23 02:25:36 PM PDT 24
Peak memory 201216 kb
Host smart-7b220fd4-ad93-4829-9411-10525cb5d4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005952209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1005952209
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.242886130
Short name T824
Test name
Test status
Simulation time 559527781 ps
CPU time 1.53 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:25:18 PM PDT 24
Peak memory 201260 kb
Host smart-cd6bde1d-db35-45c1-b6f1-2e6f154683ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242886130 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.242886130
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4112244581
Short name T905
Test name
Test status
Simulation time 503241756 ps
CPU time 1.87 seconds
Started Apr 23 02:25:14 PM PDT 24
Finished Apr 23 02:25:17 PM PDT 24
Peak memory 201252 kb
Host smart-519a4011-c264-40c2-94bb-d67824de0e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112244581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4112244581
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.358159037
Short name T797
Test name
Test status
Simulation time 294768546 ps
CPU time 1.25 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:25:18 PM PDT 24
Peak memory 201200 kb
Host smart-7c482e0f-f827-4b4b-8875-580c6ddab329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358159037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.358159037
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.748528527
Short name T55
Test name
Test status
Simulation time 4574148176 ps
CPU time 18.71 seconds
Started Apr 23 02:25:14 PM PDT 24
Finished Apr 23 02:25:33 PM PDT 24
Peak memory 201396 kb
Host smart-b64e585e-44e1-4505-9b62-4fc2c0536d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748528527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.748528527
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2963206672
Short name T59
Test name
Test status
Simulation time 475222045 ps
CPU time 1.79 seconds
Started Apr 23 02:25:17 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 201488 kb
Host smart-3821b44c-3d5f-4d3d-bbd5-df5439d23a34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963206672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2963206672
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1088675462
Short name T887
Test name
Test status
Simulation time 4310412226 ps
CPU time 6.48 seconds
Started Apr 23 02:25:15 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201488 kb
Host smart-b6652ac9-f03d-46ee-a0b9-fe8a8d01c896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088675462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1088675462
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1903329231
Short name T896
Test name
Test status
Simulation time 571023126 ps
CPU time 1.59 seconds
Started Apr 23 02:25:21 PM PDT 24
Finished Apr 23 02:25:23 PM PDT 24
Peak memory 201224 kb
Host smart-759d90ca-d046-4124-b205-1af223937f6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903329231 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1903329231
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2483784111
Short name T857
Test name
Test status
Simulation time 490824871 ps
CPU time 1.8 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 201228 kb
Host smart-87b8f93d-0587-4d6d-a768-6e0290d6b7dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483784111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2483784111
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1830906181
Short name T802
Test name
Test status
Simulation time 478903193 ps
CPU time 1.74 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 201236 kb
Host smart-125fce3b-8879-4e95-af24-d2b10cdd6f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830906181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1830906181
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3917439421
Short name T843
Test name
Test status
Simulation time 4312324129 ps
CPU time 3.42 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:24 PM PDT 24
Peak memory 201448 kb
Host smart-7f2ae628-8363-4b38-815c-256cd4811372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917439421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3917439421
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.12918859
Short name T853
Test name
Test status
Simulation time 592017409 ps
CPU time 2.95 seconds
Started Apr 23 02:25:17 PM PDT 24
Finished Apr 23 02:25:20 PM PDT 24
Peak memory 217868 kb
Host smart-3e453f19-0c96-4801-9744-d1b25148378f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12918859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.12918859
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.143733167
Short name T339
Test name
Test status
Simulation time 4918329087 ps
CPU time 4.67 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:24 PM PDT 24
Peak memory 201436 kb
Host smart-f173cb19-0136-4efb-9361-1c72da863f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143733167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.143733167
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1115703137
Short name T65
Test name
Test status
Simulation time 498498354 ps
CPU time 1.08 seconds
Started Apr 23 02:25:16 PM PDT 24
Finished Apr 23 02:25:18 PM PDT 24
Peak memory 201308 kb
Host smart-5d2cab8a-f44f-4ae0-b301-e71c32be12f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115703137 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1115703137
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.764115605
Short name T912
Test name
Test status
Simulation time 363391088 ps
CPU time 1.64 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 201252 kb
Host smart-2252a838-f8bf-4655-b07d-3d821ec85156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764115605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.764115605
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1864927664
Short name T847
Test name
Test status
Simulation time 389534001 ps
CPU time 1.5 seconds
Started Apr 23 02:25:17 PM PDT 24
Finished Apr 23 02:25:19 PM PDT 24
Peak memory 201228 kb
Host smart-41917e9f-0bc2-4178-bfac-eb7c560f60f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864927664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1864927664
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3233534162
Short name T874
Test name
Test status
Simulation time 4403314558 ps
CPU time 2.6 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 201456 kb
Host smart-2b9ac2be-d085-4c7d-9342-5361091437f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233534162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3233534162
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.301865120
Short name T846
Test name
Test status
Simulation time 466922734 ps
CPU time 2.98 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201516 kb
Host smart-fd9752cc-ceee-45f8-8536-0f1254a9b625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301865120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.301865120
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1492747447
Short name T61
Test name
Test status
Simulation time 8235054692 ps
CPU time 7.89 seconds
Started Apr 23 02:25:23 PM PDT 24
Finished Apr 23 02:25:31 PM PDT 24
Peak memory 201468 kb
Host smart-f7717a49-4841-4298-bfff-efc8cd2ed723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492747447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1492747447
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2273883979
Short name T915
Test name
Test status
Simulation time 621453357 ps
CPU time 2.1 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201284 kb
Host smart-caa7e295-623d-47ab-a1eb-21dd878a113e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273883979 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2273883979
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3205505827
Short name T852
Test name
Test status
Simulation time 480444627 ps
CPU time 0.93 seconds
Started Apr 23 02:25:21 PM PDT 24
Finished Apr 23 02:25:23 PM PDT 24
Peak memory 201204 kb
Host smart-3830cb11-eb04-4534-87a1-ccec3390a78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205505827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3205505827
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2847600551
Short name T827
Test name
Test status
Simulation time 2205044682 ps
CPU time 2.22 seconds
Started Apr 23 02:25:20 PM PDT 24
Finished Apr 23 02:25:23 PM PDT 24
Peak memory 201316 kb
Host smart-7bd7f333-12d8-4030-ac3d-a67958db4772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847600551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2847600551
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3266025794
Short name T856
Test name
Test status
Simulation time 467293225 ps
CPU time 1.7 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 201500 kb
Host smart-0fd4f68f-4dea-457c-932d-7227358b17de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266025794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3266025794
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2412831250
Short name T884
Test name
Test status
Simulation time 4838343463 ps
CPU time 4.3 seconds
Started Apr 23 02:25:21 PM PDT 24
Finished Apr 23 02:25:26 PM PDT 24
Peak memory 201348 kb
Host smart-e2ca9a95-640a-4aac-8e25-5d8ba372ca85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412831250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2412831250
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1260091400
Short name T892
Test name
Test status
Simulation time 458829827 ps
CPU time 1.86 seconds
Started Apr 23 02:25:18 PM PDT 24
Finished Apr 23 02:25:20 PM PDT 24
Peak memory 201236 kb
Host smart-88186772-2c2c-4f54-9171-096cb1976df9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260091400 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1260091400
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1725054816
Short name T899
Test name
Test status
Simulation time 541694901 ps
CPU time 2.11 seconds
Started Apr 23 02:25:21 PM PDT 24
Finished Apr 23 02:25:24 PM PDT 24
Peak memory 201216 kb
Host smart-f45735bc-b862-4832-86d6-2677a5ac8a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725054816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1725054816
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3008383050
Short name T878
Test name
Test status
Simulation time 481588189 ps
CPU time 0.81 seconds
Started Apr 23 02:25:47 PM PDT 24
Finished Apr 23 02:25:48 PM PDT 24
Peak memory 201000 kb
Host smart-f10b20a6-e412-4951-a0b5-667a7f94674b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008383050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3008383050
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4108235261
Short name T888
Test name
Test status
Simulation time 2270325053 ps
CPU time 5.7 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:26 PM PDT 24
Peak memory 201308 kb
Host smart-1ee61f12-d907-4a9b-9abe-b1edde26c342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108235261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4108235261
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2362752394
Short name T67
Test name
Test status
Simulation time 699128289 ps
CPU time 1.78 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:21 PM PDT 24
Peak memory 201476 kb
Host smart-933d3063-06b1-4278-b32d-a0214130bdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362752394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2362752394
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3745871403
Short name T832
Test name
Test status
Simulation time 4820854767 ps
CPU time 2.62 seconds
Started Apr 23 02:25:19 PM PDT 24
Finished Apr 23 02:25:22 PM PDT 24
Peak memory 201452 kb
Host smart-bd7fb3ee-ed8a-416d-a32e-3dfd0647c09e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745871403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3745871403
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2457095321
Short name T689
Test name
Test status
Simulation time 341603946400 ps
CPU time 190.65 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:29:12 PM PDT 24
Peak memory 202276 kb
Host smart-36ee3210-c918-4d50-9139-b505c5d80680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457095321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2457095321
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2298224115
Short name T515
Test name
Test status
Simulation time 164355546809 ps
CPU time 98.08 seconds
Started Apr 23 02:25:54 PM PDT 24
Finished Apr 23 02:27:33 PM PDT 24
Peak memory 202172 kb
Host smart-e0c95189-29ec-4185-abc6-1fff0487bd29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298224115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2298224115
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2997071087
Short name T493
Test name
Test status
Simulation time 488768444713 ps
CPU time 525.7 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:34:39 PM PDT 24
Peak memory 202304 kb
Host smart-0ad0fa11-9f91-46e1-aaa2-268fae1e6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997071087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2997071087
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.614635252
Short name T681
Test name
Test status
Simulation time 163100740350 ps
CPU time 35.93 seconds
Started Apr 23 02:25:57 PM PDT 24
Finished Apr 23 02:26:33 PM PDT 24
Peak memory 202052 kb
Host smart-a16d35c7-7b50-4408-bb65-1fae1cfd15b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=614635252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.614635252
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3713804790
Short name T688
Test name
Test status
Simulation time 173872324441 ps
CPU time 203.82 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:29:25 PM PDT 24
Peak memory 202336 kb
Host smart-093f1349-72fb-48c1-bb25-c44c8e1e217e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713804790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3713804790
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1177575845
Short name T351
Test name
Test status
Simulation time 203444237296 ps
CPU time 445.44 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 202312 kb
Host smart-7f0a1b72-31b3-48b2-9e1d-d75fc5a59a93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177575845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1177575845
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3246876884
Short name T624
Test name
Test status
Simulation time 120011722481 ps
CPU time 481.42 seconds
Started Apr 23 02:25:57 PM PDT 24
Finished Apr 23 02:33:59 PM PDT 24
Peak memory 202580 kb
Host smart-ab7eeb34-dbcc-488b-b1db-c3c368ad0917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246876884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3246876884
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1598478608
Short name T668
Test name
Test status
Simulation time 45650924301 ps
CPU time 98.18 seconds
Started Apr 23 02:25:57 PM PDT 24
Finished Apr 23 02:27:36 PM PDT 24
Peak memory 202024 kb
Host smart-ca3435b5-e04e-48ad-a632-1d7f415259db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598478608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1598478608
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3781962273
Short name T691
Test name
Test status
Simulation time 3838903189 ps
CPU time 2.88 seconds
Started Apr 23 02:25:54 PM PDT 24
Finished Apr 23 02:25:58 PM PDT 24
Peak memory 202024 kb
Host smart-1c9a4038-0184-4979-a18e-ad98ba38f57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781962273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3781962273
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3361491851
Short name T764
Test name
Test status
Simulation time 5951745745 ps
CPU time 5.51 seconds
Started Apr 23 02:25:53 PM PDT 24
Finished Apr 23 02:25:59 PM PDT 24
Peak memory 202104 kb
Host smart-9b7a64b5-9b27-4672-b42d-dd281a018837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361491851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3361491851
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2841724072
Short name T240
Test name
Test status
Simulation time 362358646098 ps
CPU time 418.86 seconds
Started Apr 23 02:25:56 PM PDT 24
Finished Apr 23 02:32:56 PM PDT 24
Peak memory 202228 kb
Host smart-29d35c92-fc8a-4c68-9740-323f28352f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841724072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2841724072
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.495664133
Short name T790
Test name
Test status
Simulation time 425263088 ps
CPU time 0.84 seconds
Started Apr 23 02:25:57 PM PDT 24
Finished Apr 23 02:25:58 PM PDT 24
Peak memory 201912 kb
Host smart-c1d9486e-d204-4855-9d82-b94eaf41bd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495664133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.495664133
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2060493204
Short name T336
Test name
Test status
Simulation time 501714399473 ps
CPU time 232.19 seconds
Started Apr 23 02:25:59 PM PDT 24
Finished Apr 23 02:29:52 PM PDT 24
Peak memory 202276 kb
Host smart-4d940e67-0212-466c-af32-252447ce11ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060493204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2060493204
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3518535689
Short name T329
Test name
Test status
Simulation time 161186037037 ps
CPU time 104.59 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:27:46 PM PDT 24
Peak memory 202268 kb
Host smart-a569bea9-e0a3-4a3a-9dab-a4132d514591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518535689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3518535689
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1889322479
Short name T557
Test name
Test status
Simulation time 491424387084 ps
CPU time 291.94 seconds
Started Apr 23 02:25:59 PM PDT 24
Finished Apr 23 02:30:51 PM PDT 24
Peak memory 202232 kb
Host smart-0e98e5c9-331f-463e-8948-501537b3106a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889322479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1889322479
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2410758357
Short name T468
Test name
Test status
Simulation time 161359942327 ps
CPU time 180.75 seconds
Started Apr 23 02:25:57 PM PDT 24
Finished Apr 23 02:28:58 PM PDT 24
Peak memory 202264 kb
Host smart-c30e872b-fd73-4a77-b698-5d3f1a4d70dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410758357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2410758357
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1485787928
Short name T457
Test name
Test status
Simulation time 319606918552 ps
CPU time 379.26 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:32:21 PM PDT 24
Peak memory 202212 kb
Host smart-dfd4d635-086e-4b7c-b7ab-38e0289694c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485787928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1485787928
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1219558767
Short name T589
Test name
Test status
Simulation time 404086540783 ps
CPU time 455.1 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 202312 kb
Host smart-fbeb7daf-a367-4e68-bea6-bc77716b8420
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219558767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1219558767
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3869285447
Short name T199
Test name
Test status
Simulation time 72579418735 ps
CPU time 276.99 seconds
Started Apr 23 02:25:56 PM PDT 24
Finished Apr 23 02:30:34 PM PDT 24
Peak memory 202568 kb
Host smart-bbcf1f22-c327-4c57-87a5-9613b6c04ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869285447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3869285447
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1941568756
Short name T615
Test name
Test status
Simulation time 34270294805 ps
CPU time 21.12 seconds
Started Apr 23 02:25:59 PM PDT 24
Finished Apr 23 02:26:20 PM PDT 24
Peak memory 202084 kb
Host smart-b4fea284-961a-41bd-911a-81300d07a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941568756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1941568756
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1208339919
Short name T388
Test name
Test status
Simulation time 4656211941 ps
CPU time 3.35 seconds
Started Apr 23 02:25:55 PM PDT 24
Finished Apr 23 02:25:59 PM PDT 24
Peak memory 202024 kb
Host smart-6ca37173-ceda-4f68-bcbb-1f3e0ec61876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208339919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1208339919
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.268992637
Short name T77
Test name
Test status
Simulation time 7535425335 ps
CPU time 20.03 seconds
Started Apr 23 02:25:57 PM PDT 24
Finished Apr 23 02:26:17 PM PDT 24
Peak memory 218332 kb
Host smart-b0b37701-ab3a-4ebf-af4b-1b69c9479aea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268992637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.268992637
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3867750313
Short name T469
Test name
Test status
Simulation time 5992767152 ps
CPU time 4.31 seconds
Started Apr 23 02:25:54 PM PDT 24
Finished Apr 23 02:25:59 PM PDT 24
Peak memory 202092 kb
Host smart-d938f441-d5c8-44d4-aaf5-833f3102c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867750313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3867750313
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2112219874
Short name T629
Test name
Test status
Simulation time 404151526227 ps
CPU time 886.04 seconds
Started Apr 23 02:25:56 PM PDT 24
Finished Apr 23 02:40:43 PM PDT 24
Peak memory 202324 kb
Host smart-d2d6c435-b78f-4b83-b6e8-43aad54a2940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112219874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2112219874
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2979948411
Short name T253
Test name
Test status
Simulation time 91429426146 ps
CPU time 98.62 seconds
Started Apr 23 02:25:55 PM PDT 24
Finished Apr 23 02:27:34 PM PDT 24
Peak memory 211664 kb
Host smart-86ce1815-2737-4c03-bc29-f9a0117d9bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979948411 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2979948411
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3435992242
Short name T592
Test name
Test status
Simulation time 301018555 ps
CPU time 1.35 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:26:19 PM PDT 24
Peak memory 201964 kb
Host smart-5f5227e3-a397-4ae9-b3d3-8d7a56120019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435992242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3435992242
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2794240770
Short name T293
Test name
Test status
Simulation time 161658104622 ps
CPU time 95.88 seconds
Started Apr 23 02:26:15 PM PDT 24
Finished Apr 23 02:27:51 PM PDT 24
Peak memory 202156 kb
Host smart-351c5672-faff-4cdb-ab27-936eae693bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794240770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2794240770
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1078447532
Short name T250
Test name
Test status
Simulation time 487936835508 ps
CPU time 795.51 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:39:36 PM PDT 24
Peak memory 202276 kb
Host smart-a13f284c-f7c1-42a9-bd4f-3c1fd86548b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078447532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1078447532
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1630667684
Short name T466
Test name
Test status
Simulation time 500770883593 ps
CPU time 1238.99 seconds
Started Apr 23 02:26:11 PM PDT 24
Finished Apr 23 02:46:51 PM PDT 24
Peak memory 202224 kb
Host smart-0e2bb0dd-fac1-4567-9799-1d23bfb69302
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630667684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1630667684
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2750085214
Short name T410
Test name
Test status
Simulation time 496156941390 ps
CPU time 1137.53 seconds
Started Apr 23 02:26:11 PM PDT 24
Finished Apr 23 02:45:09 PM PDT 24
Peak memory 202316 kb
Host smart-05eb45f8-be1b-4e68-b3ac-421771f58f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750085214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2750085214
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.25594872
Short name T651
Test name
Test status
Simulation time 501355303147 ps
CPU time 268.39 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:30:42 PM PDT 24
Peak memory 202316 kb
Host smart-b3207a4b-fedf-4773-9912-7f85ad11681e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=25594872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed
.25594872
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1728856512
Short name T237
Test name
Test status
Simulation time 640040413743 ps
CPU time 1471.61 seconds
Started Apr 23 02:26:16 PM PDT 24
Finished Apr 23 02:50:48 PM PDT 24
Peak memory 202272 kb
Host smart-9f08a660-588f-4d44-84e2-f71db7b764d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728856512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1728856512
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2324774508
Short name T389
Test name
Test status
Simulation time 414303375066 ps
CPU time 242.8 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:30:16 PM PDT 24
Peak memory 202196 kb
Host smart-21e1112a-3764-4ef6-a63e-cd5b871de955
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324774508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2324774508
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2780661703
Short name T503
Test name
Test status
Simulation time 133959628719 ps
CPU time 676.4 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:37:38 PM PDT 24
Peak memory 202512 kb
Host smart-0758d71b-914a-4dbb-9dd0-d3ecca0094d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780661703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2780661703
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3449200504
Short name T621
Test name
Test status
Simulation time 45928350950 ps
CPU time 50.58 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:27:12 PM PDT 24
Peak memory 202088 kb
Host smart-8f498f25-10dc-43ac-8e89-ad1a069bad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449200504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3449200504
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.200134397
Short name T636
Test name
Test status
Simulation time 3231901743 ps
CPU time 4.54 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:26:26 PM PDT 24
Peak memory 202044 kb
Host smart-b3a7d372-04ad-46d4-a585-25e45ad08f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200134397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.200134397
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1149756711
Short name T441
Test name
Test status
Simulation time 6218251501 ps
CPU time 2.44 seconds
Started Apr 23 02:26:14 PM PDT 24
Finished Apr 23 02:26:17 PM PDT 24
Peak memory 202080 kb
Host smart-d5de0cc9-88ae-437b-8038-94c520a31920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149756711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1149756711
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3844023003
Short name T263
Test name
Test status
Simulation time 386596068374 ps
CPU time 876.59 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:40:54 PM PDT 24
Peak memory 202280 kb
Host smart-de2ac397-dac6-4ae7-a38d-04c1638078b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844023003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3844023003
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2577082931
Short name T302
Test name
Test status
Simulation time 82640005803 ps
CPU time 188.85 seconds
Started Apr 23 02:26:16 PM PDT 24
Finished Apr 23 02:29:25 PM PDT 24
Peak memory 210876 kb
Host smart-bc299ff6-39a9-4e17-8f92-42eb45ce99a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577082931 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2577082931
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2296379383
Short name T590
Test name
Test status
Simulation time 419439779 ps
CPU time 0.69 seconds
Started Apr 23 02:26:16 PM PDT 24
Finished Apr 23 02:26:17 PM PDT 24
Peak memory 201960 kb
Host smart-ca96f84f-3162-4677-bd48-e7b3b2b5ae61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296379383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2296379383
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2738485958
Short name T134
Test name
Test status
Simulation time 328197234118 ps
CPU time 369.13 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:32:23 PM PDT 24
Peak memory 202208 kb
Host smart-986ed27d-9b7c-4546-aaca-146a55d2f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738485958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2738485958
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2654903927
Short name T398
Test name
Test status
Simulation time 166638120977 ps
CPU time 95.33 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:27:53 PM PDT 24
Peak memory 202212 kb
Host smart-3b2c5aff-e8a2-40a3-b778-f493c54b7427
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654903927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2654903927
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.995461590
Short name T613
Test name
Test status
Simulation time 335255572109 ps
CPU time 190.87 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:29:32 PM PDT 24
Peak memory 202280 kb
Host smart-6b833547-a4bc-4f82-8b99-15903828ef3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995461590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.995461590
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.695010125
Short name T392
Test name
Test status
Simulation time 167374186614 ps
CPU time 60.62 seconds
Started Apr 23 02:26:14 PM PDT 24
Finished Apr 23 02:27:15 PM PDT 24
Peak memory 202204 kb
Host smart-0e41f4b7-ca24-4ed5-b836-7c8337bb9e9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=695010125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.695010125
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1304255645
Short name T276
Test name
Test status
Simulation time 337455676471 ps
CPU time 228.21 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:30:07 PM PDT 24
Peak memory 202328 kb
Host smart-04ae42ee-0472-463c-8544-f2452b7fb8fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304255645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1304255645
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3888729497
Short name T645
Test name
Test status
Simulation time 395957089135 ps
CPU time 255.81 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:30:36 PM PDT 24
Peak memory 202164 kb
Host smart-68fe99f6-3d41-4dbe-9477-9d7708155564
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888729497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3888729497
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3422247531
Short name T697
Test name
Test status
Simulation time 87521850211 ps
CPU time 320.45 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:31:40 PM PDT 24
Peak memory 202536 kb
Host smart-70b7908a-568d-48d8-8f8e-8ec05a2fd146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422247531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3422247531
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2893343924
Short name T141
Test name
Test status
Simulation time 34672833644 ps
CPU time 77.77 seconds
Started Apr 23 02:26:14 PM PDT 24
Finished Apr 23 02:27:32 PM PDT 24
Peak memory 202072 kb
Host smart-fc61c1a3-3497-4e23-98bb-af3b6af8a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893343924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2893343924
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1872263570
Short name T680
Test name
Test status
Simulation time 5469351286 ps
CPU time 2.58 seconds
Started Apr 23 02:26:16 PM PDT 24
Finished Apr 23 02:26:19 PM PDT 24
Peak memory 202012 kb
Host smart-78382bf5-c479-4ab4-8a9c-578c04e23c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872263570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1872263570
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2132409360
Short name T635
Test name
Test status
Simulation time 5960407374 ps
CPU time 4.18 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:26:26 PM PDT 24
Peak memory 202076 kb
Host smart-42b94d0a-5117-4167-bc1e-b5a66673de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132409360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2132409360
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4131652954
Short name T752
Test name
Test status
Simulation time 286727052809 ps
CPU time 514.21 seconds
Started Apr 23 02:26:14 PM PDT 24
Finished Apr 23 02:34:49 PM PDT 24
Peak memory 210828 kb
Host smart-27d1b654-790b-4695-bf03-c05c72e90d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131652954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4131652954
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.544365830
Short name T787
Test name
Test status
Simulation time 146688724024 ps
CPU time 33.1 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:26:54 PM PDT 24
Peak memory 210520 kb
Host smart-204adf57-d1a0-4820-8cef-1e27de75289d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544365830 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.544365830
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2793780910
Short name T670
Test name
Test status
Simulation time 474379887 ps
CPU time 0.86 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:26:22 PM PDT 24
Peak memory 201912 kb
Host smart-b682e497-a989-4dcf-b460-42af4311c96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793780910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2793780910
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3158339114
Short name T701
Test name
Test status
Simulation time 370950946127 ps
CPU time 318.58 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:31:40 PM PDT 24
Peak memory 202192 kb
Host smart-e1f50f84-a896-42e2-84b3-1934d4607f2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158339114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3158339114
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3260965846
Short name T89
Test name
Test status
Simulation time 510041016938 ps
CPU time 584 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 202264 kb
Host smart-89106a2d-d89d-4ef5-83b7-05c0cda89c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260965846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3260965846
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.47956490
Short name T287
Test name
Test status
Simulation time 499126313787 ps
CPU time 580.81 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:36:02 PM PDT 24
Peak memory 202344 kb
Host smart-1553083e-7078-44ee-951d-4091ca81a89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47956490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.47956490
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.5994173
Short name T696
Test name
Test status
Simulation time 493323759432 ps
CPU time 314.54 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:31:36 PM PDT 24
Peak memory 202196 kb
Host smart-0066d23a-8ee1-4be0-9498-8b84c0aaa7ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=5994173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_
fixed.5994173
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2321625478
Short name T324
Test name
Test status
Simulation time 486366656125 ps
CPU time 1158.34 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:45:42 PM PDT 24
Peak memory 202192 kb
Host smart-c6c0086e-92df-458b-a621-886242389026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321625478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2321625478
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2134122753
Short name T516
Test name
Test status
Simulation time 161830676309 ps
CPU time 378.58 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:32:39 PM PDT 24
Peak memory 202240 kb
Host smart-23c54ba0-85a0-4e99-9676-97a493378bda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134122753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2134122753
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1425949981
Short name T169
Test name
Test status
Simulation time 530224832777 ps
CPU time 301.55 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:31:22 PM PDT 24
Peak memory 202256 kb
Host smart-1f9069d1-b523-4710-a75c-c90a30347cad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425949981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1425949981
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1757594564
Short name T471
Test name
Test status
Simulation time 205436384008 ps
CPU time 121.57 seconds
Started Apr 23 02:26:21 PM PDT 24
Finished Apr 23 02:28:24 PM PDT 24
Peak memory 202236 kb
Host smart-9d919090-a2e2-468c-8862-77d1fcc1d0b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757594564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1757594564
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1479468760
Short name T769
Test name
Test status
Simulation time 128743272108 ps
CPU time 487.19 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:34:28 PM PDT 24
Peak memory 202584 kb
Host smart-d6a7778a-ce09-43bc-88de-812d528de8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479468760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1479468760
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3358312540
Short name T712
Test name
Test status
Simulation time 44580747763 ps
CPU time 99.73 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:28:02 PM PDT 24
Peak memory 202064 kb
Host smart-0f06c6d2-b462-471a-bad7-d820df3ce6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358312540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3358312540
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1927244955
Short name T458
Test name
Test status
Simulation time 3625601324 ps
CPU time 2.9 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:26:25 PM PDT 24
Peak memory 202016 kb
Host smart-561cd7da-4164-4caf-8b1a-90e5e5e02555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927244955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1927244955
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1085127307
Short name T548
Test name
Test status
Simulation time 5868651536 ps
CPU time 1.93 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:26:21 PM PDT 24
Peak memory 202076 kb
Host smart-d305ac4c-ebd2-4d12-976e-78e311d7cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085127307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1085127307
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3031436234
Short name T520
Test name
Test status
Simulation time 168698058826 ps
CPU time 93.36 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:27:52 PM PDT 24
Peak memory 202244 kb
Host smart-df29885f-1494-40c7-a170-355010b26c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031436234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3031436234
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1912530056
Short name T137
Test name
Test status
Simulation time 117253391977 ps
CPU time 43.88 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:27:06 PM PDT 24
Peak memory 210572 kb
Host smart-f3efe0e4-df21-4a84-8caa-a2f0e1d4927a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912530056 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1912530056
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.284443962
Short name T536
Test name
Test status
Simulation time 292978019 ps
CPU time 1.25 seconds
Started Apr 23 02:26:21 PM PDT 24
Finished Apr 23 02:26:24 PM PDT 24
Peak memory 201828 kb
Host smart-2fdc04a2-cd27-477d-9fe7-c3e0aa55f298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284443962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.284443962
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1013320011
Short name T326
Test name
Test status
Simulation time 489047145692 ps
CPU time 606.65 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:36:29 PM PDT 24
Peak memory 202204 kb
Host smart-f911412e-9bf4-44bb-baec-65a17a3eeb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013320011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1013320011
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.242199064
Short name T576
Test name
Test status
Simulation time 321697606675 ps
CPU time 202.16 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:29:43 PM PDT 24
Peak memory 202248 kb
Host smart-bc91c2c5-03da-4889-8832-dff48c4363b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=242199064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.242199064
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1702067313
Short name T38
Test name
Test status
Simulation time 330326289070 ps
CPU time 353.37 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:32:14 PM PDT 24
Peak memory 202156 kb
Host smart-cac9cc47-c4c0-42fb-99c5-0778d99f3afb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702067313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1702067313
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.902753791
Short name T779
Test name
Test status
Simulation time 180650033178 ps
CPU time 430.39 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:33:31 PM PDT 24
Peak memory 202332 kb
Host smart-99dd52a9-06b5-4dbd-994f-5f854bf9f6e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902753791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.902753791
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2484674929
Short name T80
Test name
Test status
Simulation time 416649526671 ps
CPU time 937.12 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:42:00 PM PDT 24
Peak memory 202216 kb
Host smart-f8d3085a-db5d-439d-b480-a34115784a1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484674929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2484674929
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4288412102
Short name T665
Test name
Test status
Simulation time 76190133197 ps
CPU time 406.58 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:33:08 PM PDT 24
Peak memory 202532 kb
Host smart-18758540-912a-417d-bded-04212838e1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288412102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4288412102
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1766898922
Short name T676
Test name
Test status
Simulation time 24972691608 ps
CPU time 61.73 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:27:21 PM PDT 24
Peak memory 202040 kb
Host smart-7a753c55-9dc3-49f7-98f6-5ad0680a46a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766898922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1766898922
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3012055205
Short name T735
Test name
Test status
Simulation time 4364441662 ps
CPU time 2.05 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:26:23 PM PDT 24
Peak memory 202056 kb
Host smart-63eceb02-1190-48a1-9466-85bcc18835e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012055205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3012055205
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2163432171
Short name T683
Test name
Test status
Simulation time 5874239729 ps
CPU time 4.16 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:26:23 PM PDT 24
Peak memory 202056 kb
Host smart-ba98eeac-694f-436c-a572-c68cdb0e5993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163432171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2163432171
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.425922723
Short name T207
Test name
Test status
Simulation time 88982214616 ps
CPU time 196.59 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:29:36 PM PDT 24
Peak memory 210828 kb
Host smart-d519330b-9cad-4cac-8b0c-2b35d5b01a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425922723 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.425922723
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3074717781
Short name T396
Test name
Test status
Simulation time 306023578 ps
CPU time 1 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:26:22 PM PDT 24
Peak memory 201976 kb
Host smart-71ff2dee-13cb-4b95-9a92-6ea1ca785598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074717781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3074717781
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3044588213
Short name T222
Test name
Test status
Simulation time 352449810394 ps
CPU time 243.26 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:30:25 PM PDT 24
Peak memory 202220 kb
Host smart-c79d2871-9a40-4744-b8f8-a3e64e18614e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044588213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3044588213
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3502004101
Short name T317
Test name
Test status
Simulation time 167506939908 ps
CPU time 393.38 seconds
Started Apr 23 02:26:24 PM PDT 24
Finished Apr 23 02:32:58 PM PDT 24
Peak memory 202340 kb
Host smart-e13c904e-3151-4a9d-bc07-6b37aed718c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502004101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3502004101
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3670113358
Short name T612
Test name
Test status
Simulation time 502311215596 ps
CPU time 586.37 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:36:09 PM PDT 24
Peak memory 202348 kb
Host smart-b72269d1-7439-4745-9435-cf0b9ede20cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670113358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3670113358
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3099680552
Short name T374
Test name
Test status
Simulation time 498010635711 ps
CPU time 350.11 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:32:13 PM PDT 24
Peak memory 202176 kb
Host smart-bac12425-17db-45d0-b335-097a7578ae57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099680552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3099680552
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2751217730
Short name T524
Test name
Test status
Simulation time 494721294378 ps
CPU time 165.04 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:29:08 PM PDT 24
Peak memory 202184 kb
Host smart-3ddcf133-594d-485e-a120-49808cce55fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751217730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2751217730
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1653059367
Short name T363
Test name
Test status
Simulation time 165406265755 ps
CPU time 93.76 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:28:00 PM PDT 24
Peak memory 202292 kb
Host smart-b590be9e-1820-426a-89d4-7e79ed83cc05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653059367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1653059367
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2590668758
Short name T720
Test name
Test status
Simulation time 254581087059 ps
CPU time 300.68 seconds
Started Apr 23 02:26:19 PM PDT 24
Finished Apr 23 02:31:22 PM PDT 24
Peak memory 202272 kb
Host smart-58f37e47-64b8-43e2-8bb1-0289ea3274ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590668758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2590668758
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.207366361
Short name T512
Test name
Test status
Simulation time 608363514904 ps
CPU time 1371.61 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:49:18 PM PDT 24
Peak memory 202272 kb
Host smart-5edb028c-446a-46f3-8a6c-c0482be534a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207366361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.207366361
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.502101341
Short name T598
Test name
Test status
Simulation time 126017958502 ps
CPU time 495.77 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:34:38 PM PDT 24
Peak memory 202540 kb
Host smart-7f501381-dc88-4048-9fba-3da009f56c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502101341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.502101341
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1640798027
Short name T372
Test name
Test status
Simulation time 22596050584 ps
CPU time 24.92 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:26:47 PM PDT 24
Peak memory 202064 kb
Host smart-0381e8a3-325d-4196-b0ff-68748ca6caf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640798027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1640798027
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.4192646950
Short name T514
Test name
Test status
Simulation time 2862790323 ps
CPU time 4 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:26:27 PM PDT 24
Peak memory 202092 kb
Host smart-1b1457c1-914d-4dc1-b8fd-7c6975e9e921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192646950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.4192646950
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.290752599
Short name T406
Test name
Test status
Simulation time 5780555202 ps
CPU time 13.59 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:26:36 PM PDT 24
Peak memory 202044 kb
Host smart-169aa390-7687-4bc9-87d8-bc9bd33cd26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290752599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.290752599
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.352016320
Short name T573
Test name
Test status
Simulation time 159261567325 ps
CPU time 195.96 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:29:37 PM PDT 24
Peak memory 202312 kb
Host smart-aad94071-bd4a-4a7a-a317-12a0040a2e4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352016320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
352016320
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2811361121
Short name T446
Test name
Test status
Simulation time 508576058 ps
CPU time 1.75 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:26:25 PM PDT 24
Peak memory 202000 kb
Host smart-c7560985-471f-432e-9721-169dba86e85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811361121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2811361121
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3166502868
Short name T330
Test name
Test status
Simulation time 166013379706 ps
CPU time 182.06 seconds
Started Apr 23 02:26:24 PM PDT 24
Finished Apr 23 02:29:27 PM PDT 24
Peak memory 202400 kb
Host smart-1bfd6f8e-7bdc-43d2-a0ac-a00ead3a40bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166502868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3166502868
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1793436483
Short name T757
Test name
Test status
Simulation time 329130932467 ps
CPU time 660.1 seconds
Started Apr 23 02:26:24 PM PDT 24
Finished Apr 23 02:37:25 PM PDT 24
Peak memory 202392 kb
Host smart-0a616143-d30b-425d-8d00-73dff0f0acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793436483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1793436483
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1295428093
Short name T565
Test name
Test status
Simulation time 164767008246 ps
CPU time 101.22 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:28:05 PM PDT 24
Peak memory 202196 kb
Host smart-5c9a2487-c60c-4ef7-8871-c3e5c48e4600
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295428093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1295428093
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2693004573
Short name T684
Test name
Test status
Simulation time 322422653216 ps
CPU time 172.5 seconds
Started Apr 23 02:26:23 PM PDT 24
Finished Apr 23 02:29:16 PM PDT 24
Peak memory 202252 kb
Host smart-1c7d8f2f-5492-4160-bf5d-3f2b47fc82c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693004573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2693004573
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3293255910
Short name T521
Test name
Test status
Simulation time 590530874192 ps
CPU time 669.5 seconds
Started Apr 23 02:26:20 PM PDT 24
Finished Apr 23 02:37:31 PM PDT 24
Peak memory 202224 kb
Host smart-e6cc7131-7fde-49c9-9e46-511bae3218b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293255910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3293255910
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3041059184
Short name T193
Test name
Test status
Simulation time 108335262398 ps
CPU time 514.44 seconds
Started Apr 23 02:26:24 PM PDT 24
Finished Apr 23 02:34:58 PM PDT 24
Peak memory 202604 kb
Host smart-6dc60fbe-67f1-429b-a4b4-bb280e7b875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041059184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3041059184
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1949606594
Short name T751
Test name
Test status
Simulation time 37101799130 ps
CPU time 21.12 seconds
Started Apr 23 02:26:27 PM PDT 24
Finished Apr 23 02:26:49 PM PDT 24
Peak memory 202048 kb
Host smart-e9f973b8-25f5-49e8-a94d-faee003e8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949606594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1949606594
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3742391342
Short name T100
Test name
Test status
Simulation time 4412360207 ps
CPU time 10.92 seconds
Started Apr 23 02:26:30 PM PDT 24
Finished Apr 23 02:26:41 PM PDT 24
Peak memory 202020 kb
Host smart-d1e9a1c6-a276-4b65-b854-a676f1ff9510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742391342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3742391342
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.593556819
Short name T418
Test name
Test status
Simulation time 5991228955 ps
CPU time 16.09 seconds
Started Apr 23 02:26:21 PM PDT 24
Finished Apr 23 02:26:39 PM PDT 24
Peak memory 202024 kb
Host smart-3f537918-4802-4ea0-b161-7e8439506d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593556819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.593556819
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1565834484
Short name T335
Test name
Test status
Simulation time 305133134514 ps
CPU time 1016.33 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:43:23 PM PDT 24
Peak memory 210792 kb
Host smart-0ea435d0-f283-4d37-b3e9-4b9f92df0e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565834484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1565834484
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3834360458
Short name T185
Test name
Test status
Simulation time 45300286036 ps
CPU time 111.03 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:28:18 PM PDT 24
Peak memory 210956 kb
Host smart-f8476c19-f489-48fc-b948-d648f4854514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834360458 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3834360458
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.628507144
Short name T395
Test name
Test status
Simulation time 500266832 ps
CPU time 1.61 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:26:28 PM PDT 24
Peak memory 201940 kb
Host smart-aeab3857-4a6e-4b2f-a519-acb363124296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628507144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.628507144
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3397964169
Short name T543
Test name
Test status
Simulation time 166021131698 ps
CPU time 395.31 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:33:01 PM PDT 24
Peak memory 202248 kb
Host smart-7440165c-6cb7-4783-9879-ed4e7b9b94fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397964169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3397964169
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3577932829
Short name T616
Test name
Test status
Simulation time 163993628941 ps
CPU time 263.18 seconds
Started Apr 23 02:26:27 PM PDT 24
Finished Apr 23 02:30:50 PM PDT 24
Peak memory 202200 kb
Host smart-99e81340-bbdf-4656-ad53-110172dc40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577932829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3577932829
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1460683715
Short name T511
Test name
Test status
Simulation time 489690305282 ps
CPU time 323.22 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:31:47 PM PDT 24
Peak memory 202284 kb
Host smart-cca84adb-0271-4096-a57c-394e9933cf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460683715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1460683715
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2225803045
Short name T580
Test name
Test status
Simulation time 490537398639 ps
CPU time 1228.21 seconds
Started Apr 23 02:26:24 PM PDT 24
Finished Apr 23 02:46:52 PM PDT 24
Peak memory 202288 kb
Host smart-f5f65e30-e6d5-405a-8a93-5fccf1fde0a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225803045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2225803045
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.877952697
Short name T411
Test name
Test status
Simulation time 164095622707 ps
CPU time 340.62 seconds
Started Apr 23 02:26:23 PM PDT 24
Finished Apr 23 02:32:04 PM PDT 24
Peak memory 202240 kb
Host smart-1adff407-e6e0-4325-8647-17c17c427dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877952697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.877952697
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2077713569
Short name T599
Test name
Test status
Simulation time 166864042191 ps
CPU time 187.79 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:29:31 PM PDT 24
Peak memory 202228 kb
Host smart-3e66f2f8-dedb-4697-8025-20006d9421ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077713569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2077713569
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3385235138
Short name T281
Test name
Test status
Simulation time 347563435992 ps
CPU time 817.79 seconds
Started Apr 23 02:26:29 PM PDT 24
Finished Apr 23 02:40:08 PM PDT 24
Peak memory 202228 kb
Host smart-193aa66f-302a-499d-b13d-f6332dbbdcd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385235138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3385235138
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1063015967
Short name T625
Test name
Test status
Simulation time 387824681687 ps
CPU time 415.79 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:33:22 PM PDT 24
Peak memory 202332 kb
Host smart-4f0d1b03-2fe9-4532-9d45-53716f2addeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063015967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1063015967
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3437692993
Short name T404
Test name
Test status
Simulation time 65303270165 ps
CPU time 245.72 seconds
Started Apr 23 02:26:28 PM PDT 24
Finished Apr 23 02:30:34 PM PDT 24
Peak memory 202552 kb
Host smart-c1f7c760-e39f-4735-9916-56dc890b5e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437692993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3437692993
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1926654648
Short name T4
Test name
Test status
Simulation time 26443902895 ps
CPU time 31.41 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:26:57 PM PDT 24
Peak memory 202052 kb
Host smart-3e7b7562-c5c1-43a8-8ac1-da3b98eab83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926654648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1926654648
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.707050511
Short name T367
Test name
Test status
Simulation time 3136778076 ps
CPU time 7.81 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:26:34 PM PDT 24
Peak memory 202000 kb
Host smart-d15a9997-44c0-4599-9143-fd50f8424171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707050511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.707050511
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.392437475
Short name T542
Test name
Test status
Simulation time 5937132463 ps
CPU time 7.57 seconds
Started Apr 23 02:26:22 PM PDT 24
Finished Apr 23 02:26:31 PM PDT 24
Peak memory 202036 kb
Host smart-8f2aebd9-f69b-40cb-9ed1-1a8ec3f0cb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392437475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.392437475
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.468884494
Short name T22
Test name
Test status
Simulation time 97301026566 ps
CPU time 127.65 seconds
Started Apr 23 02:26:30 PM PDT 24
Finished Apr 23 02:28:38 PM PDT 24
Peak memory 210740 kb
Host smart-4f8abe4a-4a1c-4445-8758-12d732c16826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468884494 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.468884494
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.48055313
Short name T391
Test name
Test status
Simulation time 360250141 ps
CPU time 1.42 seconds
Started Apr 23 02:26:30 PM PDT 24
Finished Apr 23 02:26:32 PM PDT 24
Peak memory 201960 kb
Host smart-1c321c11-ba17-49dc-9698-ba743f164278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48055313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.48055313
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.39117203
Short name T295
Test name
Test status
Simulation time 209646807071 ps
CPU time 415.03 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:33:22 PM PDT 24
Peak memory 202332 kb
Host smart-972e5b51-d093-4d57-aa1e-1fee156d8bcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gatin
g.39117203
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3510523095
Short name T775
Test name
Test status
Simulation time 505804007670 ps
CPU time 1147.99 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:45:34 PM PDT 24
Peak memory 202236 kb
Host smart-b0c954c0-43bc-4f5d-bca4-c7feb4c5821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510523095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3510523095
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3051830584
Short name T633
Test name
Test status
Simulation time 166006334854 ps
CPU time 401.8 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:33:08 PM PDT 24
Peak memory 202308 kb
Host smart-3d6d3c2f-512b-46cb-bf9f-2d7db529c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051830584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3051830584
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.876247678
Short name T550
Test name
Test status
Simulation time 490886133671 ps
CPU time 281.58 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:31:07 PM PDT 24
Peak memory 202196 kb
Host smart-a5286403-376c-4f3f-960f-5ce954674761
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=876247678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.876247678
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3020436441
Short name T507
Test name
Test status
Simulation time 328173719059 ps
CPU time 53.72 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:27:19 PM PDT 24
Peak memory 202240 kb
Host smart-716a04b1-028a-4d0f-928c-92bf0b872d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020436441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3020436441
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.499135802
Short name T774
Test name
Test status
Simulation time 164963090389 ps
CPU time 345.63 seconds
Started Apr 23 02:26:27 PM PDT 24
Finished Apr 23 02:32:13 PM PDT 24
Peak memory 202204 kb
Host smart-d287ce46-9ba0-457a-bd2a-cb6ef0cf7c64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=499135802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.499135802
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.157528795
Short name T748
Test name
Test status
Simulation time 203503029452 ps
CPU time 245.02 seconds
Started Apr 23 02:26:25 PM PDT 24
Finished Apr 23 02:30:31 PM PDT 24
Peak memory 202284 kb
Host smart-4c98f67d-d9cb-4390-a33e-3f625426fb79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157528795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.157528795
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2641669112
Short name T785
Test name
Test status
Simulation time 600778045642 ps
CPU time 651.05 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:37:18 PM PDT 24
Peak memory 202184 kb
Host smart-8fb7dd1e-133d-449f-889b-7430461cf2f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641669112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2641669112
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.302217975
Short name T778
Test name
Test status
Simulation time 128579195734 ps
CPU time 663.36 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:37:30 PM PDT 24
Peak memory 202660 kb
Host smart-c7e6e0a9-bb64-4488-969f-86acf9aa47c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302217975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.302217975
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2654032871
Short name T139
Test name
Test status
Simulation time 37609996378 ps
CPU time 45.64 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:27:12 PM PDT 24
Peak memory 202084 kb
Host smart-5743af7d-8cd1-474c-b299-3594d41f2535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654032871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2654032871
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1181068497
Short name T449
Test name
Test status
Simulation time 3840467208 ps
CPU time 2.84 seconds
Started Apr 23 02:26:27 PM PDT 24
Finished Apr 23 02:26:30 PM PDT 24
Peak memory 201944 kb
Host smart-7b62cf5b-2d3e-43d9-8e47-1488f74b681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181068497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1181068497
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.94656619
Short name T377
Test name
Test status
Simulation time 6092138840 ps
CPU time 6.26 seconds
Started Apr 23 02:26:26 PM PDT 24
Finished Apr 23 02:26:33 PM PDT 24
Peak memory 202060 kb
Host smart-08fbad9b-a533-4f51-85a2-e62b71c9e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94656619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.94656619
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1110370318
Short name T249
Test name
Test status
Simulation time 340099222711 ps
CPU time 182.28 seconds
Started Apr 23 02:26:28 PM PDT 24
Finished Apr 23 02:29:31 PM PDT 24
Peak memory 202328 kb
Host smart-dd5453eb-241e-4c28-b7ec-2caff13433af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110370318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1110370318
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3727265797
Short name T414
Test name
Test status
Simulation time 319741274 ps
CPU time 0.76 seconds
Started Apr 23 02:26:32 PM PDT 24
Finished Apr 23 02:26:33 PM PDT 24
Peak memory 201996 kb
Host smart-82cdec3f-5e5c-4a2f-9cf4-e3cef51f0d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727265797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3727265797
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.640927010
Short name T603
Test name
Test status
Simulation time 487740765092 ps
CPU time 940.25 seconds
Started Apr 23 02:26:31 PM PDT 24
Finished Apr 23 02:42:12 PM PDT 24
Peak memory 202260 kb
Host smart-43a41df5-de16-47f8-91ee-7551bf893aa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640927010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.640927010
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1566203945
Short name T234
Test name
Test status
Simulation time 334401206440 ps
CPU time 810.27 seconds
Started Apr 23 02:26:31 PM PDT 24
Finished Apr 23 02:40:02 PM PDT 24
Peak memory 202272 kb
Host smart-78ad4d16-aa39-4edd-bf34-df8bc1ba6cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566203945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1566203945
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2614453293
Short name T652
Test name
Test status
Simulation time 165202289232 ps
CPU time 185.38 seconds
Started Apr 23 02:26:40 PM PDT 24
Finished Apr 23 02:29:46 PM PDT 24
Peak memory 202160 kb
Host smart-8201afb5-4f8f-4b8f-b5a9-c8c2db8f4bdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614453293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2614453293
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.53486275
Short name T130
Test name
Test status
Simulation time 493330863102 ps
CPU time 1060.19 seconds
Started Apr 23 02:26:30 PM PDT 24
Finished Apr 23 02:44:11 PM PDT 24
Peak memory 202264 kb
Host smart-e2b71e9f-bf83-4697-8bdf-dc71e5db2124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53486275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.53486275
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3331946943
Short name T561
Test name
Test status
Simulation time 493337328285 ps
CPU time 293.38 seconds
Started Apr 23 02:26:31 PM PDT 24
Finished Apr 23 02:31:24 PM PDT 24
Peak memory 202324 kb
Host smart-f211586b-4c70-4408-b280-e84e8f86d135
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331946943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3331946943
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.87565822
Short name T622
Test name
Test status
Simulation time 554857910277 ps
CPU time 1345.2 seconds
Started Apr 23 02:26:30 PM PDT 24
Finished Apr 23 02:48:56 PM PDT 24
Peak memory 202204 kb
Host smart-a9b92778-24ba-47f1-b58e-918860c83cdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87565822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_w
akeup.87565822
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3966500822
Short name T485
Test name
Test status
Simulation time 201081910016 ps
CPU time 221.23 seconds
Started Apr 23 02:26:28 PM PDT 24
Finished Apr 23 02:30:10 PM PDT 24
Peak memory 202192 kb
Host smart-5941c908-4340-4e97-bd1c-0a79e09d848d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966500822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3966500822
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1757054425
Short name T51
Test name
Test status
Simulation time 72701622746 ps
CPU time 382.85 seconds
Started Apr 23 02:26:34 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 202560 kb
Host smart-49b851a5-3bb7-4632-a784-bed7994d1027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757054425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1757054425
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2080290223
Short name T602
Test name
Test status
Simulation time 38441677166 ps
CPU time 22.33 seconds
Started Apr 23 02:26:39 PM PDT 24
Finished Apr 23 02:27:02 PM PDT 24
Peak memory 202088 kb
Host smart-c276173f-4387-446a-8a55-2d20e70dc62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080290223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2080290223
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3955003581
Short name T667
Test name
Test status
Simulation time 2844629302 ps
CPU time 7.6 seconds
Started Apr 23 02:26:33 PM PDT 24
Finished Apr 23 02:26:41 PM PDT 24
Peak memory 202060 kb
Host smart-c13af400-48f2-43f4-a0e4-6bade966a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955003581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3955003581
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3542846039
Short name T475
Test name
Test status
Simulation time 5990385645 ps
CPU time 10 seconds
Started Apr 23 02:26:29 PM PDT 24
Finished Apr 23 02:26:39 PM PDT 24
Peak memory 202052 kb
Host smart-354f2691-a582-4470-aa8f-7ad18d037d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542846039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3542846039
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.390276589
Short name T284
Test name
Test status
Simulation time 236078426122 ps
CPU time 599.98 seconds
Started Apr 23 02:26:33 PM PDT 24
Finished Apr 23 02:36:33 PM PDT 24
Peak memory 202184 kb
Host smart-e3a6dce1-153a-4baf-9aa5-5d44eedd0ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390276589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
390276589
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.984794072
Short name T617
Test name
Test status
Simulation time 533559926616 ps
CPU time 133.62 seconds
Started Apr 23 02:26:33 PM PDT 24
Finished Apr 23 02:28:47 PM PDT 24
Peak memory 210692 kb
Host smart-7d77004b-f201-4089-a30c-60e24ef8f3ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984794072 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.984794072
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3213018216
Short name T686
Test name
Test status
Simulation time 464565661 ps
CPU time 1.58 seconds
Started Apr 23 02:26:41 PM PDT 24
Finished Apr 23 02:26:43 PM PDT 24
Peak memory 201972 kb
Host smart-e88fb7b1-8ab9-41bf-b3cb-f57e169f321a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213018216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3213018216
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.216063970
Short name T272
Test name
Test status
Simulation time 490572878860 ps
CPU time 311.89 seconds
Started Apr 23 02:26:38 PM PDT 24
Finished Apr 23 02:31:50 PM PDT 24
Peak memory 202276 kb
Host smart-ab676b4c-68dc-4055-94f7-1a107c91d6fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216063970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.216063970
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2689973331
Short name T286
Test name
Test status
Simulation time 384608767571 ps
CPU time 480.07 seconds
Started Apr 23 02:26:38 PM PDT 24
Finished Apr 23 02:34:38 PM PDT 24
Peak memory 202272 kb
Host smart-19316745-9033-4bd1-8a16-4cb9a09697ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689973331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2689973331
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2595399833
Short name T181
Test name
Test status
Simulation time 160242869550 ps
CPU time 78.31 seconds
Started Apr 23 02:26:38 PM PDT 24
Finished Apr 23 02:27:57 PM PDT 24
Peak memory 202268 kb
Host smart-f99157f1-86d4-4576-9932-fc1e40ec3071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595399833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2595399833
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1706359869
Short name T420
Test name
Test status
Simulation time 158612929605 ps
CPU time 95.94 seconds
Started Apr 23 02:26:40 PM PDT 24
Finished Apr 23 02:28:16 PM PDT 24
Peak memory 202088 kb
Host smart-c2fb53ba-3c0b-44dd-b5a8-2805cf21fa27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706359869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1706359869
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.31219951
Short name T756
Test name
Test status
Simulation time 164311664194 ps
CPU time 97.47 seconds
Started Apr 23 02:26:38 PM PDT 24
Finished Apr 23 02:28:16 PM PDT 24
Peak memory 202220 kb
Host smart-ef187ce3-1f27-4201-a274-6c9a909a3a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31219951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.31219951
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.403899311
Short name T346
Test name
Test status
Simulation time 169897852817 ps
CPU time 404.89 seconds
Started Apr 23 02:26:39 PM PDT 24
Finished Apr 23 02:33:25 PM PDT 24
Peak memory 202340 kb
Host smart-1f8470b4-f503-4670-8fda-78e566aef443
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=403899311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.403899311
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3586484079
Short name T733
Test name
Test status
Simulation time 353368848904 ps
CPU time 169.93 seconds
Started Apr 23 02:26:37 PM PDT 24
Finished Apr 23 02:29:27 PM PDT 24
Peak memory 202252 kb
Host smart-0008e03b-9c8f-462f-8d9f-65adeaa9f0a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586484079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3586484079
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2688193461
Short name T510
Test name
Test status
Simulation time 204124456231 ps
CPU time 32.58 seconds
Started Apr 23 02:26:39 PM PDT 24
Finished Apr 23 02:27:12 PM PDT 24
Peak memory 202272 kb
Host smart-b21e639d-fd9d-40fd-89b2-af73451538b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688193461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2688193461
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3647574594
Short name T488
Test name
Test status
Simulation time 43659513096 ps
CPU time 35.93 seconds
Started Apr 23 02:26:38 PM PDT 24
Finished Apr 23 02:27:15 PM PDT 24
Peak memory 201984 kb
Host smart-b0ffb9fd-1f3b-46c9-9b46-31ccc9048fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647574594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3647574594
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1634505067
Short name T33
Test name
Test status
Simulation time 4935792357 ps
CPU time 11.23 seconds
Started Apr 23 02:26:39 PM PDT 24
Finished Apr 23 02:26:50 PM PDT 24
Peak memory 201936 kb
Host smart-be8b4a44-9354-4df5-ade8-a9bd9a5d3f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634505067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1634505067
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3108107403
Short name T126
Test name
Test status
Simulation time 6067024409 ps
CPU time 7.27 seconds
Started Apr 23 02:26:38 PM PDT 24
Finished Apr 23 02:26:45 PM PDT 24
Peak memory 202012 kb
Host smart-a9cfab66-84ec-4a2e-a8be-23e6d9482bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108107403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3108107403
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4124685281
Short name T309
Test name
Test status
Simulation time 361176719351 ps
CPU time 81.33 seconds
Started Apr 23 02:26:40 PM PDT 24
Finished Apr 23 02:28:02 PM PDT 24
Peak memory 202260 kb
Host smart-7f49ad3b-955d-4fa0-aa69-25f09870ae29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124685281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4124685281
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2521750198
Short name T745
Test name
Test status
Simulation time 475041524568 ps
CPU time 203.71 seconds
Started Apr 23 02:26:44 PM PDT 24
Finished Apr 23 02:30:08 PM PDT 24
Peak memory 210572 kb
Host smart-22943897-08dc-4fea-89b2-04c44f7f579f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521750198 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2521750198
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2357552022
Short name T370
Test name
Test status
Simulation time 483389081 ps
CPU time 0.91 seconds
Started Apr 23 02:25:58 PM PDT 24
Finished Apr 23 02:25:59 PM PDT 24
Peak memory 201936 kb
Host smart-29015e7d-4dc1-4d4a-91b4-89b02e979a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357552022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2357552022
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.496637776
Short name T124
Test name
Test status
Simulation time 325612687523 ps
CPU time 219.24 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:29:40 PM PDT 24
Peak memory 202112 kb
Host smart-aba7dcfe-d477-473a-b83b-9a5550183635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496637776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.496637776
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1202148954
Short name T736
Test name
Test status
Simulation time 158193436226 ps
CPU time 98.24 seconds
Started Apr 23 02:26:02 PM PDT 24
Finished Apr 23 02:27:41 PM PDT 24
Peak memory 202328 kb
Host smart-561fb21a-ce66-4db9-9c99-f72f8422bfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202148954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1202148954
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3980246030
Short name T749
Test name
Test status
Simulation time 335794302230 ps
CPU time 193.86 seconds
Started Apr 23 02:25:58 PM PDT 24
Finished Apr 23 02:29:12 PM PDT 24
Peak memory 202240 kb
Host smart-5b5c1f11-2bf6-44af-988a-74d91b0a63c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980246030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3980246030
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.946571303
Short name T504
Test name
Test status
Simulation time 328028706897 ps
CPU time 732.06 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:38:12 PM PDT 24
Peak memory 202324 kb
Host smart-1dad655b-225c-4e08-a91e-10722a44abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946571303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.946571303
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.997330173
Short name T528
Test name
Test status
Simulation time 163383354657 ps
CPU time 65.63 seconds
Started Apr 23 02:25:59 PM PDT 24
Finished Apr 23 02:27:05 PM PDT 24
Peak memory 202256 kb
Host smart-67208caf-881d-4c8b-bc88-f69c87ad166d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=997330173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.997330173
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2911007452
Short name T283
Test name
Test status
Simulation time 342613327161 ps
CPU time 190.18 seconds
Started Apr 23 02:25:59 PM PDT 24
Finished Apr 23 02:29:10 PM PDT 24
Peak memory 202288 kb
Host smart-f0f242ed-979c-4585-a2c0-b40abe4825a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911007452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2911007452
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2440402283
Short name T368
Test name
Test status
Simulation time 598938282706 ps
CPU time 1500.83 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:51:02 PM PDT 24
Peak memory 202080 kb
Host smart-90b7dacc-651c-4523-9178-bf52c90cb418
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440402283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2440402283
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3380983562
Short name T402
Test name
Test status
Simulation time 122887928047 ps
CPU time 584.69 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:35:47 PM PDT 24
Peak memory 202528 kb
Host smart-75fcb28e-bf5f-4bd0-8b13-9277fa7acb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380983562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3380983562
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.553162167
Short name T365
Test name
Test status
Simulation time 22115275356 ps
CPU time 13.84 seconds
Started Apr 23 02:25:59 PM PDT 24
Finished Apr 23 02:26:13 PM PDT 24
Peak memory 202060 kb
Host smart-bec67ae8-6bc2-4191-a5cd-470f2a9af1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553162167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.553162167
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.167484812
Short name T782
Test name
Test status
Simulation time 5400940901 ps
CPU time 3.88 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:26:05 PM PDT 24
Peak memory 202000 kb
Host smart-349173b2-f5ab-4f95-b500-971d4d48c652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167484812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.167484812
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3252471332
Short name T64
Test name
Test status
Simulation time 7782895501 ps
CPU time 19.86 seconds
Started Apr 23 02:26:02 PM PDT 24
Finished Apr 23 02:26:23 PM PDT 24
Peak memory 218896 kb
Host smart-55f345c3-f176-4e9a-971b-c80113cb49bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252471332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3252471332
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3350298736
Short name T789
Test name
Test status
Simulation time 5731470942 ps
CPU time 4.82 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:26:06 PM PDT 24
Peak memory 202072 kb
Host smart-f938b874-f750-4158-94f0-a32ed91f5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350298736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3350298736
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1361518720
Short name T586
Test name
Test status
Simulation time 128455739725 ps
CPU time 528.09 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:34:50 PM PDT 24
Peak memory 212256 kb
Host smart-1fbbd992-cf9c-4090-9830-6dcfa7893b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361518720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1361518720
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1512161105
Short name T337
Test name
Test status
Simulation time 752876680678 ps
CPU time 441.52 seconds
Started Apr 23 02:25:58 PM PDT 24
Finished Apr 23 02:33:20 PM PDT 24
Peak memory 210780 kb
Host smart-74fa5808-978d-4a5b-9a69-f5a0c00d89bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512161105 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1512161105
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1992849266
Short name T358
Test name
Test status
Simulation time 450148737 ps
CPU time 1.77 seconds
Started Apr 23 02:26:51 PM PDT 24
Finished Apr 23 02:26:53 PM PDT 24
Peak memory 201992 kb
Host smart-84b77f0e-ab2b-409b-8afa-400464c8f25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992849266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1992849266
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3167853054
Short name T265
Test name
Test status
Simulation time 195674860271 ps
CPU time 123.53 seconds
Started Apr 23 02:26:48 PM PDT 24
Finished Apr 23 02:28:52 PM PDT 24
Peak memory 202224 kb
Host smart-49690438-1114-4009-81ff-171d8235a0bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167853054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3167853054
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2540767022
Short name T79
Test name
Test status
Simulation time 187768110922 ps
CPU time 28.12 seconds
Started Apr 23 02:26:46 PM PDT 24
Finished Apr 23 02:27:15 PM PDT 24
Peak memory 202204 kb
Host smart-c84b8814-c48a-4889-8041-320de8328477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540767022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2540767022
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1282557417
Short name T716
Test name
Test status
Simulation time 495339177336 ps
CPU time 171.9 seconds
Started Apr 23 02:26:43 PM PDT 24
Finished Apr 23 02:29:35 PM PDT 24
Peak memory 202236 kb
Host smart-f7c0070e-9cb7-4e6a-9c4e-814eebbc4c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282557417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1282557417
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3724491910
Short name T264
Test name
Test status
Simulation time 492432245554 ps
CPU time 386.7 seconds
Started Apr 23 02:26:45 PM PDT 24
Finished Apr 23 02:33:12 PM PDT 24
Peak memory 202244 kb
Host smart-ba871f18-b934-4027-bd76-1c48ac85b546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724491910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3724491910
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.4096575771
Short name T644
Test name
Test status
Simulation time 505401043756 ps
CPU time 1221.62 seconds
Started Apr 23 02:26:44 PM PDT 24
Finished Apr 23 02:47:07 PM PDT 24
Peak memory 202344 kb
Host smart-e7de1000-da05-462d-96b9-14dd63b41a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096575771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.4096575771
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2828903882
Short name T704
Test name
Test status
Simulation time 326576435844 ps
CPU time 779.78 seconds
Started Apr 23 02:26:41 PM PDT 24
Finished Apr 23 02:39:42 PM PDT 24
Peak memory 202312 kb
Host smart-c8fc336f-857e-4019-9874-bc322ead641e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828903882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2828903882
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.963824409
Short name T44
Test name
Test status
Simulation time 425503879657 ps
CPU time 124.66 seconds
Started Apr 23 02:26:48 PM PDT 24
Finished Apr 23 02:28:53 PM PDT 24
Peak memory 202172 kb
Host smart-29d336cc-771a-4f59-ab81-024e407fb69e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963824409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.963824409
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.138818262
Short name T366
Test name
Test status
Simulation time 44208311359 ps
CPU time 27.02 seconds
Started Apr 23 02:26:44 PM PDT 24
Finished Apr 23 02:27:11 PM PDT 24
Peak memory 202012 kb
Host smart-9cd4a941-0786-42ae-873e-e413188c3235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138818262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.138818262
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1166025213
Short name T725
Test name
Test status
Simulation time 5324781978 ps
CPU time 12.75 seconds
Started Apr 23 02:26:46 PM PDT 24
Finished Apr 23 02:26:59 PM PDT 24
Peak memory 202020 kb
Host smart-147a99b5-6bc1-42c4-8f3c-10e587b969dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166025213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1166025213
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.988533729
Short name T138
Test name
Test status
Simulation time 5732434672 ps
CPU time 14.46 seconds
Started Apr 23 02:26:44 PM PDT 24
Finished Apr 23 02:26:59 PM PDT 24
Peak memory 202032 kb
Host smart-0bdd7702-c363-4d76-a632-37995e0d9ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988533729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.988533729
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.488242201
Short name T47
Test name
Test status
Simulation time 662222186067 ps
CPU time 227.85 seconds
Started Apr 23 02:26:48 PM PDT 24
Finished Apr 23 02:30:36 PM PDT 24
Peak memory 202264 kb
Host smart-e4f36439-2f99-46b1-9932-8c9a08a71579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488242201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
488242201
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.265095188
Short name T5
Test name
Test status
Simulation time 35297280863 ps
CPU time 104.53 seconds
Started Apr 23 02:26:45 PM PDT 24
Finished Apr 23 02:28:30 PM PDT 24
Peak memory 211108 kb
Host smart-e3fc79ec-5275-4e48-aab2-b30349df5657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265095188 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.265095188
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3586565513
Short name T582
Test name
Test status
Simulation time 426565147 ps
CPU time 0.9 seconds
Started Apr 23 02:26:52 PM PDT 24
Finished Apr 23 02:26:53 PM PDT 24
Peak memory 201984 kb
Host smart-c778b4b7-e75e-475d-8628-0e06ba1e3a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586565513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3586565513
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1478805377
Short name T738
Test name
Test status
Simulation time 328213374022 ps
CPU time 404.16 seconds
Started Apr 23 02:26:53 PM PDT 24
Finished Apr 23 02:33:37 PM PDT 24
Peak memory 202224 kb
Host smart-cb74d82b-52a8-418c-aa48-d54f255f01d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478805377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1478805377
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1585406497
Short name T313
Test name
Test status
Simulation time 323223303240 ps
CPU time 779.24 seconds
Started Apr 23 02:26:50 PM PDT 24
Finished Apr 23 02:39:49 PM PDT 24
Peak memory 202260 kb
Host smart-da7c74b1-9a24-40a9-a2b5-13671b343dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585406497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1585406497
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1425588100
Short name T483
Test name
Test status
Simulation time 163530724063 ps
CPU time 201.34 seconds
Started Apr 23 02:26:47 PM PDT 24
Finished Apr 23 02:30:09 PM PDT 24
Peak memory 202296 kb
Host smart-ed098e01-be87-4fbb-aa9f-7c16f74d89f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425588100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1425588100
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.376478314
Short name T742
Test name
Test status
Simulation time 329839470767 ps
CPU time 190.57 seconds
Started Apr 23 02:26:51 PM PDT 24
Finished Apr 23 02:30:02 PM PDT 24
Peak memory 202332 kb
Host smart-21e0e6d4-7c78-42f2-9302-abb3f69e7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376478314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.376478314
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3399041134
Short name T400
Test name
Test status
Simulation time 329450166654 ps
CPU time 206.95 seconds
Started Apr 23 02:26:52 PM PDT 24
Finished Apr 23 02:30:19 PM PDT 24
Peak memory 202208 kb
Host smart-0967518a-4856-4106-a120-af9482613826
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399041134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3399041134
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1066500742
Short name T292
Test name
Test status
Simulation time 575439898702 ps
CPU time 665.41 seconds
Started Apr 23 02:26:48 PM PDT 24
Finished Apr 23 02:37:54 PM PDT 24
Peak memory 202344 kb
Host smart-650392ac-f452-4b4f-ac4c-2be3e1d8b568
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066500742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1066500742
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1654395890
Short name T442
Test name
Test status
Simulation time 598643636007 ps
CPU time 607.09 seconds
Started Apr 23 02:26:54 PM PDT 24
Finished Apr 23 02:37:01 PM PDT 24
Peak memory 202256 kb
Host smart-d4e05e40-77f3-4ac2-b92a-2cfdd741e677
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654395890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1654395890
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3668667605
Short name T487
Test name
Test status
Simulation time 116911584437 ps
CPU time 676.1 seconds
Started Apr 23 02:26:53 PM PDT 24
Finished Apr 23 02:38:10 PM PDT 24
Peak memory 202568 kb
Host smart-0451f4f1-edfa-4b82-b485-b5acafdf01bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668667605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3668667605
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4018197369
Short name T473
Test name
Test status
Simulation time 45340066137 ps
CPU time 7.49 seconds
Started Apr 23 02:26:53 PM PDT 24
Finished Apr 23 02:27:01 PM PDT 24
Peak memory 202088 kb
Host smart-cbd1b7a9-9b7e-4b05-bf9b-b37ead8c0679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018197369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4018197369
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1809782429
Short name T623
Test name
Test status
Simulation time 2655253558 ps
CPU time 2.25 seconds
Started Apr 23 02:26:52 PM PDT 24
Finished Apr 23 02:26:55 PM PDT 24
Peak memory 202044 kb
Host smart-5af6a055-560b-456c-96e6-51d8d52fa815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809782429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1809782429
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1484684394
Short name T474
Test name
Test status
Simulation time 6047465679 ps
CPU time 14.8 seconds
Started Apr 23 02:26:49 PM PDT 24
Finished Apr 23 02:27:04 PM PDT 24
Peak memory 202056 kb
Host smart-eb496fd6-9c39-413e-9ccb-7bb998610492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484684394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1484684394
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3027580504
Short name T638
Test name
Test status
Simulation time 48715476540 ps
CPU time 60.6 seconds
Started Apr 23 02:26:50 PM PDT 24
Finished Apr 23 02:27:51 PM PDT 24
Peak memory 202076 kb
Host smart-1079793d-8fe0-4d44-b816-d19b1e502cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027580504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3027580504
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3782222380
Short name T451
Test name
Test status
Simulation time 389726080 ps
CPU time 0.65 seconds
Started Apr 23 02:26:56 PM PDT 24
Finished Apr 23 02:26:57 PM PDT 24
Peak memory 201976 kb
Host smart-d2b85340-409c-49af-bd56-9f0b77a9adb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782222380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3782222380
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2017369872
Short name T128
Test name
Test status
Simulation time 169870725946 ps
CPU time 62.15 seconds
Started Apr 23 02:26:53 PM PDT 24
Finished Apr 23 02:27:56 PM PDT 24
Peak memory 202280 kb
Host smart-32b58329-e6b8-4199-aea3-39d3d322153b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017369872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2017369872
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1153998955
Short name T737
Test name
Test status
Simulation time 182062866622 ps
CPU time 431.97 seconds
Started Apr 23 02:26:54 PM PDT 24
Finished Apr 23 02:34:06 PM PDT 24
Peak memory 202356 kb
Host smart-6a690006-2a25-4ec2-92a0-f9c17b383358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153998955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1153998955
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2153020594
Short name T460
Test name
Test status
Simulation time 331844607265 ps
CPU time 204.34 seconds
Started Apr 23 02:26:55 PM PDT 24
Finished Apr 23 02:30:19 PM PDT 24
Peak memory 202268 kb
Host smart-6a26b8d0-5877-4986-ae65-53572748a2bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153020594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2153020594
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.481487381
Short name T560
Test name
Test status
Simulation time 332127400639 ps
CPU time 399.5 seconds
Started Apr 23 02:26:53 PM PDT 24
Finished Apr 23 02:33:33 PM PDT 24
Peak memory 202232 kb
Host smart-02d9c411-180e-477e-8e1a-47d40881567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481487381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.481487381
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1279618227
Short name T730
Test name
Test status
Simulation time 326190707746 ps
CPU time 759.16 seconds
Started Apr 23 02:26:55 PM PDT 24
Finished Apr 23 02:39:35 PM PDT 24
Peak memory 202208 kb
Host smart-c32f8b34-058d-4059-bb9b-c9d2d390e506
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279618227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1279618227
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3303840791
Short name T523
Test name
Test status
Simulation time 564775121555 ps
CPU time 615.86 seconds
Started Apr 23 02:26:54 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 202340 kb
Host smart-4297d845-9b78-476a-9f85-db125f81166e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303840791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3303840791
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3539977088
Short name T648
Test name
Test status
Simulation time 400346942008 ps
CPU time 221.81 seconds
Started Apr 23 02:26:53 PM PDT 24
Finished Apr 23 02:30:36 PM PDT 24
Peak memory 202152 kb
Host smart-7aaaed8b-61b1-4677-b86b-558adb44d8df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539977088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3539977088
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.615424061
Short name T575
Test name
Test status
Simulation time 98068020881 ps
CPU time 370.49 seconds
Started Apr 23 02:26:56 PM PDT 24
Finished Apr 23 02:33:07 PM PDT 24
Peak memory 202580 kb
Host smart-bdb8cfb7-9eae-4434-9c2b-cdd0fb6651c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615424061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.615424061
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1816419255
Short name T662
Test name
Test status
Simulation time 23944001496 ps
CPU time 57.38 seconds
Started Apr 23 02:26:56 PM PDT 24
Finished Apr 23 02:27:54 PM PDT 24
Peak memory 202020 kb
Host smart-1022c096-98ad-48c1-8853-8395604f9887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816419255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1816419255
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3621129432
Short name T513
Test name
Test status
Simulation time 3675067535 ps
CPU time 3.02 seconds
Started Apr 23 02:26:55 PM PDT 24
Finished Apr 23 02:26:58 PM PDT 24
Peak memory 202020 kb
Host smart-6aea8eba-7c52-47b5-9515-a9d8fe13cc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621129432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3621129432
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.4116388793
Short name T379
Test name
Test status
Simulation time 5982806354 ps
CPU time 3.69 seconds
Started Apr 23 02:26:51 PM PDT 24
Finished Apr 23 02:26:55 PM PDT 24
Peak memory 202068 kb
Host smart-47cc3f3e-8e31-4bc8-bf8f-d9120cb536f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116388793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4116388793
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2103860762
Short name T554
Test name
Test status
Simulation time 338416148881 ps
CPU time 142.93 seconds
Started Apr 23 02:26:57 PM PDT 24
Finished Apr 23 02:29:20 PM PDT 24
Peak memory 202352 kb
Host smart-9a6e6d0d-5e2d-44ec-908e-38913888957f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103860762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2103860762
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2618854196
Short name T18
Test name
Test status
Simulation time 19137482183 ps
CPU time 68.89 seconds
Started Apr 23 02:26:56 PM PDT 24
Finished Apr 23 02:28:05 PM PDT 24
Peak memory 210868 kb
Host smart-a463132d-ebbf-49a7-ba17-3681c71152d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618854196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2618854196
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2177198252
Short name T443
Test name
Test status
Simulation time 493315313 ps
CPU time 0.74 seconds
Started Apr 23 02:27:04 PM PDT 24
Finished Apr 23 02:27:05 PM PDT 24
Peak memory 201976 kb
Host smart-6a52e958-4e52-41fd-bba6-031ce233da96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177198252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2177198252
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.465365239
Short name T254
Test name
Test status
Simulation time 373455428857 ps
CPU time 636.85 seconds
Started Apr 23 02:26:59 PM PDT 24
Finished Apr 23 02:37:37 PM PDT 24
Peak memory 202360 kb
Host smart-b448cef5-ef76-4596-8356-21d5728a6f65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465365239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.465365239
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3439807460
Short name T120
Test name
Test status
Simulation time 360306848184 ps
CPU time 330.95 seconds
Started Apr 23 02:26:58 PM PDT 24
Finished Apr 23 02:32:30 PM PDT 24
Peak memory 202272 kb
Host smart-e6c0489b-f9da-4c8e-ba22-b2171e03b202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439807460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3439807460
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.247376484
Short name T740
Test name
Test status
Simulation time 332125369454 ps
CPU time 85.12 seconds
Started Apr 23 02:26:58 PM PDT 24
Finished Apr 23 02:28:23 PM PDT 24
Peak memory 202268 kb
Host smart-737d59b1-8cee-403f-a5af-464be56697b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247376484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.247376484
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3841507314
Short name T131
Test name
Test status
Simulation time 162437383436 ps
CPU time 358.28 seconds
Started Apr 23 02:27:00 PM PDT 24
Finished Apr 23 02:32:58 PM PDT 24
Peak memory 202224 kb
Host smart-67815f46-efbb-4447-9bad-9b6b85168888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841507314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3841507314
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.994083509
Short name T438
Test name
Test status
Simulation time 329603294330 ps
CPU time 566.89 seconds
Started Apr 23 02:26:56 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 202308 kb
Host smart-815fca6a-d7ab-449b-b31b-bd7bcd8215c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=994083509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.994083509
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1608038297
Short name T776
Test name
Test status
Simulation time 427917715808 ps
CPU time 274.32 seconds
Started Apr 23 02:27:00 PM PDT 24
Finished Apr 23 02:31:35 PM PDT 24
Peak memory 202372 kb
Host smart-18aecb20-cfa0-4957-b9ff-8036f238eacb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608038297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1608038297
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3552635786
Short name T381
Test name
Test status
Simulation time 600822149603 ps
CPU time 363.6 seconds
Started Apr 23 02:26:59 PM PDT 24
Finished Apr 23 02:33:03 PM PDT 24
Peak memory 202124 kb
Host smart-0834d272-59a7-40ed-ba4f-a5014b411581
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552635786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3552635786
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2260671578
Short name T666
Test name
Test status
Simulation time 35809293767 ps
CPU time 5.82 seconds
Started Apr 23 02:26:59 PM PDT 24
Finished Apr 23 02:27:05 PM PDT 24
Peak memory 202088 kb
Host smart-e2f17104-ad05-417b-91e1-dc1ae0cc39e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260671578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2260671578
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3827047081
Short name T672
Test name
Test status
Simulation time 3743985475 ps
CPU time 9.03 seconds
Started Apr 23 02:26:59 PM PDT 24
Finished Apr 23 02:27:08 PM PDT 24
Peak memory 202052 kb
Host smart-2865b6b9-8105-4a2d-b955-9268075507b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827047081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3827047081
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.890043562
Short name T569
Test name
Test status
Simulation time 5842342191 ps
CPU time 4.17 seconds
Started Apr 23 02:26:59 PM PDT 24
Finished Apr 23 02:27:04 PM PDT 24
Peak memory 202056 kb
Host smart-f2a4e99c-f7bc-4b91-8384-e9039cb6d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890043562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.890043562
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.4128748174
Short name T305
Test name
Test status
Simulation time 608625531450 ps
CPU time 920.83 seconds
Started Apr 23 02:27:03 PM PDT 24
Finished Apr 23 02:42:24 PM PDT 24
Peak memory 202308 kb
Host smart-7371e95f-500a-4a03-bfd1-e82f08a5b0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128748174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.4128748174
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2225563618
Short name T708
Test name
Test status
Simulation time 169020191761 ps
CPU time 382.81 seconds
Started Apr 23 02:27:03 PM PDT 24
Finished Apr 23 02:33:26 PM PDT 24
Peak memory 219016 kb
Host smart-7cfd96ae-d7e8-41da-95b2-82a08cc63639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225563618 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2225563618
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1463286673
Short name T15
Test name
Test status
Simulation time 327976529 ps
CPU time 1.37 seconds
Started Apr 23 02:27:13 PM PDT 24
Finished Apr 23 02:27:14 PM PDT 24
Peak memory 201924 kb
Host smart-20024278-12db-4869-8a76-09b20d8c007a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463286673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1463286673
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2899836554
Short name T159
Test name
Test status
Simulation time 344925197892 ps
CPU time 98.2 seconds
Started Apr 23 02:27:08 PM PDT 24
Finished Apr 23 02:28:47 PM PDT 24
Peak memory 202128 kb
Host smart-40521210-75a6-4e4b-8d4c-17e67397e7bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899836554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2899836554
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1685797006
Short name T247
Test name
Test status
Simulation time 196252894492 ps
CPU time 234.35 seconds
Started Apr 23 02:27:09 PM PDT 24
Finished Apr 23 02:31:03 PM PDT 24
Peak memory 202276 kb
Host smart-40e5c4af-081e-4dc0-8316-b8343b24b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685797006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1685797006
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.621240923
Short name T732
Test name
Test status
Simulation time 163915798711 ps
CPU time 367.13 seconds
Started Apr 23 02:27:04 PM PDT 24
Finished Apr 23 02:33:12 PM PDT 24
Peak memory 202184 kb
Host smart-7629df55-b6df-45d3-966f-a1cb7bb45c4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=621240923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.621240923
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1867318091
Short name T226
Test name
Test status
Simulation time 330377239787 ps
CPU time 375.64 seconds
Started Apr 23 02:27:05 PM PDT 24
Finished Apr 23 02:33:21 PM PDT 24
Peak memory 202284 kb
Host smart-da8c72ec-ad43-4d22-bf7a-0718516edae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867318091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1867318091
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1943097411
Short name T540
Test name
Test status
Simulation time 164276353216 ps
CPU time 36.45 seconds
Started Apr 23 02:27:07 PM PDT 24
Finished Apr 23 02:27:43 PM PDT 24
Peak memory 202200 kb
Host smart-dde741d2-ccce-4344-a4b6-8a7f37994d0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943097411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1943097411
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1188645392
Short name T46
Test name
Test status
Simulation time 439574161713 ps
CPU time 1109.8 seconds
Started Apr 23 02:27:08 PM PDT 24
Finished Apr 23 02:45:38 PM PDT 24
Peak memory 202280 kb
Host smart-5e0b6979-e68f-4e95-8e33-c1aac8e559d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188645392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1188645392
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.424825091
Short name T759
Test name
Test status
Simulation time 194751441264 ps
CPU time 112.22 seconds
Started Apr 23 02:27:06 PM PDT 24
Finished Apr 23 02:28:59 PM PDT 24
Peak memory 202332 kb
Host smart-197c4ca6-af6c-4587-925e-6a52944626f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424825091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.424825091
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3989439425
Short name T566
Test name
Test status
Simulation time 125846051266 ps
CPU time 396.94 seconds
Started Apr 23 02:27:12 PM PDT 24
Finished Apr 23 02:33:49 PM PDT 24
Peak memory 202516 kb
Host smart-66d12ed7-77dd-4bf7-ae58-df0fab5d3d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989439425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3989439425
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3726674738
Short name T747
Test name
Test status
Simulation time 42788733725 ps
CPU time 89.85 seconds
Started Apr 23 02:27:11 PM PDT 24
Finished Apr 23 02:28:42 PM PDT 24
Peak memory 202092 kb
Host smart-4bc9f0db-e0f9-4925-8ef7-032e7e57fd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726674738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3726674738
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1895886486
Short name T352
Test name
Test status
Simulation time 4315229025 ps
CPU time 10.39 seconds
Started Apr 23 02:27:09 PM PDT 24
Finished Apr 23 02:27:19 PM PDT 24
Peak memory 202044 kb
Host smart-3a075a84-d55d-453b-9fef-8405fa4ff84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895886486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1895886486
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2441500031
Short name T479
Test name
Test status
Simulation time 5806176843 ps
CPU time 10.04 seconds
Started Apr 23 02:27:01 PM PDT 24
Finished Apr 23 02:27:12 PM PDT 24
Peak memory 202052 kb
Host smart-173e17c6-19d4-478d-acd1-2344b52a2c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441500031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2441500031
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3530508575
Short name T525
Test name
Test status
Simulation time 36432250358 ps
CPU time 90.15 seconds
Started Apr 23 02:27:12 PM PDT 24
Finished Apr 23 02:28:43 PM PDT 24
Peak memory 210528 kb
Host smart-9debe904-f1d7-4cf5-8d67-26a1f0df2683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530508575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3530508575
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2805406983
Short name T434
Test name
Test status
Simulation time 306525591 ps
CPU time 1.29 seconds
Started Apr 23 02:27:30 PM PDT 24
Finished Apr 23 02:27:32 PM PDT 24
Peak memory 201928 kb
Host smart-5ba71e37-e926-4ed5-8b40-7783501b6a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805406983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2805406983
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.4122714317
Short name T213
Test name
Test status
Simulation time 165198805960 ps
CPU time 375.04 seconds
Started Apr 23 02:27:24 PM PDT 24
Finished Apr 23 02:33:39 PM PDT 24
Peak memory 202316 kb
Host smart-3b1b624f-032f-4e9b-9c41-591f35ebb6e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122714317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.4122714317
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.222845013
Short name T563
Test name
Test status
Simulation time 538740927554 ps
CPU time 613.36 seconds
Started Apr 23 02:27:27 PM PDT 24
Finished Apr 23 02:37:41 PM PDT 24
Peak memory 202256 kb
Host smart-0a709fc6-07bb-49a5-8187-4f37eeb87631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222845013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.222845013
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3747273706
Short name T7
Test name
Test status
Simulation time 166793085251 ps
CPU time 55.95 seconds
Started Apr 23 02:27:20 PM PDT 24
Finished Apr 23 02:28:17 PM PDT 24
Peak memory 202228 kb
Host smart-6e49fff4-e7e8-4d4a-ad1a-c7e3f7a289d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747273706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3747273706
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3775204860
Short name T596
Test name
Test status
Simulation time 489633627405 ps
CPU time 583.28 seconds
Started Apr 23 02:27:19 PM PDT 24
Finished Apr 23 02:37:03 PM PDT 24
Peak memory 202196 kb
Host smart-1dade7db-f51a-44ad-871f-280d708d7478
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775204860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3775204860
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3226146802
Short name T711
Test name
Test status
Simulation time 156790456174 ps
CPU time 62.22 seconds
Started Apr 23 02:27:14 PM PDT 24
Finished Apr 23 02:28:17 PM PDT 24
Peak memory 202240 kb
Host smart-cddafc9b-aa7e-410e-b52d-90e9d99a9d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226146802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3226146802
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4005081846
Short name T518
Test name
Test status
Simulation time 333153029109 ps
CPU time 718.45 seconds
Started Apr 23 02:27:16 PM PDT 24
Finished Apr 23 02:39:14 PM PDT 24
Peak memory 202228 kb
Host smart-377a73e5-c61f-4bfa-8591-4861b6f3d3fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005081846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4005081846
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3981074750
Short name T155
Test name
Test status
Simulation time 371061063475 ps
CPU time 442.98 seconds
Started Apr 23 02:27:23 PM PDT 24
Finished Apr 23 02:34:46 PM PDT 24
Peak memory 202340 kb
Host smart-05d34df3-aded-4e40-8bb3-db555c30e152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981074750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3981074750
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3489814463
Short name T519
Test name
Test status
Simulation time 409115963700 ps
CPU time 912.33 seconds
Started Apr 23 02:27:21 PM PDT 24
Finished Apr 23 02:42:34 PM PDT 24
Peak memory 202304 kb
Host smart-d8471f5e-29b6-4b80-945b-6ea271994ad7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489814463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3489814463
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2733662893
Short name T761
Test name
Test status
Simulation time 130798797385 ps
CPU time 473.86 seconds
Started Apr 23 02:27:26 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 202436 kb
Host smart-74b097d1-8c02-49ea-b054-6dc76683c1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733662893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2733662893
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3022288974
Short name T679
Test name
Test status
Simulation time 23201225082 ps
CPU time 55.87 seconds
Started Apr 23 02:27:24 PM PDT 24
Finished Apr 23 02:28:20 PM PDT 24
Peak memory 202048 kb
Host smart-41de48c1-b5cf-4d20-b4ee-4626b2734749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022288974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3022288974
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2776511786
Short name T163
Test name
Test status
Simulation time 2896051844 ps
CPU time 2.87 seconds
Started Apr 23 02:27:27 PM PDT 24
Finished Apr 23 02:27:31 PM PDT 24
Peak memory 202060 kb
Host smart-c1d4d0bf-b54a-4f33-8d01-14d69955abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776511786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2776511786
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.910740190
Short name T461
Test name
Test status
Simulation time 6153074371 ps
CPU time 1.72 seconds
Started Apr 23 02:27:16 PM PDT 24
Finished Apr 23 02:27:18 PM PDT 24
Peak memory 202056 kb
Host smart-2d52b8b2-9c87-4ecc-bdf8-7251a47f20f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910740190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.910740190
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3912121474
Short name T282
Test name
Test status
Simulation time 333167236451 ps
CPU time 101.77 seconds
Started Apr 23 02:27:28 PM PDT 24
Finished Apr 23 02:29:10 PM PDT 24
Peak memory 202348 kb
Host smart-4039737a-833d-45d3-89d6-fa89dee34ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912121474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3912121474
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.522275063
Short name T383
Test name
Test status
Simulation time 318231416 ps
CPU time 0.8 seconds
Started Apr 23 02:27:38 PM PDT 24
Finished Apr 23 02:27:39 PM PDT 24
Peak memory 201980 kb
Host smart-58e0dd91-d8bf-4077-aa78-bd714067bfe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522275063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.522275063
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1489164799
Short name T334
Test name
Test status
Simulation time 320852525791 ps
CPU time 396.45 seconds
Started Apr 23 02:27:27 PM PDT 24
Finished Apr 23 02:34:04 PM PDT 24
Peak memory 202304 kb
Host smart-0f657f03-08e5-4303-965d-c4954dbdc97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489164799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1489164799
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.182585980
Short name T654
Test name
Test status
Simulation time 165253752549 ps
CPU time 374.33 seconds
Started Apr 23 02:27:30 PM PDT 24
Finished Apr 23 02:33:45 PM PDT 24
Peak memory 202176 kb
Host smart-7713a06f-d35c-40e2-8619-381d4a325ec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=182585980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.182585980
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2728981667
Short name T319
Test name
Test status
Simulation time 330487942560 ps
CPU time 731.08 seconds
Started Apr 23 02:27:30 PM PDT 24
Finished Apr 23 02:39:41 PM PDT 24
Peak memory 202284 kb
Host smart-354e1b50-e630-47cd-8580-4cfed4bb4647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728981667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2728981667
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3644651827
Short name T162
Test name
Test status
Simulation time 165766092917 ps
CPU time 105.65 seconds
Started Apr 23 02:27:28 PM PDT 24
Finished Apr 23 02:29:14 PM PDT 24
Peak memory 202220 kb
Host smart-f97cdfd0-c61a-4e87-b134-9a01bdb2a75c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644651827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3644651827
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1263026246
Short name T171
Test name
Test status
Simulation time 541153316355 ps
CPU time 423.65 seconds
Started Apr 23 02:27:28 PM PDT 24
Finished Apr 23 02:34:32 PM PDT 24
Peak memory 202260 kb
Host smart-27d31539-c0fd-42c7-8250-ded7a24cd57c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263026246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1263026246
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.862284337
Short name T545
Test name
Test status
Simulation time 193384414278 ps
CPU time 97.25 seconds
Started Apr 23 02:27:29 PM PDT 24
Finished Apr 23 02:29:06 PM PDT 24
Peak memory 202064 kb
Host smart-6b763019-941c-49e0-bbfb-e15e137d75ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862284337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.862284337
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2639915055
Short name T597
Test name
Test status
Simulation time 78051089280 ps
CPU time 277.73 seconds
Started Apr 23 02:27:34 PM PDT 24
Finished Apr 23 02:32:12 PM PDT 24
Peak memory 202628 kb
Host smart-cab48603-1a09-4b56-a500-30734803d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639915055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2639915055
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1876052121
Short name T380
Test name
Test status
Simulation time 32229666351 ps
CPU time 39.9 seconds
Started Apr 23 02:27:32 PM PDT 24
Finished Apr 23 02:28:13 PM PDT 24
Peak memory 202076 kb
Host smart-5cc6ad63-0234-49c9-b6b9-f9eab3ca26d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876052121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1876052121
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.198910333
Short name T459
Test name
Test status
Simulation time 4993606758 ps
CPU time 6.75 seconds
Started Apr 23 02:27:31 PM PDT 24
Finished Apr 23 02:27:38 PM PDT 24
Peak memory 202060 kb
Host smart-5c9d97e9-f37a-4287-a487-e6ba12bb1857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198910333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.198910333
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1366115911
Short name T81
Test name
Test status
Simulation time 5642863179 ps
CPU time 3.34 seconds
Started Apr 23 02:27:29 PM PDT 24
Finished Apr 23 02:27:33 PM PDT 24
Peak memory 201912 kb
Host smart-e2483178-7da3-4798-8956-0b32c9f90057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366115911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1366115911
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.342841543
Short name T203
Test name
Test status
Simulation time 54712932492 ps
CPU time 181.84 seconds
Started Apr 23 02:27:36 PM PDT 24
Finished Apr 23 02:30:38 PM PDT 24
Peak memory 211176 kb
Host smart-421f9d52-0a27-4f21-988e-c647e8f191f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342841543 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.342841543
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1081981206
Short name T375
Test name
Test status
Simulation time 358785751 ps
CPU time 1.48 seconds
Started Apr 23 02:27:48 PM PDT 24
Finished Apr 23 02:27:50 PM PDT 24
Peak memory 201924 kb
Host smart-09baee1d-1d10-4224-a19c-eaed62f9d435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081981206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1081981206
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1310310560
Short name T765
Test name
Test status
Simulation time 317093087862 ps
CPU time 556.97 seconds
Started Apr 23 02:27:43 PM PDT 24
Finished Apr 23 02:37:00 PM PDT 24
Peak memory 202268 kb
Host smart-16245afa-10b4-4da8-b085-f534ed837583
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310310560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1310310560
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2270758981
Short name T723
Test name
Test status
Simulation time 170086077698 ps
CPU time 110.31 seconds
Started Apr 23 02:27:41 PM PDT 24
Finished Apr 23 02:29:31 PM PDT 24
Peak memory 202260 kb
Host smart-c591be16-85ba-4e81-93e3-0f7146d74035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270758981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2270758981
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2224721499
Short name T611
Test name
Test status
Simulation time 166428909053 ps
CPU time 98 seconds
Started Apr 23 02:27:38 PM PDT 24
Finished Apr 23 02:29:17 PM PDT 24
Peak memory 202264 kb
Host smart-a8a86ba3-b682-424c-9f72-33678641402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224721499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2224721499
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2751542672
Short name T419
Test name
Test status
Simulation time 165121027944 ps
CPU time 382.47 seconds
Started Apr 23 02:27:43 PM PDT 24
Finished Apr 23 02:34:05 PM PDT 24
Peak memory 202280 kb
Host smart-14ceb719-8271-476e-8117-a5ff59e44652
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751542672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2751542672
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1320651725
Short name T325
Test name
Test status
Simulation time 164291817302 ps
CPU time 98.51 seconds
Started Apr 23 02:27:38 PM PDT 24
Finished Apr 23 02:29:17 PM PDT 24
Peak memory 202336 kb
Host smart-fa3c7bf7-32ea-461a-84b5-ac0705176ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320651725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1320651725
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4259843771
Short name T43
Test name
Test status
Simulation time 486043716642 ps
CPU time 272.05 seconds
Started Apr 23 02:27:39 PM PDT 24
Finished Apr 23 02:32:11 PM PDT 24
Peak memory 202252 kb
Host smart-34d07bdb-1db8-4e3b-8582-fd6f82fec83b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259843771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4259843771
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.31019970
Short name T517
Test name
Test status
Simulation time 386705453891 ps
CPU time 805.73 seconds
Started Apr 23 02:27:44 PM PDT 24
Finished Apr 23 02:41:10 PM PDT 24
Peak memory 202212 kb
Host smart-0b1747b8-fb14-440e-9d0a-5a7c98f24beb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31019970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
dc_ctrl_filters_wakeup_fixed.31019970
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.4071254216
Short name T209
Test name
Test status
Simulation time 78443517223 ps
CPU time 458.93 seconds
Started Apr 23 02:27:43 PM PDT 24
Finished Apr 23 02:35:23 PM PDT 24
Peak memory 202572 kb
Host smart-2a37035f-5be0-4e6e-a72b-5f97140fec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071254216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.4071254216
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1587760215
Short name T369
Test name
Test status
Simulation time 29241390272 ps
CPU time 37.09 seconds
Started Apr 23 02:27:44 PM PDT 24
Finished Apr 23 02:28:22 PM PDT 24
Peak memory 202016 kb
Host smart-ef2d65cd-947b-4617-97aa-d8e9a0384ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587760215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1587760215
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3992044318
Short name T98
Test name
Test status
Simulation time 3090063728 ps
CPU time 2.51 seconds
Started Apr 23 02:27:40 PM PDT 24
Finished Apr 23 02:27:43 PM PDT 24
Peak memory 202060 kb
Host smart-e6870c8a-ed71-4973-a044-a1e37b4dea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992044318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3992044318
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3005099396
Short name T348
Test name
Test status
Simulation time 5693801296 ps
CPU time 12.84 seconds
Started Apr 23 02:27:37 PM PDT 24
Finished Apr 23 02:27:50 PM PDT 24
Peak memory 202072 kb
Host smart-d7e6bdec-f6c2-4cb1-9785-a17cf3efe595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005099396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3005099396
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.694248529
Short name T731
Test name
Test status
Simulation time 495043170 ps
CPU time 1.73 seconds
Started Apr 23 02:27:58 PM PDT 24
Finished Apr 23 02:28:00 PM PDT 24
Peak memory 201980 kb
Host smart-081361d1-331b-4fa6-aa8f-686712baa4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694248529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.694248529
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1035466032
Short name T568
Test name
Test status
Simulation time 164409593912 ps
CPU time 345.84 seconds
Started Apr 23 02:27:45 PM PDT 24
Finished Apr 23 02:33:31 PM PDT 24
Peak memory 202284 kb
Host smart-492199b3-0be0-4128-948b-111a95643a77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035466032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1035466032
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.204147817
Short name T481
Test name
Test status
Simulation time 165275574201 ps
CPU time 350.69 seconds
Started Apr 23 02:27:50 PM PDT 24
Finished Apr 23 02:33:41 PM PDT 24
Peak memory 202296 kb
Host smart-c7b45e10-fdfa-4b25-9de6-dccfea4bd3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204147817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.204147817
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2297179177
Short name T659
Test name
Test status
Simulation time 499830537346 ps
CPU time 1105.21 seconds
Started Apr 23 02:27:48 PM PDT 24
Finished Apr 23 02:46:13 PM PDT 24
Peak memory 202188 kb
Host smart-66e28443-137e-4e14-8258-576157164c00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297179177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2297179177
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3375444558
Short name T152
Test name
Test status
Simulation time 328365434598 ps
CPU time 194.7 seconds
Started Apr 23 02:27:44 PM PDT 24
Finished Apr 23 02:30:59 PM PDT 24
Peak memory 202260 kb
Host smart-251b670b-6c10-4662-98d5-1b6ffb06997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375444558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3375444558
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2650612913
Short name T342
Test name
Test status
Simulation time 331858058171 ps
CPU time 354.21 seconds
Started Apr 23 02:27:48 PM PDT 24
Finished Apr 23 02:33:42 PM PDT 24
Peak memory 202168 kb
Host smart-533d64c6-a1ce-4abc-b52c-3a0e104d02ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650612913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2650612913
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2585951417
Short name T214
Test name
Test status
Simulation time 349337149756 ps
CPU time 451.05 seconds
Started Apr 23 02:27:49 PM PDT 24
Finished Apr 23 02:35:20 PM PDT 24
Peak memory 202252 kb
Host smart-04588250-b45a-42fa-8eef-453d8a6b5668
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585951417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2585951417
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.338517794
Short name T432
Test name
Test status
Simulation time 399211774126 ps
CPU time 314.28 seconds
Started Apr 23 02:27:48 PM PDT 24
Finished Apr 23 02:33:03 PM PDT 24
Peak memory 202184 kb
Host smart-710b4551-19bf-4d57-863b-38db230e98c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338517794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.338517794
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3397333242
Short name T201
Test name
Test status
Simulation time 152677224725 ps
CPU time 501.87 seconds
Started Apr 23 02:27:50 PM PDT 24
Finished Apr 23 02:36:12 PM PDT 24
Peak memory 202580 kb
Host smart-0fde640d-06ed-4be0-8eb6-8d957da9e153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397333242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3397333242
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.817051218
Short name T456
Test name
Test status
Simulation time 27561680217 ps
CPU time 66.16 seconds
Started Apr 23 02:27:50 PM PDT 24
Finished Apr 23 02:28:56 PM PDT 24
Peak memory 201992 kb
Host smart-d1c88241-d70c-4bc5-af28-ab1ca6023467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817051218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.817051218
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.740445396
Short name T16
Test name
Test status
Simulation time 3205402923 ps
CPU time 1.03 seconds
Started Apr 23 02:27:50 PM PDT 24
Finished Apr 23 02:27:51 PM PDT 24
Peak memory 202020 kb
Host smart-5cdda4b5-6442-4809-928f-0fbfe89887d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740445396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.740445396
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.549022492
Short name T728
Test name
Test status
Simulation time 6149542506 ps
CPU time 3.95 seconds
Started Apr 23 02:27:47 PM PDT 24
Finished Apr 23 02:27:51 PM PDT 24
Peak memory 202056 kb
Host smart-f99c1950-8f78-47d2-b648-3be8c3c30528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549022492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.549022492
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4178452113
Short name T727
Test name
Test status
Simulation time 168741206020 ps
CPU time 97.88 seconds
Started Apr 23 02:27:54 PM PDT 24
Finished Apr 23 02:29:32 PM PDT 24
Peak memory 202224 kb
Host smart-ebdd4bbf-26fc-42f8-b756-c48afb08d89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178452113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4178452113
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1958061878
Short name T436
Test name
Test status
Simulation time 51885734863 ps
CPU time 36.52 seconds
Started Apr 23 02:27:53 PM PDT 24
Finished Apr 23 02:28:30 PM PDT 24
Peak memory 202452 kb
Host smart-7582c320-28b5-41ce-8198-11cfd1a06efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958061878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1958061878
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1316416252
Short name T378
Test name
Test status
Simulation time 545232937 ps
CPU time 0.85 seconds
Started Apr 23 02:28:08 PM PDT 24
Finished Apr 23 02:28:10 PM PDT 24
Peak memory 201964 kb
Host smart-89f1dccc-3442-429b-9774-2b9b614c90e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316416252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1316416252
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1712359757
Short name T227
Test name
Test status
Simulation time 175865796823 ps
CPU time 11.76 seconds
Started Apr 23 02:28:02 PM PDT 24
Finished Apr 23 02:28:14 PM PDT 24
Peak memory 202128 kb
Host smart-8247ae65-a12d-41e1-a7eb-bdec133a1dfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712359757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1712359757
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1694237671
Short name T577
Test name
Test status
Simulation time 168387416489 ps
CPU time 95.31 seconds
Started Apr 23 02:28:03 PM PDT 24
Finished Apr 23 02:29:39 PM PDT 24
Peak memory 202220 kb
Host smart-a6bb3794-df28-4aa7-b491-85ea0dec3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694237671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1694237671
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2014734090
Short name T232
Test name
Test status
Simulation time 319910374358 ps
CPU time 192.73 seconds
Started Apr 23 02:28:02 PM PDT 24
Finished Apr 23 02:31:15 PM PDT 24
Peak memory 202220 kb
Host smart-5074cf48-8a04-47db-8a9f-9ba94ef62198
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014734090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2014734090
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3140255688
Short name T506
Test name
Test status
Simulation time 166378288476 ps
CPU time 102.91 seconds
Started Apr 23 02:27:59 PM PDT 24
Finished Apr 23 02:29:42 PM PDT 24
Peak memory 202264 kb
Host smart-6ddd363b-a348-4e30-81fb-3d8600be047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140255688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3140255688
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.870621741
Short name T462
Test name
Test status
Simulation time 486603903389 ps
CPU time 958.7 seconds
Started Apr 23 02:27:59 PM PDT 24
Finished Apr 23 02:43:58 PM PDT 24
Peak memory 202212 kb
Host smart-186a8a13-c7af-425b-8d9b-ac92342e9880
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=870621741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.870621741
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3074745599
Short name T158
Test name
Test status
Simulation time 344340398948 ps
CPU time 415.6 seconds
Started Apr 23 02:28:02 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 202280 kb
Host smart-84589805-390f-48ad-ac35-728f15d4ebce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074745599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3074745599
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2726949609
Short name T669
Test name
Test status
Simulation time 598427014052 ps
CPU time 369.12 seconds
Started Apr 23 02:28:03 PM PDT 24
Finished Apr 23 02:34:13 PM PDT 24
Peak memory 202168 kb
Host smart-aa2b832f-4576-4ddb-b590-ec267e4907e0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726949609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2726949609
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3569744489
Short name T424
Test name
Test status
Simulation time 77866076984 ps
CPU time 376.69 seconds
Started Apr 23 02:28:04 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 202620 kb
Host smart-4d4c979d-3d0d-4990-a0b1-3b68c74e1abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569744489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3569744489
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3114577236
Short name T174
Test name
Test status
Simulation time 31348028002 ps
CPU time 10.76 seconds
Started Apr 23 02:28:06 PM PDT 24
Finished Apr 23 02:28:17 PM PDT 24
Peak memory 202068 kb
Host smart-9e79e41c-bb9f-4c93-8f95-4bc92635a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114577236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3114577236
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.751678997
Short name T593
Test name
Test status
Simulation time 3480249333 ps
CPU time 4.51 seconds
Started Apr 23 02:28:03 PM PDT 24
Finished Apr 23 02:28:08 PM PDT 24
Peak memory 202048 kb
Host smart-c0b9dd15-8b08-4442-b792-72d990f24e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751678997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.751678997
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.4211465052
Short name T179
Test name
Test status
Simulation time 5947248837 ps
CPU time 4.34 seconds
Started Apr 23 02:27:58 PM PDT 24
Finished Apr 23 02:28:03 PM PDT 24
Peak memory 202072 kb
Host smart-862b592c-f9d4-4aee-87f6-dc4742a8d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211465052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.4211465052
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4084948758
Short name T531
Test name
Test status
Simulation time 390901791 ps
CPU time 1.52 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:26:03 PM PDT 24
Peak memory 201940 kb
Host smart-c2bf0ba4-a3c6-4c25-98f8-da1464c1e465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084948758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4084948758
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2960278519
Short name T772
Test name
Test status
Simulation time 181230869048 ps
CPU time 375.15 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:32:19 PM PDT 24
Peak memory 202248 kb
Host smart-549f117f-f1bd-478a-a44c-756ea501e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960278519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2960278519
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.638538263
Short name T340
Test name
Test status
Simulation time 332761141333 ps
CPU time 401.24 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:32:43 PM PDT 24
Peak memory 202220 kb
Host smart-efc6a19e-03b2-4843-a97e-cfb6e21dda38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=638538263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.638538263
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.311098698
Short name T229
Test name
Test status
Simulation time 497071171889 ps
CPU time 1168.51 seconds
Started Apr 23 02:26:02 PM PDT 24
Finished Apr 23 02:45:31 PM PDT 24
Peak memory 202236 kb
Host smart-7c41ce83-4564-439f-98f1-f3f11371a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311098698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.311098698
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1667207705
Short name T3
Test name
Test status
Simulation time 483077423444 ps
CPU time 840.88 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:40:03 PM PDT 24
Peak memory 202232 kb
Host smart-5445ae99-2a8b-40ff-99fe-6113c76bbece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667207705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1667207705
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3054083730
Short name T90
Test name
Test status
Simulation time 535407904953 ps
CPU time 214.79 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:29:36 PM PDT 24
Peak memory 202260 kb
Host smart-f9b33f29-8937-45cf-a217-1a3ed0d791bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054083730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3054083730
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3368446442
Short name T393
Test name
Test status
Simulation time 616900867354 ps
CPU time 241.81 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:30:02 PM PDT 24
Peak memory 201936 kb
Host smart-8f4d7af3-b7cd-46aa-800c-d53a7b9f2c0f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368446442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3368446442
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3020847017
Short name T647
Test name
Test status
Simulation time 118884899864 ps
CPU time 606.53 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:36:19 PM PDT 24
Peak memory 202556 kb
Host smart-9944c46a-11ce-4969-99ca-e9e1b0f3c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020847017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3020847017
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.4235208807
Short name T421
Test name
Test status
Simulation time 43676608230 ps
CPU time 50.25 seconds
Started Apr 23 02:26:06 PM PDT 24
Finished Apr 23 02:26:57 PM PDT 24
Peak memory 201992 kb
Host smart-0e14c7db-0eab-4a3b-b4f6-0cb772a5cbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235208807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4235208807
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3077118611
Short name T470
Test name
Test status
Simulation time 2936912943 ps
CPU time 7.38 seconds
Started Apr 23 02:26:01 PM PDT 24
Finished Apr 23 02:26:10 PM PDT 24
Peak memory 202012 kb
Host smart-09768c63-5a71-4ace-b78b-60c699c12d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077118611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3077118611
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2827038777
Short name T63
Test name
Test status
Simulation time 7521405218 ps
CPU time 17.71 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:26:22 PM PDT 24
Peak memory 218848 kb
Host smart-466db73d-2e49-45f3-994f-f8a29cf9f828
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827038777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2827038777
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.4173928378
Short name T8
Test name
Test status
Simulation time 5804860930 ps
CPU time 14.33 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:26:19 PM PDT 24
Peak memory 202008 kb
Host smart-d16e26e7-0aba-4aa6-968a-233e57f93f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173928378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.4173928378
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2949576474
Short name T646
Test name
Test status
Simulation time 210054971537 ps
CPU time 483.92 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:34:24 PM PDT 24
Peak memory 202144 kb
Host smart-30d75cd2-4dbb-4147-b0f4-a1a2795f3b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949576474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2949576474
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3075073774
Short name T762
Test name
Test status
Simulation time 401809198 ps
CPU time 1.04 seconds
Started Apr 23 02:28:21 PM PDT 24
Finished Apr 23 02:28:23 PM PDT 24
Peak memory 201920 kb
Host smart-5809dabe-039d-4e5e-a9dc-89698f025d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075073774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3075073774
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.331460018
Short name T221
Test name
Test status
Simulation time 517624590376 ps
CPU time 370.57 seconds
Started Apr 23 02:28:14 PM PDT 24
Finished Apr 23 02:34:25 PM PDT 24
Peak memory 202252 kb
Host smart-2af147e7-91b3-495b-b63d-fd807887cec8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331460018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.331460018
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.547691040
Short name T216
Test name
Test status
Simulation time 162558326707 ps
CPU time 84.26 seconds
Started Apr 23 02:28:16 PM PDT 24
Finished Apr 23 02:29:41 PM PDT 24
Peak memory 202080 kb
Host smart-11367932-8652-428b-945e-b1d580ff41b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547691040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.547691040
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.129064194
Short name T465
Test name
Test status
Simulation time 321081950582 ps
CPU time 782.27 seconds
Started Apr 23 02:28:13 PM PDT 24
Finished Apr 23 02:41:15 PM PDT 24
Peak memory 202228 kb
Host smart-510ccff7-0c66-400c-a958-c0ac29f3638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129064194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.129064194
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.609427570
Short name T653
Test name
Test status
Simulation time 161535773390 ps
CPU time 95.38 seconds
Started Apr 23 02:28:13 PM PDT 24
Finished Apr 23 02:29:49 PM PDT 24
Peak memory 202228 kb
Host smart-e0e2eb3d-7387-461c-a1ca-b58dc8d8973b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=609427570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.609427570
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3402651422
Short name T729
Test name
Test status
Simulation time 325963263918 ps
CPU time 707.42 seconds
Started Apr 23 02:28:06 PM PDT 24
Finished Apr 23 02:39:54 PM PDT 24
Peak memory 202328 kb
Host smart-f997008a-66c9-43a1-ac82-8c0b085d3fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402651422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3402651422
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.878435013
Short name T572
Test name
Test status
Simulation time 329317958468 ps
CPU time 642.46 seconds
Started Apr 23 02:28:09 PM PDT 24
Finished Apr 23 02:38:52 PM PDT 24
Peak memory 202196 kb
Host smart-d4061696-a609-44c2-ad54-22e2f6adb597
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=878435013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.878435013
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.635660109
Short name T535
Test name
Test status
Simulation time 190057038567 ps
CPU time 144.84 seconds
Started Apr 23 02:28:12 PM PDT 24
Finished Apr 23 02:30:37 PM PDT 24
Peak memory 202252 kb
Host smart-70d2d19f-2c87-4a55-aa3e-9c3a187b4625
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635660109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.635660109
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1235133639
Short name T52
Test name
Test status
Simulation time 129649837475 ps
CPU time 458.23 seconds
Started Apr 23 02:28:18 PM PDT 24
Finished Apr 23 02:35:56 PM PDT 24
Peak memory 202560 kb
Host smart-60e301ab-a022-473e-b886-128fc37e3708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235133639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1235133639
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2635173069
Short name T675
Test name
Test status
Simulation time 35261570707 ps
CPU time 74.19 seconds
Started Apr 23 02:28:18 PM PDT 24
Finished Apr 23 02:29:33 PM PDT 24
Peak memory 202080 kb
Host smart-7e3590c7-fe85-464f-8dc7-0be210b62b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635173069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2635173069
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3281612347
Short name T632
Test name
Test status
Simulation time 5281629793 ps
CPU time 11.39 seconds
Started Apr 23 02:28:16 PM PDT 24
Finished Apr 23 02:28:28 PM PDT 24
Peak memory 201904 kb
Host smart-852bec84-2f69-4fa5-939e-b758d9a7c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281612347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3281612347
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2858937853
Short name T581
Test name
Test status
Simulation time 5941170012 ps
CPU time 8.23 seconds
Started Apr 23 02:28:07 PM PDT 24
Finished Apr 23 02:28:16 PM PDT 24
Peak memory 202096 kb
Host smart-3f8087d4-872f-4233-b9c6-8950df2dc623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858937853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2858937853
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2396824498
Short name T746
Test name
Test status
Simulation time 489195489807 ps
CPU time 1077.74 seconds
Started Apr 23 02:28:22 PM PDT 24
Finished Apr 23 02:46:20 PM PDT 24
Peak memory 202184 kb
Host smart-f6562d93-0c12-402c-a842-00733ce54e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396824498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2396824498
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.875002798
Short name T634
Test name
Test status
Simulation time 292022754 ps
CPU time 1.27 seconds
Started Apr 23 02:28:27 PM PDT 24
Finished Apr 23 02:28:29 PM PDT 24
Peak memory 201880 kb
Host smart-73af0fc5-656e-4375-a63b-3cf0be3b40f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875002798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.875002798
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1873382954
Short name T245
Test name
Test status
Simulation time 167290676321 ps
CPU time 395.07 seconds
Started Apr 23 02:28:21 PM PDT 24
Finished Apr 23 02:34:57 PM PDT 24
Peak memory 202204 kb
Host smart-3fdce3a4-9bcb-44c4-b89e-340e66ac122a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873382954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1873382954
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3707854713
Short name T423
Test name
Test status
Simulation time 161680822139 ps
CPU time 240.48 seconds
Started Apr 23 02:28:20 PM PDT 24
Finished Apr 23 02:32:21 PM PDT 24
Peak memory 202200 kb
Host smart-1a3d6861-9e14-42ef-95c7-fba16ede8647
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707854713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3707854713
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2646895124
Short name T149
Test name
Test status
Simulation time 160055368723 ps
CPU time 104.53 seconds
Started Apr 23 02:28:23 PM PDT 24
Finished Apr 23 02:30:08 PM PDT 24
Peak memory 202184 kb
Host smart-2462f84e-5cc3-4be4-ae4f-f8a6130b0f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646895124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2646895124
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.57703221
Short name T344
Test name
Test status
Simulation time 164716264221 ps
CPU time 104.38 seconds
Started Apr 23 02:28:22 PM PDT 24
Finished Apr 23 02:30:07 PM PDT 24
Peak memory 202244 kb
Host smart-b19ab05d-a7ad-4986-a64d-d0094a76832c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=57703221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed
.57703221
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1287352400
Short name T527
Test name
Test status
Simulation time 193121108236 ps
CPU time 111.29 seconds
Started Apr 23 02:28:23 PM PDT 24
Finished Apr 23 02:30:14 PM PDT 24
Peak memory 202248 kb
Host smart-bbb56dcc-f225-4e37-bede-fc2225aa14a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287352400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1287352400
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2786886885
Short name T376
Test name
Test status
Simulation time 205366127271 ps
CPU time 130.47 seconds
Started Apr 23 02:28:23 PM PDT 24
Finished Apr 23 02:30:34 PM PDT 24
Peak memory 202252 kb
Host smart-ba8d7944-f0ad-44c6-a755-ebb3d2ca22d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786886885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2786886885
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2447474862
Short name T91
Test name
Test status
Simulation time 93625956748 ps
CPU time 317.24 seconds
Started Apr 23 02:28:24 PM PDT 24
Finished Apr 23 02:33:41 PM PDT 24
Peak memory 202536 kb
Host smart-f6f824af-fda2-457b-852a-6b193414ea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447474862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2447474862
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2890797551
Short name T642
Test name
Test status
Simulation time 24600655525 ps
CPU time 8.1 seconds
Started Apr 23 02:28:25 PM PDT 24
Finished Apr 23 02:28:33 PM PDT 24
Peak memory 202044 kb
Host smart-185f4e66-09e3-4322-8fd2-b9476cf22ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890797551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2890797551
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3115448508
Short name T655
Test name
Test status
Simulation time 3828952433 ps
CPU time 2.02 seconds
Started Apr 23 02:28:22 PM PDT 24
Finished Apr 23 02:28:25 PM PDT 24
Peak memory 202072 kb
Host smart-acc8c8e6-6b19-4ff8-b156-047611825248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115448508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3115448508
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3663232850
Short name T453
Test name
Test status
Simulation time 5993256534 ps
CPU time 13.76 seconds
Started Apr 23 02:28:23 PM PDT 24
Finished Apr 23 02:28:37 PM PDT 24
Peak memory 202012 kb
Host smart-0d0d10c6-f848-428e-ac9c-a4595dcc1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663232850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3663232850
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.456509772
Short name T583
Test name
Test status
Simulation time 581332090217 ps
CPU time 1588.56 seconds
Started Apr 23 02:28:27 PM PDT 24
Finished Apr 23 02:54:56 PM PDT 24
Peak memory 210812 kb
Host smart-799e8d49-f510-4d19-92c1-9d9a17dd265f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456509772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
456509772
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3866093984
Short name T754
Test name
Test status
Simulation time 482215841 ps
CPU time 0.78 seconds
Started Apr 23 02:28:41 PM PDT 24
Finished Apr 23 02:28:42 PM PDT 24
Peak memory 201980 kb
Host smart-cbd6594c-3246-4342-b58c-3fc06e01101e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866093984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3866093984
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4290421368
Short name T164
Test name
Test status
Simulation time 591497914985 ps
CPU time 1079.56 seconds
Started Apr 23 02:28:36 PM PDT 24
Finished Apr 23 02:46:36 PM PDT 24
Peak memory 202260 kb
Host smart-4e60cb87-d219-4263-9153-788117b63269
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290421368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4290421368
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.473418378
Short name T594
Test name
Test status
Simulation time 165542740055 ps
CPU time 43.93 seconds
Started Apr 23 02:28:36 PM PDT 24
Finished Apr 23 02:29:21 PM PDT 24
Peak memory 202252 kb
Host smart-36d1c659-b2ce-48cb-8562-64efb8c223d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473418378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.473418378
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2120419144
Short name T34
Test name
Test status
Simulation time 324502879022 ps
CPU time 749.32 seconds
Started Apr 23 02:28:36 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 202248 kb
Host smart-63a9fc1d-881c-4d08-a372-b4d1d3e880dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120419144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2120419144
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1782689410
Short name T660
Test name
Test status
Simulation time 485174084618 ps
CPU time 1044.84 seconds
Started Apr 23 02:28:37 PM PDT 24
Finished Apr 23 02:46:03 PM PDT 24
Peak memory 202320 kb
Host smart-6ef05e79-b9c1-4ce8-9626-02368304baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782689410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1782689410
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1642055292
Short name T94
Test name
Test status
Simulation time 163480320232 ps
CPU time 73.2 seconds
Started Apr 23 02:28:37 PM PDT 24
Finished Apr 23 02:29:50 PM PDT 24
Peak memory 202288 kb
Host smart-bf1204a4-3a6a-41ea-b319-340301586c93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642055292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1642055292
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2366339310
Short name T726
Test name
Test status
Simulation time 190906911639 ps
CPU time 458.91 seconds
Started Apr 23 02:28:40 PM PDT 24
Finished Apr 23 02:36:19 PM PDT 24
Peak memory 202252 kb
Host smart-faf9bd8d-4bbe-43eb-ba93-5b65cfd58001
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366339310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2366339310
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1607885029
Short name T722
Test name
Test status
Simulation time 113024000113 ps
CPU time 581.18 seconds
Started Apr 23 02:28:35 PM PDT 24
Finished Apr 23 02:38:17 PM PDT 24
Peak memory 202568 kb
Host smart-6c931230-7b14-4a4f-96b5-b23df3f6336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607885029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1607885029
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1633297990
Short name T399
Test name
Test status
Simulation time 21111274700 ps
CPU time 24.48 seconds
Started Apr 23 02:28:37 PM PDT 24
Finished Apr 23 02:29:03 PM PDT 24
Peak memory 202048 kb
Host smart-9c679558-a6c6-4f70-84a2-efc30b1cd57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633297990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1633297990
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2091837920
Short name T350
Test name
Test status
Simulation time 2969895637 ps
CPU time 7.34 seconds
Started Apr 23 02:28:36 PM PDT 24
Finished Apr 23 02:28:43 PM PDT 24
Peak memory 202008 kb
Host smart-ba3b75c0-274b-47c4-97a8-7dd06c68fa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091837920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2091837920
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1875606011
Short name T587
Test name
Test status
Simulation time 5798123688 ps
CPU time 15.88 seconds
Started Apr 23 02:28:37 PM PDT 24
Finished Apr 23 02:28:54 PM PDT 24
Peak memory 202052 kb
Host smart-9c5b9d9e-9348-4b87-9601-ba84cfa1521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875606011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1875606011
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1233217859
Short name T694
Test name
Test status
Simulation time 509427384702 ps
CPU time 1172.7 seconds
Started Apr 23 02:28:40 PM PDT 24
Finished Apr 23 02:48:13 PM PDT 24
Peak memory 202228 kb
Host smart-aa26ed8b-2ad8-4b08-a4ce-5357c957d92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233217859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1233217859
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.706507739
Short name T220
Test name
Test status
Simulation time 9095417865 ps
CPU time 32.14 seconds
Started Apr 23 02:28:41 PM PDT 24
Finished Apr 23 02:29:14 PM PDT 24
Peak memory 210912 kb
Host smart-507f0b43-51e7-47ea-a4bb-e4e8b36500a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706507739 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.706507739
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4000567351
Short name T430
Test name
Test status
Simulation time 279143395 ps
CPU time 1.25 seconds
Started Apr 23 02:28:48 PM PDT 24
Finished Apr 23 02:28:50 PM PDT 24
Peak memory 201940 kb
Host smart-97d454c3-8416-40df-a113-cce29527d99c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000567351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4000567351
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3005316178
Short name T154
Test name
Test status
Simulation time 504712705799 ps
CPU time 191.74 seconds
Started Apr 23 02:28:45 PM PDT 24
Finished Apr 23 02:31:57 PM PDT 24
Peak memory 202320 kb
Host smart-a2e49b08-d353-464e-8367-80b78f088c1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005316178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3005316178
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2175820339
Short name T500
Test name
Test status
Simulation time 166355564209 ps
CPU time 219.45 seconds
Started Apr 23 02:28:42 PM PDT 24
Finished Apr 23 02:32:22 PM PDT 24
Peak memory 202276 kb
Host smart-f18e272c-46a7-42cd-a179-01b5b3bb2588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175820339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2175820339
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3106579367
Short name T758
Test name
Test status
Simulation time 163358751263 ps
CPU time 344.46 seconds
Started Apr 23 02:28:42 PM PDT 24
Finished Apr 23 02:34:27 PM PDT 24
Peak memory 202276 kb
Host smart-1b97a043-3004-4bd9-95fe-9852f3e31aa9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106579367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3106579367
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.380713662
Short name T273
Test name
Test status
Simulation time 162361842350 ps
CPU time 26.84 seconds
Started Apr 23 02:28:39 PM PDT 24
Finished Apr 23 02:29:07 PM PDT 24
Peak memory 202304 kb
Host smart-495381a0-be4b-40a7-acf9-e547f27d75a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380713662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.380713662
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2147859507
Short name T32
Test name
Test status
Simulation time 493835875832 ps
CPU time 328.05 seconds
Started Apr 23 02:28:42 PM PDT 24
Finished Apr 23 02:34:10 PM PDT 24
Peak memory 202200 kb
Host smart-a78d7a6b-5663-4303-9ce1-e3bb79d3a4f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147859507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2147859507
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3481092421
Short name T92
Test name
Test status
Simulation time 203070859081 ps
CPU time 451.2 seconds
Started Apr 23 02:28:44 PM PDT 24
Finished Apr 23 02:36:16 PM PDT 24
Peak memory 202308 kb
Host smart-34a80cf3-cce7-494c-936c-49fa0bab14b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481092421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3481092421
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3877016598
Short name T551
Test name
Test status
Simulation time 610052663971 ps
CPU time 383.74 seconds
Started Apr 23 02:28:50 PM PDT 24
Finished Apr 23 02:35:14 PM PDT 24
Peak memory 202280 kb
Host smart-0c9c087a-0f1a-4e16-bcc1-f8111e40fb1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877016598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3877016598
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.328525815
Short name T552
Test name
Test status
Simulation time 132392247878 ps
CPU time 430.47 seconds
Started Apr 23 02:28:45 PM PDT 24
Finished Apr 23 02:35:56 PM PDT 24
Peak memory 202600 kb
Host smart-e7b7e17a-e8fc-450a-8844-03c35c4ee177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328525815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.328525815
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.973397367
Short name T710
Test name
Test status
Simulation time 36256803606 ps
CPU time 85.77 seconds
Started Apr 23 02:28:50 PM PDT 24
Finished Apr 23 02:30:16 PM PDT 24
Peak memory 202024 kb
Host smart-e4b6496f-5fdf-4958-b76e-c56d305b6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973397367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.973397367
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.751346042
Short name T718
Test name
Test status
Simulation time 5186517347 ps
CPU time 4 seconds
Started Apr 23 02:28:45 PM PDT 24
Finished Apr 23 02:28:49 PM PDT 24
Peak memory 202056 kb
Host smart-d99b344f-dd6c-42f1-8c95-c721a1b64443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751346042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.751346042
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3121900135
Short name T707
Test name
Test status
Simulation time 5892061560 ps
CPU time 13.85 seconds
Started Apr 23 02:28:39 PM PDT 24
Finished Apr 23 02:28:54 PM PDT 24
Peak memory 202060 kb
Host smart-1aea5c1f-cf4f-4a64-9651-1ca777ec2d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121900135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3121900135
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.880080173
Short name T316
Test name
Test status
Simulation time 518793635267 ps
CPU time 617.81 seconds
Started Apr 23 02:28:48 PM PDT 24
Finished Apr 23 02:39:07 PM PDT 24
Peak memory 202344 kb
Host smart-4bae306c-69de-4210-8b91-b4f951a0fefc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880080173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
880080173
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2683205324
Short name T20
Test name
Test status
Simulation time 126720372472 ps
CPU time 79.04 seconds
Started Apr 23 02:28:49 PM PDT 24
Finished Apr 23 02:30:09 PM PDT 24
Peak memory 210872 kb
Host smart-ab8145a0-de61-42c3-9966-ea648286a1f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683205324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2683205324
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3713755234
Short name T82
Test name
Test status
Simulation time 329449036 ps
CPU time 0.83 seconds
Started Apr 23 02:28:55 PM PDT 24
Finished Apr 23 02:28:57 PM PDT 24
Peak memory 201904 kb
Host smart-637fab64-7221-43e7-a5eb-28c269d31c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713755234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3713755234
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.308677389
Short name T571
Test name
Test status
Simulation time 165573947961 ps
CPU time 97.96 seconds
Started Apr 23 02:28:52 PM PDT 24
Finished Apr 23 02:30:30 PM PDT 24
Peak memory 202240 kb
Host smart-0d964884-d4b5-40b3-b11d-017b4b3e1cd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308677389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.308677389
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.394096940
Short name T136
Test name
Test status
Simulation time 515535875295 ps
CPU time 1095.62 seconds
Started Apr 23 02:28:54 PM PDT 24
Finished Apr 23 02:47:10 PM PDT 24
Peak memory 202220 kb
Host smart-a6dd3965-fa90-4d26-bdf3-ba3779760b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394096940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.394096940
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.967962771
Short name T311
Test name
Test status
Simulation time 326070627896 ps
CPU time 206.77 seconds
Started Apr 23 02:28:53 PM PDT 24
Finished Apr 23 02:32:20 PM PDT 24
Peak memory 202324 kb
Host smart-12881f30-99fd-4acd-98aa-07964fd466a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967962771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.967962771
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4021558265
Short name T744
Test name
Test status
Simulation time 493080208671 ps
CPU time 1163.7 seconds
Started Apr 23 02:28:52 PM PDT 24
Finished Apr 23 02:48:16 PM PDT 24
Peak memory 202188 kb
Host smart-c873bad6-f28b-4683-aeb2-b2880c3beaac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021558265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.4021558265
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3120527359
Short name T241
Test name
Test status
Simulation time 498785492236 ps
CPU time 298.69 seconds
Started Apr 23 02:28:48 PM PDT 24
Finished Apr 23 02:33:47 PM PDT 24
Peak memory 202316 kb
Host smart-e50c70fa-be74-4e52-b2cc-77e6d4d5acf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120527359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3120527359
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2594375215
Short name T357
Test name
Test status
Simulation time 330681312263 ps
CPU time 191.7 seconds
Started Apr 23 02:28:52 PM PDT 24
Finished Apr 23 02:32:04 PM PDT 24
Peak memory 202164 kb
Host smart-8e50ceb1-39be-420e-9a92-5b4f4cbba40e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594375215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2594375215
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1132250146
Short name T123
Test name
Test status
Simulation time 643986575735 ps
CPU time 118.87 seconds
Started Apr 23 02:28:53 PM PDT 24
Finished Apr 23 02:30:52 PM PDT 24
Peak memory 202252 kb
Host smart-f8e17aa0-4d75-496a-a081-f6db2730dbaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132250146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1132250146
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.562456238
Short name T435
Test name
Test status
Simulation time 206326227043 ps
CPU time 109.1 seconds
Started Apr 23 02:28:52 PM PDT 24
Finished Apr 23 02:30:42 PM PDT 24
Peak memory 202256 kb
Host smart-fa8366dc-775b-4a30-abc3-28dfbafc03b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562456238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.562456238
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3556945478
Short name T657
Test name
Test status
Simulation time 92283999495 ps
CPU time 314.26 seconds
Started Apr 23 02:28:54 PM PDT 24
Finished Apr 23 02:34:09 PM PDT 24
Peak memory 202544 kb
Host smart-70b48cdc-b368-495a-b6c2-de3baa6c6960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556945478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3556945478
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2510686738
Short name T437
Test name
Test status
Simulation time 37213999837 ps
CPU time 80.97 seconds
Started Apr 23 02:28:55 PM PDT 24
Finished Apr 23 02:30:17 PM PDT 24
Peak memory 202088 kb
Host smart-b30b36c8-7a12-4ff2-9899-94771b165d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510686738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2510686738
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4288855703
Short name T606
Test name
Test status
Simulation time 4702246876 ps
CPU time 12.12 seconds
Started Apr 23 02:28:51 PM PDT 24
Finished Apr 23 02:29:03 PM PDT 24
Peak memory 202080 kb
Host smart-96775073-8a6f-4382-819e-c3d6c6dfe48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288855703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4288855703
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4056832669
Short name T591
Test name
Test status
Simulation time 6014563900 ps
CPU time 14.72 seconds
Started Apr 23 02:28:50 PM PDT 24
Finished Apr 23 02:29:05 PM PDT 24
Peak memory 202016 kb
Host smart-b83d3dd4-a392-4e81-905a-e88854c86721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056832669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4056832669
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1212839492
Short name T195
Test name
Test status
Simulation time 303316386838 ps
CPU time 515.69 seconds
Started Apr 23 02:28:58 PM PDT 24
Finished Apr 23 02:37:34 PM PDT 24
Peak memory 210704 kb
Host smart-3905598b-3ca4-4e16-8027-5cfb524c3866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212839492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1212839492
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1523275730
Short name T231
Test name
Test status
Simulation time 81602073181 ps
CPU time 159.39 seconds
Started Apr 23 02:28:58 PM PDT 24
Finished Apr 23 02:31:38 PM PDT 24
Peak memory 210608 kb
Host smart-4f5a7c77-d547-499c-8176-06ccb20de217
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523275730 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1523275730
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2956433864
Short name T537
Test name
Test status
Simulation time 326144775 ps
CPU time 1.3 seconds
Started Apr 23 02:29:13 PM PDT 24
Finished Apr 23 02:29:14 PM PDT 24
Peak memory 201952 kb
Host smart-a9b2e8ca-bbbf-4ccc-8f69-20985282de35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956433864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2956433864
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1295596539
Short name T333
Test name
Test status
Simulation time 344454244794 ps
CPU time 208.38 seconds
Started Apr 23 02:29:09 PM PDT 24
Finished Apr 23 02:32:37 PM PDT 24
Peak memory 202212 kb
Host smart-58c909f0-38fe-4129-8a1f-52af03ce92eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295596539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1295596539
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.795281885
Short name T242
Test name
Test status
Simulation time 162108750613 ps
CPU time 178.61 seconds
Started Apr 23 02:28:59 PM PDT 24
Finished Apr 23 02:31:58 PM PDT 24
Peak memory 202280 kb
Host smart-7f63a9c5-b4d9-4199-81d5-c7fd5fbcfeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795281885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.795281885
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.217985446
Short name T608
Test name
Test status
Simulation time 494464677694 ps
CPU time 1054.9 seconds
Started Apr 23 02:29:04 PM PDT 24
Finished Apr 23 02:46:39 PM PDT 24
Peak memory 202188 kb
Host smart-181ca802-b34e-44ef-a32d-95ea92aa18ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217985446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.217985446
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1413755934
Short name T243
Test name
Test status
Simulation time 161925511767 ps
CPU time 55.42 seconds
Started Apr 23 02:28:57 PM PDT 24
Finished Apr 23 02:29:53 PM PDT 24
Peak memory 202316 kb
Host smart-6d68870f-1edf-46fe-9dc7-b57e277d22d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413755934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1413755934
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3794648869
Short name T702
Test name
Test status
Simulation time 320047209808 ps
CPU time 249.93 seconds
Started Apr 23 02:29:00 PM PDT 24
Finished Apr 23 02:33:10 PM PDT 24
Peak memory 202304 kb
Host smart-ce19d407-f5ab-4362-be15-33a691d19f57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794648869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3794648869
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2281511333
Short name T717
Test name
Test status
Simulation time 363695522952 ps
CPU time 414.55 seconds
Started Apr 23 02:29:08 PM PDT 24
Finished Apr 23 02:36:03 PM PDT 24
Peak memory 202280 kb
Host smart-79c2e042-fe77-484a-806e-1ca589b6565f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281511333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2281511333
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4128847506
Short name T767
Test name
Test status
Simulation time 602979692081 ps
CPU time 515.27 seconds
Started Apr 23 02:29:05 PM PDT 24
Finished Apr 23 02:37:41 PM PDT 24
Peak memory 202208 kb
Host smart-3c3d2cfd-6c25-4a92-b639-901a91e16b18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128847506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4128847506
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3581029538
Short name T50
Test name
Test status
Simulation time 111855313168 ps
CPU time 583.42 seconds
Started Apr 23 02:29:11 PM PDT 24
Finished Apr 23 02:38:55 PM PDT 24
Peak memory 202536 kb
Host smart-30963181-2f3b-42c9-b507-448a43ac7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581029538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3581029538
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3438897285
Short name T382
Test name
Test status
Simulation time 36622020096 ps
CPU time 79.73 seconds
Started Apr 23 02:29:10 PM PDT 24
Finished Apr 23 02:30:30 PM PDT 24
Peak memory 202036 kb
Host smart-bbf1203c-3a76-4fdf-a1fe-b8891df6b3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438897285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3438897285
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2619558284
Short name T792
Test name
Test status
Simulation time 4400204287 ps
CPU time 2.54 seconds
Started Apr 23 02:29:09 PM PDT 24
Finished Apr 23 02:29:12 PM PDT 24
Peak memory 201984 kb
Host smart-17e40930-7bba-40a4-a2db-b76ae620ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619558284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2619558284
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.477157948
Short name T620
Test name
Test status
Simulation time 5681666043 ps
CPU time 14.95 seconds
Started Apr 23 02:28:58 PM PDT 24
Finished Apr 23 02:29:13 PM PDT 24
Peak memory 202076 kb
Host smart-7b4722a4-25dd-4b28-ae06-6d527461d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477157948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.477157948
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3228833036
Short name T674
Test name
Test status
Simulation time 243781536695 ps
CPU time 392.11 seconds
Started Apr 23 02:29:11 PM PDT 24
Finished Apr 23 02:35:43 PM PDT 24
Peak memory 218880 kb
Host smart-81c4223c-59c4-487f-9afa-ab88643a0238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228833036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3228833036
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1181494099
Short name T296
Test name
Test status
Simulation time 198919975038 ps
CPU time 167.83 seconds
Started Apr 23 02:29:13 PM PDT 24
Finished Apr 23 02:32:01 PM PDT 24
Peak memory 218944 kb
Host smart-b42f7ca8-316c-4f3e-bfdb-3b15d4ce93b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181494099 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1181494099
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1019546062
Short name T364
Test name
Test status
Simulation time 432418054 ps
CPU time 0.79 seconds
Started Apr 23 02:29:26 PM PDT 24
Finished Apr 23 02:29:27 PM PDT 24
Peak memory 201988 kb
Host smart-63880c68-e2e2-4dd2-be21-cbabb039df84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019546062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1019546062
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.941037901
Short name T223
Test name
Test status
Simulation time 339051007715 ps
CPU time 424.4 seconds
Started Apr 23 02:29:18 PM PDT 24
Finished Apr 23 02:36:23 PM PDT 24
Peak memory 202180 kb
Host smart-c83115ef-9710-4675-adbf-b20da498b72e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941037901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.941037901
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4170686669
Short name T119
Test name
Test status
Simulation time 358118704627 ps
CPU time 218.53 seconds
Started Apr 23 02:29:18 PM PDT 24
Finished Apr 23 02:32:57 PM PDT 24
Peak memory 202220 kb
Host smart-a3d4e353-974c-4f77-8d24-e85f5bfbd599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170686669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4170686669
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1422126372
Short name T143
Test name
Test status
Simulation time 487146324010 ps
CPU time 172.45 seconds
Started Apr 23 02:29:21 PM PDT 24
Finished Apr 23 02:32:14 PM PDT 24
Peak memory 202284 kb
Host smart-0f247cba-4198-425e-bbd8-50471784a2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422126372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1422126372
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2939267692
Short name T553
Test name
Test status
Simulation time 168343305850 ps
CPU time 81.14 seconds
Started Apr 23 02:29:18 PM PDT 24
Finished Apr 23 02:30:40 PM PDT 24
Peak memory 202228 kb
Host smart-d4a8cdf0-0cac-4771-af10-15f1ae977a2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939267692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2939267692
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.811412412
Short name T121
Test name
Test status
Simulation time 153967653555 ps
CPU time 190.77 seconds
Started Apr 23 02:29:12 PM PDT 24
Finished Apr 23 02:32:24 PM PDT 24
Peak memory 202304 kb
Host smart-6ddd8a33-0e08-4f0b-bd71-2fb320959139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811412412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.811412412
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.241207193
Short name T721
Test name
Test status
Simulation time 325413632512 ps
CPU time 735.79 seconds
Started Apr 23 02:29:18 PM PDT 24
Finished Apr 23 02:41:34 PM PDT 24
Peak memory 202200 kb
Host smart-d5b89f2b-9014-4017-99a2-d5eb711b8679
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=241207193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.241207193
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3858257418
Short name T161
Test name
Test status
Simulation time 531334207862 ps
CPU time 329.5 seconds
Started Apr 23 02:29:18 PM PDT 24
Finished Apr 23 02:34:48 PM PDT 24
Peak memory 202344 kb
Host smart-968aefa5-a107-49b6-9368-bcb00c02691e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858257418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3858257418
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1661747818
Short name T412
Test name
Test status
Simulation time 610328393007 ps
CPU time 1379.22 seconds
Started Apr 23 02:29:17 PM PDT 24
Finished Apr 23 02:52:17 PM PDT 24
Peak memory 202204 kb
Host smart-6c5c2259-5111-4256-a6cb-9033d2273432
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661747818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1661747818
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1033420004
Short name T206
Test name
Test status
Simulation time 70416114809 ps
CPU time 279.74 seconds
Started Apr 23 02:29:22 PM PDT 24
Finished Apr 23 02:34:02 PM PDT 24
Peak memory 202560 kb
Host smart-76395073-48fe-42d5-b8d0-68fa73fe52c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033420004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1033420004
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2494859008
Short name T439
Test name
Test status
Simulation time 36833987323 ps
CPU time 43.37 seconds
Started Apr 23 02:29:21 PM PDT 24
Finished Apr 23 02:30:05 PM PDT 24
Peak memory 202032 kb
Host smart-d629d3dd-85c1-4532-b7e4-1cd8f528394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494859008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2494859008
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.459656174
Short name T390
Test name
Test status
Simulation time 4089418249 ps
CPU time 8.76 seconds
Started Apr 23 02:29:17 PM PDT 24
Finished Apr 23 02:29:27 PM PDT 24
Peak memory 202068 kb
Host smart-ff95ce4e-037a-44ea-af61-bd9ee9d573d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459656174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.459656174
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1696492208
Short name T693
Test name
Test status
Simulation time 5943066777 ps
CPU time 7.38 seconds
Started Apr 23 02:29:12 PM PDT 24
Finished Apr 23 02:29:19 PM PDT 24
Peak memory 202072 kb
Host smart-95470080-1b7e-40c4-b4fc-0f7cbf40cf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696492208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1696492208
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.387889601
Short name T184
Test name
Test status
Simulation time 164736581232 ps
CPU time 32.54 seconds
Started Apr 23 02:29:21 PM PDT 24
Finished Apr 23 02:29:54 PM PDT 24
Peak memory 202260 kb
Host smart-707e515a-f4a6-4950-897f-b2428a98e46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387889601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
387889601
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2070020033
Short name T546
Test name
Test status
Simulation time 438452959045 ps
CPU time 150.5 seconds
Started Apr 23 02:29:22 PM PDT 24
Finished Apr 23 02:31:53 PM PDT 24
Peak memory 210568 kb
Host smart-efb27e89-23a8-4e07-bf05-c56df63c2b22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070020033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2070020033
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.666254593
Short name T176
Test name
Test status
Simulation time 405214382 ps
CPU time 0.7 seconds
Started Apr 23 02:29:35 PM PDT 24
Finished Apr 23 02:29:36 PM PDT 24
Peak memory 201876 kb
Host smart-472c2408-8eb1-4622-ae22-570084694b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666254593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.666254593
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.649241301
Short name T224
Test name
Test status
Simulation time 170984889770 ps
CPU time 125.78 seconds
Started Apr 23 02:29:28 PM PDT 24
Finished Apr 23 02:31:34 PM PDT 24
Peak memory 202248 kb
Host smart-4372b074-8ffc-4466-b9d2-db01ffeb209d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649241301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.649241301
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3773948188
Short name T491
Test name
Test status
Simulation time 166069759325 ps
CPU time 395.68 seconds
Started Apr 23 02:29:29 PM PDT 24
Finished Apr 23 02:36:05 PM PDT 24
Peak memory 202244 kb
Host smart-64269a67-634b-4de3-9972-7d24f6584123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773948188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3773948188
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4210243867
Short name T275
Test name
Test status
Simulation time 172378361847 ps
CPU time 202.52 seconds
Started Apr 23 02:29:30 PM PDT 24
Finished Apr 23 02:32:53 PM PDT 24
Peak memory 202236 kb
Host smart-fe1184bf-3db3-46b2-80e9-da17f312726f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210243867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4210243867
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3175976483
Short name T549
Test name
Test status
Simulation time 327658902387 ps
CPU time 816.56 seconds
Started Apr 23 02:29:29 PM PDT 24
Finished Apr 23 02:43:06 PM PDT 24
Peak memory 202228 kb
Host smart-75b389b2-c125-4eb4-82ad-2c0b5257f33c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175976483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3175976483
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1777528550
Short name T331
Test name
Test status
Simulation time 481472706380 ps
CPU time 1137.96 seconds
Started Apr 23 02:29:27 PM PDT 24
Finished Apr 23 02:48:25 PM PDT 24
Peak memory 202220 kb
Host smart-9dacf39c-ef3d-43d0-b63f-e863f068a0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777528550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1777528550
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3673709403
Short name T492
Test name
Test status
Simulation time 500827121230 ps
CPU time 291.77 seconds
Started Apr 23 02:29:29 PM PDT 24
Finished Apr 23 02:34:21 PM PDT 24
Peak memory 202240 kb
Host smart-9994e863-c180-4414-9cba-54f0d3260fbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673709403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3673709403
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1936793058
Short name T558
Test name
Test status
Simulation time 617365320200 ps
CPU time 1519.23 seconds
Started Apr 23 02:29:30 PM PDT 24
Finished Apr 23 02:54:49 PM PDT 24
Peak memory 202172 kb
Host smart-bd731cc7-cb39-458c-8f82-f7ee8a468dfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936793058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1936793058
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.137563407
Short name T522
Test name
Test status
Simulation time 83381329259 ps
CPU time 368.26 seconds
Started Apr 23 02:29:31 PM PDT 24
Finished Apr 23 02:35:40 PM PDT 24
Peak memory 202620 kb
Host smart-55359e5e-662e-47f2-989a-507214b23196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137563407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.137563407
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1239157177
Short name T362
Test name
Test status
Simulation time 38349385574 ps
CPU time 23.45 seconds
Started Apr 23 02:29:33 PM PDT 24
Finished Apr 23 02:29:57 PM PDT 24
Peak memory 202016 kb
Host smart-adc2466a-743b-46c1-b4cf-3c935e7da858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239157177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1239157177
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3005383056
Short name T509
Test name
Test status
Simulation time 5418039903 ps
CPU time 5.83 seconds
Started Apr 23 02:29:28 PM PDT 24
Finished Apr 23 02:29:34 PM PDT 24
Peak memory 202052 kb
Host smart-7ab82d43-ad32-43b2-8492-8822fab2a615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005383056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3005383056
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2356925345
Short name T627
Test name
Test status
Simulation time 6064754774 ps
CPU time 13.18 seconds
Started Apr 23 02:29:25 PM PDT 24
Finished Apr 23 02:29:38 PM PDT 24
Peak memory 202064 kb
Host smart-e0645725-0348-40c8-b0ce-0ca3ce0b5966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356925345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2356925345
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2626899205
Short name T637
Test name
Test status
Simulation time 59383252097 ps
CPU time 135.23 seconds
Started Apr 23 02:29:33 PM PDT 24
Finished Apr 23 02:31:49 PM PDT 24
Peak memory 210528 kb
Host smart-94546b1b-7b51-4aa7-a974-e46572cc40c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626899205 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2626899205
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.683446810
Short name T427
Test name
Test status
Simulation time 424106324 ps
CPU time 0.81 seconds
Started Apr 23 02:29:45 PM PDT 24
Finished Apr 23 02:29:46 PM PDT 24
Peak memory 201988 kb
Host smart-d6e4fc59-593d-4258-a8d9-f4a36488c2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683446810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.683446810
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3776273993
Short name T715
Test name
Test status
Simulation time 166501036977 ps
CPU time 200.03 seconds
Started Apr 23 02:29:43 PM PDT 24
Finished Apr 23 02:33:04 PM PDT 24
Peak memory 202268 kb
Host smart-ea600460-534b-4405-bd46-c95e03ce01e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776273993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3776273993
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1106627603
Short name T753
Test name
Test status
Simulation time 535031303436 ps
CPU time 1282.13 seconds
Started Apr 23 02:29:40 PM PDT 24
Finished Apr 23 02:51:03 PM PDT 24
Peak memory 202284 kb
Host smart-697f67ed-95fe-4954-aa95-0ecd434b7123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106627603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1106627603
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2891039106
Short name T29
Test name
Test status
Simulation time 327230969092 ps
CPU time 367.62 seconds
Started Apr 23 02:29:39 PM PDT 24
Finished Apr 23 02:35:47 PM PDT 24
Peak memory 202244 kb
Host smart-f6d53959-8223-4775-80cd-e90a2350acc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891039106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2891039106
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.269047692
Short name T416
Test name
Test status
Simulation time 165217338874 ps
CPU time 388.97 seconds
Started Apr 23 02:29:39 PM PDT 24
Finished Apr 23 02:36:08 PM PDT 24
Peak memory 202196 kb
Host smart-84d59389-001c-4458-b85b-618b205ccdb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=269047692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.269047692
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.160414922
Short name T182
Test name
Test status
Simulation time 486499890854 ps
CPU time 283.62 seconds
Started Apr 23 02:29:38 PM PDT 24
Finished Apr 23 02:34:22 PM PDT 24
Peak memory 202144 kb
Host smart-36e32144-c42a-451c-86df-d0eda0566ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160414922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.160414922
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2552690666
Short name T795
Test name
Test status
Simulation time 326839254748 ps
CPU time 676.74 seconds
Started Apr 23 02:29:38 PM PDT 24
Finished Apr 23 02:40:55 PM PDT 24
Peak memory 202332 kb
Host smart-6919d33d-8e3b-4c02-bcbf-504f0ba1041c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552690666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2552690666
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1773968028
Short name T619
Test name
Test status
Simulation time 188768972306 ps
CPU time 388.47 seconds
Started Apr 23 02:29:38 PM PDT 24
Finished Apr 23 02:36:07 PM PDT 24
Peak memory 202268 kb
Host smart-4034ecb2-8d87-4e2e-b04d-48b806c1556f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773968028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1773968028
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.4146872956
Short name T579
Test name
Test status
Simulation time 203981483334 ps
CPU time 127.43 seconds
Started Apr 23 02:29:40 PM PDT 24
Finished Apr 23 02:31:48 PM PDT 24
Peak memory 202172 kb
Host smart-f7d8cb32-5868-49b8-ab59-ce540627ffab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146872956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.4146872956
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1647505377
Short name T478
Test name
Test status
Simulation time 62571588881 ps
CPU time 230.08 seconds
Started Apr 23 02:29:46 PM PDT 24
Finished Apr 23 02:33:36 PM PDT 24
Peak memory 202588 kb
Host smart-c1c091dd-7597-49a7-88ab-b53ef26d72cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647505377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1647505377
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3484302654
Short name T547
Test name
Test status
Simulation time 42800940875 ps
CPU time 25.19 seconds
Started Apr 23 02:29:46 PM PDT 24
Finished Apr 23 02:30:11 PM PDT 24
Peak memory 202028 kb
Host smart-366ba255-61ec-47e9-ab0d-92a6530f9c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484302654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3484302654
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2945612290
Short name T780
Test name
Test status
Simulation time 3226741045 ps
CPU time 8.51 seconds
Started Apr 23 02:29:42 PM PDT 24
Finished Apr 23 02:29:51 PM PDT 24
Peak memory 202024 kb
Host smart-b8baaa32-5c33-49a2-ba0a-3d22ffdc4b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945612290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2945612290
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4198161882
Short name T401
Test name
Test status
Simulation time 6116998922 ps
CPU time 1.67 seconds
Started Apr 23 02:29:35 PM PDT 24
Finished Apr 23 02:29:37 PM PDT 24
Peak memory 202052 kb
Host smart-13ecb880-8636-4d65-ab18-4957f0e64bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198161882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4198161882
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.277720497
Short name T204
Test name
Test status
Simulation time 577614505776 ps
CPU time 1003.34 seconds
Started Apr 23 02:29:45 PM PDT 24
Finished Apr 23 02:46:29 PM PDT 24
Peak memory 212824 kb
Host smart-6a81a820-a50d-441e-aab7-69213064d7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277720497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
277720497
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.15936279
Short name T285
Test name
Test status
Simulation time 239833094800 ps
CPU time 115.69 seconds
Started Apr 23 02:29:44 PM PDT 24
Finished Apr 23 02:31:40 PM PDT 24
Peak memory 214312 kb
Host smart-44052659-bff6-488e-a45b-487075c8562a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936279 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.15936279
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3023181804
Short name T578
Test name
Test status
Simulation time 363647567 ps
CPU time 0.85 seconds
Started Apr 23 02:29:56 PM PDT 24
Finished Apr 23 02:29:57 PM PDT 24
Peak memory 201976 kb
Host smart-8127394c-bf90-4a5f-9c8f-5db4c6bcb938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023181804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3023181804
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3929007084
Short name T494
Test name
Test status
Simulation time 334323059424 ps
CPU time 77.48 seconds
Started Apr 23 02:29:48 PM PDT 24
Finished Apr 23 02:31:06 PM PDT 24
Peak memory 202288 kb
Host smart-3d693da4-cac7-4951-ba97-4b9c2703e702
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929007084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3929007084
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.252577056
Short name T173
Test name
Test status
Simulation time 499096145589 ps
CPU time 489.11 seconds
Started Apr 23 02:29:49 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 202228 kb
Host smart-b217cc25-557f-4a06-8dde-0b12900bef16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252577056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.252577056
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4280170598
Short name T297
Test name
Test status
Simulation time 490324929205 ps
CPU time 288.02 seconds
Started Apr 23 02:29:47 PM PDT 24
Finished Apr 23 02:34:36 PM PDT 24
Peak memory 202292 kb
Host smart-5dba4b49-d185-4c17-ae1f-9f42e297bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280170598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4280170598
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1148243887
Short name T709
Test name
Test status
Simulation time 159862782841 ps
CPU time 50.47 seconds
Started Apr 23 02:29:47 PM PDT 24
Finished Apr 23 02:30:38 PM PDT 24
Peak memory 202208 kb
Host smart-601e29fb-82b7-4646-ba0d-ab77813ffb03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148243887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1148243887
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.756694010
Short name T793
Test name
Test status
Simulation time 167711484764 ps
CPU time 190.57 seconds
Started Apr 23 02:29:45 PM PDT 24
Finished Apr 23 02:32:55 PM PDT 24
Peak memory 202268 kb
Host smart-601473ed-059a-45fb-98f0-ee32e359562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756694010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.756694010
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2951491500
Short name T27
Test name
Test status
Simulation time 165833203818 ps
CPU time 93.56 seconds
Started Apr 23 02:29:47 PM PDT 24
Finished Apr 23 02:31:21 PM PDT 24
Peak memory 202224 kb
Host smart-9eb13357-922a-4728-8bf4-1882137a7f60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951491500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2951491500
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1384742794
Short name T30
Test name
Test status
Simulation time 358873538352 ps
CPU time 832.6 seconds
Started Apr 23 02:29:48 PM PDT 24
Finished Apr 23 02:43:41 PM PDT 24
Peak memory 202304 kb
Host smart-5ffa86a0-3845-4f2c-9428-b3f413b56941
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384742794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1384742794
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.753920703
Short name T559
Test name
Test status
Simulation time 197621549781 ps
CPU time 235.57 seconds
Started Apr 23 02:29:48 PM PDT 24
Finished Apr 23 02:33:43 PM PDT 24
Peak memory 202204 kb
Host smart-a57b92a8-d6ab-4a15-a164-49a53806094e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753920703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.753920703
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1132149527
Short name T640
Test name
Test status
Simulation time 130115323067 ps
CPU time 570.6 seconds
Started Apr 23 02:29:55 PM PDT 24
Finished Apr 23 02:39:26 PM PDT 24
Peak memory 202652 kb
Host smart-821e255c-0d2d-46dd-a4b4-90316e4950b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132149527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1132149527
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2413690882
Short name T175
Test name
Test status
Simulation time 42718275497 ps
CPU time 16.68 seconds
Started Apr 23 02:29:49 PM PDT 24
Finished Apr 23 02:30:06 PM PDT 24
Peak memory 202052 kb
Host smart-d1b89b64-cff6-484a-9cbd-dce0eb362ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413690882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2413690882
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2920589065
Short name T83
Test name
Test status
Simulation time 3578794223 ps
CPU time 8.68 seconds
Started Apr 23 02:29:49 PM PDT 24
Finished Apr 23 02:29:58 PM PDT 24
Peak memory 201964 kb
Host smart-41fd9f98-ab89-4ee5-abd7-620f71e0cc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920589065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2920589065
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3224665506
Short name T555
Test name
Test status
Simulation time 5980560131 ps
CPU time 4.15 seconds
Started Apr 23 02:29:46 PM PDT 24
Finished Apr 23 02:29:50 PM PDT 24
Peak memory 202068 kb
Host smart-bff307b1-51be-4f79-ab7d-c67c5b893380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224665506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3224665506
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2841393519
Short name T788
Test name
Test status
Simulation time 194505249374 ps
CPU time 113.39 seconds
Started Apr 23 02:29:54 PM PDT 24
Finished Apr 23 02:31:48 PM PDT 24
Peak memory 202248 kb
Host smart-dbe6c5b2-e54b-49cb-bca4-64b1e49ab8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841393519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2841393519
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1671605924
Short name T26
Test name
Test status
Simulation time 348549020576 ps
CPU time 206.68 seconds
Started Apr 23 02:29:56 PM PDT 24
Finished Apr 23 02:33:23 PM PDT 24
Peak memory 210572 kb
Host smart-368145a4-dfde-4543-8740-8ceb4b41da6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671605924 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1671605924
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3791805192
Short name T489
Test name
Test status
Simulation time 433796005 ps
CPU time 0.85 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:26:05 PM PDT 24
Peak memory 201960 kb
Host smart-13ff182d-ebce-4056-9438-d47ae5ec2bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791805192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3791805192
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1341417626
Short name T429
Test name
Test status
Simulation time 173620609933 ps
CPU time 211.12 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:29:36 PM PDT 24
Peak memory 202248 kb
Host smart-5cbe5371-c130-4bcb-8c20-a92117f1649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341417626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1341417626
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3484003045
Short name T605
Test name
Test status
Simulation time 332002050745 ps
CPU time 161.15 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:28:47 PM PDT 24
Peak memory 202356 kb
Host smart-b45ddcac-25a6-455e-ab5b-2f532e24424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484003045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3484003045
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.174632745
Short name T533
Test name
Test status
Simulation time 168215163157 ps
CPU time 107.16 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:27:51 PM PDT 24
Peak memory 202276 kb
Host smart-787fe9b3-6aa2-41df-8259-6745a5bbd9f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=174632745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.174632745
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1643419498
Short name T426
Test name
Test status
Simulation time 166350666003 ps
CPU time 203.93 seconds
Started Apr 23 02:26:02 PM PDT 24
Finished Apr 23 02:29:27 PM PDT 24
Peak memory 202320 kb
Host smart-144dc488-8736-4df9-a04e-8b0ce0b627de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643419498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1643419498
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.404264215
Short name T682
Test name
Test status
Simulation time 165524643277 ps
CPU time 155.99 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:28:42 PM PDT 24
Peak memory 202304 kb
Host smart-fe124c03-1fab-4e56-83e3-1603847096ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=404264215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.404264215
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2637487038
Short name T280
Test name
Test status
Simulation time 163236282113 ps
CPU time 62.34 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:27:13 PM PDT 24
Peak memory 202348 kb
Host smart-a0728cd4-4ec1-4365-8067-8bb7339ab9d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637487038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2637487038
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4034302215
Short name T486
Test name
Test status
Simulation time 403639464728 ps
CPU time 772.78 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:39:11 PM PDT 24
Peak memory 202048 kb
Host smart-079782f8-d21b-4cfa-a177-7edad1cc047f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034302215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4034302215
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1681161796
Short name T777
Test name
Test status
Simulation time 77888226873 ps
CPU time 320.37 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:31:40 PM PDT 24
Peak memory 202368 kb
Host smart-92c73380-0ead-428b-8945-9f7575707508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681161796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1681161796
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4049975606
Short name T700
Test name
Test status
Simulation time 25219746213 ps
CPU time 9.07 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:26:29 PM PDT 24
Peak memory 201872 kb
Host smart-94ee92ff-0180-4071-a118-19c2d3b6a34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049975606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4049975606
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3338469481
Short name T529
Test name
Test status
Simulation time 3627948269 ps
CPU time 2.05 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:26:06 PM PDT 24
Peak memory 201980 kb
Host smart-2e4b73fa-5608-4380-a244-9899326a7685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338469481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3338469481
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2333947371
Short name T78
Test name
Test status
Simulation time 4322836490 ps
CPU time 3.14 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:26:16 PM PDT 24
Peak memory 217788 kb
Host smart-55e085d7-c7b1-4875-b210-c50d84d0b11d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333947371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2333947371
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2772538459
Short name T664
Test name
Test status
Simulation time 5401211031 ps
CPU time 12.19 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:26:16 PM PDT 24
Peak memory 202064 kb
Host smart-0059f043-4989-4663-8390-a9d017546e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772538459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2772538459
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3900147908
Short name T262
Test name
Test status
Simulation time 548271429305 ps
CPU time 292.29 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:30:56 PM PDT 24
Peak memory 202340 kb
Host smart-37a40522-3d92-47c7-a3c1-019965bc69c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900147908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3900147908
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1138808705
Short name T671
Test name
Test status
Simulation time 540213248 ps
CPU time 1.25 seconds
Started Apr 23 02:30:05 PM PDT 24
Finished Apr 23 02:30:07 PM PDT 24
Peak memory 201840 kb
Host smart-beebb8b3-0a23-471a-b030-d50c9622e172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138808705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1138808705
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2679639796
Short name T172
Test name
Test status
Simulation time 534240498490 ps
CPU time 558.61 seconds
Started Apr 23 02:30:02 PM PDT 24
Finished Apr 23 02:39:21 PM PDT 24
Peak memory 202244 kb
Host smart-7c7d0eb8-d1db-454c-9c1f-14455d95165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679639796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2679639796
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1879748837
Short name T763
Test name
Test status
Simulation time 326669865015 ps
CPU time 263.06 seconds
Started Apr 23 02:30:05 PM PDT 24
Finished Apr 23 02:34:29 PM PDT 24
Peak memory 202200 kb
Host smart-e312013e-2228-4f8a-a798-b202f3eeab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879748837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1879748837
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2188855577
Short name T28
Test name
Test status
Simulation time 497055278175 ps
CPU time 1114.04 seconds
Started Apr 23 02:29:58 PM PDT 24
Finished Apr 23 02:48:32 PM PDT 24
Peak memory 202196 kb
Host smart-9a61606a-8aa2-4151-8fa8-5cb7e9b19a74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188855577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2188855577
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1943127287
Short name T166
Test name
Test status
Simulation time 328434285290 ps
CPU time 150.36 seconds
Started Apr 23 02:29:59 PM PDT 24
Finished Apr 23 02:32:29 PM PDT 24
Peak memory 202180 kb
Host smart-d70a2f86-c712-42f3-8960-58ffe58f1b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943127287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1943127287
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2213552334
Short name T673
Test name
Test status
Simulation time 161510072448 ps
CPU time 107.99 seconds
Started Apr 23 02:30:00 PM PDT 24
Finished Apr 23 02:31:48 PM PDT 24
Peak memory 202212 kb
Host smart-1dba50ca-70a8-4959-83e4-94d3a79738de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213552334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2213552334
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.119223259
Short name T153
Test name
Test status
Simulation time 563369617634 ps
CPU time 138.55 seconds
Started Apr 23 02:30:01 PM PDT 24
Finished Apr 23 02:32:20 PM PDT 24
Peak memory 202236 kb
Host smart-0d138886-df42-4ecc-aae6-1d2e4c9270a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119223259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.119223259
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1554954223
Short name T386
Test name
Test status
Simulation time 601652078635 ps
CPU time 1303.38 seconds
Started Apr 23 02:30:01 PM PDT 24
Finished Apr 23 02:51:45 PM PDT 24
Peak memory 202252 kb
Host smart-7822023b-d19b-4acf-abfb-2e77e828d113
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554954223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1554954223
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.756625106
Short name T464
Test name
Test status
Simulation time 130686194171 ps
CPU time 574.23 seconds
Started Apr 23 02:30:08 PM PDT 24
Finished Apr 23 02:39:43 PM PDT 24
Peak memory 202440 kb
Host smart-6a37416f-23b6-4c51-a989-6b4fb713e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756625106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.756625106
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2312360268
Short name T643
Test name
Test status
Simulation time 45517872319 ps
CPU time 29.25 seconds
Started Apr 23 02:30:03 PM PDT 24
Finished Apr 23 02:30:33 PM PDT 24
Peak memory 202084 kb
Host smart-68828007-3085-42bd-8e0b-27d4ec9ba9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312360268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2312360268
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2138318838
Short name T496
Test name
Test status
Simulation time 2780788797 ps
CPU time 6.55 seconds
Started Apr 23 02:30:04 PM PDT 24
Finished Apr 23 02:30:11 PM PDT 24
Peak memory 202032 kb
Host smart-feb392f5-a653-44f5-aea9-d8f19b82ab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138318838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2138318838
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.211702042
Short name T610
Test name
Test status
Simulation time 5579575173 ps
CPU time 3.06 seconds
Started Apr 23 02:29:58 PM PDT 24
Finished Apr 23 02:30:01 PM PDT 24
Peak memory 202068 kb
Host smart-25e336bc-bdf8-4d60-9d7a-f43816e6ebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211702042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.211702042
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2584372185
Short name T755
Test name
Test status
Simulation time 51744224753 ps
CPU time 60.72 seconds
Started Apr 23 02:30:03 PM PDT 24
Finished Apr 23 02:31:04 PM PDT 24
Peak memory 202040 kb
Host smart-6676ba73-7a2c-413d-aeec-330afb405a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584372185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2584372185
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2854616344
Short name T21
Test name
Test status
Simulation time 559965340325 ps
CPU time 415.81 seconds
Started Apr 23 02:30:05 PM PDT 24
Finished Apr 23 02:37:01 PM PDT 24
Peak memory 218316 kb
Host smart-1748e42c-31dd-4f2e-9976-caa80b49462f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854616344 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2854616344
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.877507337
Short name T574
Test name
Test status
Simulation time 445261510 ps
CPU time 1.18 seconds
Started Apr 23 02:30:08 PM PDT 24
Finished Apr 23 02:30:10 PM PDT 24
Peak memory 201960 kb
Host smart-8efe3ce2-d528-4b90-9123-f14cf291e96a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877507337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.877507337
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2271468605
Short name T607
Test name
Test status
Simulation time 602160403555 ps
CPU time 750.29 seconds
Started Apr 23 02:30:07 PM PDT 24
Finished Apr 23 02:42:37 PM PDT 24
Peak memory 202260 kb
Host smart-23817ce6-0d74-4487-bdeb-0e23057ddf10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271468605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2271468605
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2067320515
Short name T534
Test name
Test status
Simulation time 485445295028 ps
CPU time 100.12 seconds
Started Apr 23 02:30:06 PM PDT 24
Finished Apr 23 02:31:47 PM PDT 24
Peak memory 202224 kb
Host smart-b58e9681-83ad-4a19-af4b-38fbcb25f425
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067320515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2067320515
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2079483013
Short name T631
Test name
Test status
Simulation time 163091740494 ps
CPU time 355.03 seconds
Started Apr 23 02:30:05 PM PDT 24
Finished Apr 23 02:36:01 PM PDT 24
Peak memory 202304 kb
Host smart-8827575e-3bcc-41f7-8200-56ef2f9453af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079483013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2079483013
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2512169484
Short name T567
Test name
Test status
Simulation time 161129612835 ps
CPU time 98.31 seconds
Started Apr 23 02:30:06 PM PDT 24
Finished Apr 23 02:31:45 PM PDT 24
Peak memory 202152 kb
Host smart-8e2e7b9b-be86-459d-99e5-9c22a600c823
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512169484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2512169484
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3475692116
Short name T298
Test name
Test status
Simulation time 568228011559 ps
CPU time 1322.65 seconds
Started Apr 23 02:30:08 PM PDT 24
Finished Apr 23 02:52:12 PM PDT 24
Peak memory 202256 kb
Host smart-ea02397b-8df2-4f52-9798-ecbaa836ec87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475692116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3475692116
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.920602412
Short name T791
Test name
Test status
Simulation time 611168905179 ps
CPU time 360.23 seconds
Started Apr 23 02:30:10 PM PDT 24
Finished Apr 23 02:36:11 PM PDT 24
Peak memory 202236 kb
Host smart-60e4f38e-a2e7-4d88-97f3-d7cc74703918
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920602412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.920602412
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4071841612
Short name T177
Test name
Test status
Simulation time 132516575036 ps
CPU time 433.84 seconds
Started Apr 23 02:30:11 PM PDT 24
Finished Apr 23 02:37:25 PM PDT 24
Peak memory 202636 kb
Host smart-68a93c2e-dc7d-4381-9e9c-1b36b2dad2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071841612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4071841612
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1734812254
Short name T705
Test name
Test status
Simulation time 46099149157 ps
CPU time 108.49 seconds
Started Apr 23 02:30:11 PM PDT 24
Finished Apr 23 02:31:59 PM PDT 24
Peak memory 202068 kb
Host smart-03086809-6f06-481a-a10b-43cdcf1c2ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734812254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1734812254
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1259602665
Short name T409
Test name
Test status
Simulation time 4896309029 ps
CPU time 11.52 seconds
Started Apr 23 02:30:06 PM PDT 24
Finished Apr 23 02:30:18 PM PDT 24
Peak memory 202016 kb
Host smart-3ddcb3e7-a5ac-424e-bafb-9346700b2629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259602665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1259602665
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2740072498
Short name T526
Test name
Test status
Simulation time 5942062323 ps
CPU time 14.58 seconds
Started Apr 23 02:30:11 PM PDT 24
Finished Apr 23 02:30:26 PM PDT 24
Peak memory 202060 kb
Host smart-32db9976-6905-4643-aa41-9905231730e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740072498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2740072498
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.4166597793
Short name T741
Test name
Test status
Simulation time 419941447794 ps
CPU time 402.95 seconds
Started Apr 23 02:30:09 PM PDT 24
Finished Apr 23 02:36:53 PM PDT 24
Peak memory 213184 kb
Host smart-14eeef82-a29c-4e1d-b192-4e97b3a99165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166597793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.4166597793
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1663252276
Short name T306
Test name
Test status
Simulation time 92781017842 ps
CPU time 210.81 seconds
Started Apr 23 02:30:08 PM PDT 24
Finished Apr 23 02:33:40 PM PDT 24
Peak memory 210608 kb
Host smart-42890974-1f4a-44b7-8115-51d0b4b26037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663252276 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1663252276
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.4183388475
Short name T96
Test name
Test status
Simulation time 394308376 ps
CPU time 1.51 seconds
Started Apr 23 02:30:24 PM PDT 24
Finished Apr 23 02:30:26 PM PDT 24
Peak memory 201844 kb
Host smart-8d47fb67-f2bf-4bc5-a848-31719c6b0668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183388475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.4183388475
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3669590841
Short name T238
Test name
Test status
Simulation time 326514758931 ps
CPU time 141.58 seconds
Started Apr 23 02:30:19 PM PDT 24
Finished Apr 23 02:32:41 PM PDT 24
Peak memory 202276 kb
Host smart-b2dd6013-1991-49bf-bad2-150706e96803
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669590841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3669590841
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.113381310
Short name T308
Test name
Test status
Simulation time 495015514652 ps
CPU time 1102.13 seconds
Started Apr 23 02:30:17 PM PDT 24
Finished Apr 23 02:48:39 PM PDT 24
Peak memory 202264 kb
Host smart-98ccf536-6d14-4cdb-95a1-c60f934147bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113381310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.113381310
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2925137055
Short name T180
Test name
Test status
Simulation time 169762272646 ps
CPU time 101.7 seconds
Started Apr 23 02:30:16 PM PDT 24
Finished Apr 23 02:31:58 PM PDT 24
Peak memory 202228 kb
Host smart-ba1b08a8-e0ac-45ab-a4c4-0bd7f5233c83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925137055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2925137055
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2499427770
Short name T484
Test name
Test status
Simulation time 494480148434 ps
CPU time 267.6 seconds
Started Apr 23 02:30:12 PM PDT 24
Finished Apr 23 02:34:40 PM PDT 24
Peak memory 202324 kb
Host smart-53ed2121-519f-41cb-9cd8-0d968c92e7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499427770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2499427770
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.793692518
Short name T405
Test name
Test status
Simulation time 324685263116 ps
CPU time 371.78 seconds
Started Apr 23 02:30:12 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 202284 kb
Host smart-786e9758-7b7b-4598-bd54-7e93adb734c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=793692518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.793692518
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.186599815
Short name T450
Test name
Test status
Simulation time 607211667831 ps
CPU time 195.99 seconds
Started Apr 23 02:30:14 PM PDT 24
Finished Apr 23 02:33:30 PM PDT 24
Peak memory 202320 kb
Host smart-ca0f5a70-3f56-43d4-a540-ad2a6cc5bee2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186599815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.186599815
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1079686634
Short name T570
Test name
Test status
Simulation time 123869386916 ps
CPU time 436.12 seconds
Started Apr 23 02:30:20 PM PDT 24
Finished Apr 23 02:37:36 PM PDT 24
Peak memory 202612 kb
Host smart-aa4ddd2d-511f-4167-a1ec-1600cb27639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079686634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1079686634
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2741665737
Short name T99
Test name
Test status
Simulation time 33648621662 ps
CPU time 72.06 seconds
Started Apr 23 02:30:20 PM PDT 24
Finished Apr 23 02:31:32 PM PDT 24
Peak memory 202044 kb
Host smart-5d993682-8e4c-464f-95e4-c7305479d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741665737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2741665737
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.334411357
Short name T353
Test name
Test status
Simulation time 3173764453 ps
CPU time 2.35 seconds
Started Apr 23 02:30:18 PM PDT 24
Finished Apr 23 02:30:21 PM PDT 24
Peak memory 202156 kb
Host smart-2880de38-a0aa-4e48-a4e7-e5b2209d0268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334411357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.334411357
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1492435936
Short name T387
Test name
Test status
Simulation time 6128988694 ps
CPU time 16.64 seconds
Started Apr 23 02:30:13 PM PDT 24
Finished Apr 23 02:30:30 PM PDT 24
Peak memory 202056 kb
Host smart-ac3f538b-e3bd-444a-acb1-2164546842d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492435936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1492435936
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1121547595
Short name T132
Test name
Test status
Simulation time 386793086960 ps
CPU time 122.72 seconds
Started Apr 23 02:30:24 PM PDT 24
Finished Apr 23 02:32:27 PM PDT 24
Peak memory 202240 kb
Host smart-f124b509-ec94-484b-b708-e89499dc41a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121547595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1121547595
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2877909587
Short name T42
Test name
Test status
Simulation time 389851627 ps
CPU time 1.56 seconds
Started Apr 23 02:30:33 PM PDT 24
Finished Apr 23 02:30:35 PM PDT 24
Peak memory 201964 kb
Host smart-b7daa0dd-8751-4ef8-8a06-0f4ad1d625ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877909587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2877909587
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3834600218
Short name T564
Test name
Test status
Simulation time 185747568315 ps
CPU time 19.39 seconds
Started Apr 23 02:30:25 PM PDT 24
Finished Apr 23 02:30:45 PM PDT 24
Peak memory 202224 kb
Host smart-f3990483-60c5-4258-a854-ad564173b861
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834600218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3834600218
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1654977308
Short name T303
Test name
Test status
Simulation time 513539973500 ps
CPU time 635.09 seconds
Started Apr 23 02:30:31 PM PDT 24
Finished Apr 23 02:41:06 PM PDT 24
Peak memory 202268 kb
Host smart-b87b3486-c3e0-4292-b25f-2a8432dbe9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654977308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1654977308
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.4244380326
Short name T685
Test name
Test status
Simulation time 323127790274 ps
CPU time 771.12 seconds
Started Apr 23 02:30:25 PM PDT 24
Finished Apr 23 02:43:17 PM PDT 24
Peak memory 202208 kb
Host smart-d82625b4-7b8c-4c98-bc82-6e11a8f62fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244380326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4244380326
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.505319430
Short name T347
Test name
Test status
Simulation time 493768226770 ps
CPU time 311.28 seconds
Started Apr 23 02:30:26 PM PDT 24
Finished Apr 23 02:35:38 PM PDT 24
Peak memory 202280 kb
Host smart-71a34da2-e96b-4d57-98ae-bc2283f091b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=505319430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.505319430
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3967263240
Short name T768
Test name
Test status
Simulation time 330467121564 ps
CPU time 833.6 seconds
Started Apr 23 02:30:26 PM PDT 24
Finished Apr 23 02:44:20 PM PDT 24
Peak memory 202348 kb
Host smart-29487e73-36b3-4855-ac7d-c9c2c90c7b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967263240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3967263240
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4102515751
Short name T490
Test name
Test status
Simulation time 335347907579 ps
CPU time 227 seconds
Started Apr 23 02:30:25 PM PDT 24
Finished Apr 23 02:34:13 PM PDT 24
Peak memory 202160 kb
Host smart-01a0b2cb-7e55-4423-9a82-5a661219d5ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102515751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4102515751
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3971153896
Short name T431
Test name
Test status
Simulation time 199915596755 ps
CPU time 110.71 seconds
Started Apr 23 02:30:27 PM PDT 24
Finished Apr 23 02:32:18 PM PDT 24
Peak memory 202196 kb
Host smart-45104f4e-97f4-4426-9d0a-8a7d9d4a207c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971153896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3971153896
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2918017936
Short name T205
Test name
Test status
Simulation time 113292651115 ps
CPU time 447.38 seconds
Started Apr 23 02:30:31 PM PDT 24
Finished Apr 23 02:37:59 PM PDT 24
Peak memory 202616 kb
Host smart-fd6d0be5-8eb9-4a78-b7e2-b31b90a11c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918017936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2918017936
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.696934804
Short name T452
Test name
Test status
Simulation time 31029211205 ps
CPU time 35.73 seconds
Started Apr 23 02:30:32 PM PDT 24
Finished Apr 23 02:31:08 PM PDT 24
Peak memory 202072 kb
Host smart-60e676e9-acfc-4fe5-b7a6-612c36ada80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696934804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.696934804
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3400031594
Short name T641
Test name
Test status
Simulation time 2892419544 ps
CPU time 2.57 seconds
Started Apr 23 02:30:30 PM PDT 24
Finished Apr 23 02:30:33 PM PDT 24
Peak memory 202040 kb
Host smart-9c614b2c-0f05-4691-9203-0c2fd2a7d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400031594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3400031594
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3257224121
Short name T85
Test name
Test status
Simulation time 5897980431 ps
CPU time 2.16 seconds
Started Apr 23 02:30:24 PM PDT 24
Finished Apr 23 02:30:27 PM PDT 24
Peak memory 201996 kb
Host smart-1dd21894-2263-44c3-bc99-15b559f5eadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257224121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3257224121
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.169468639
Short name T695
Test name
Test status
Simulation time 663614740947 ps
CPU time 227.58 seconds
Started Apr 23 02:30:32 PM PDT 24
Finished Apr 23 02:34:20 PM PDT 24
Peak memory 202228 kb
Host smart-dcdefd24-251b-44b3-a677-11067370ccac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169468639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
169468639
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2034508966
Short name T87
Test name
Test status
Simulation time 336021303362 ps
CPU time 316.3 seconds
Started Apr 23 02:30:32 PM PDT 24
Finished Apr 23 02:35:48 PM PDT 24
Peak memory 210988 kb
Host smart-27697fb1-91f1-4aa2-a22e-94ef9691e585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034508966 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2034508966
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.58933340
Short name T444
Test name
Test status
Simulation time 505604092 ps
CPU time 0.89 seconds
Started Apr 23 02:30:43 PM PDT 24
Finished Apr 23 02:30:44 PM PDT 24
Peak memory 201828 kb
Host smart-3629e792-0881-43ab-a086-8ededeea9a22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58933340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.58933340
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3685824254
Short name T300
Test name
Test status
Simulation time 337208858485 ps
CPU time 425.44 seconds
Started Apr 23 02:30:39 PM PDT 24
Finished Apr 23 02:37:45 PM PDT 24
Peak memory 202252 kb
Host smart-d79b7867-d38c-4ec3-8d96-e13d09c1dc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685824254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3685824254
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3379751973
Short name T476
Test name
Test status
Simulation time 165280243840 ps
CPU time 101.23 seconds
Started Apr 23 02:30:37 PM PDT 24
Finished Apr 23 02:32:19 PM PDT 24
Peak memory 202316 kb
Host smart-6c9aaa5b-6719-4021-8547-d5b91defe0dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379751973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3379751973
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1123660335
Short name T165
Test name
Test status
Simulation time 500101481992 ps
CPU time 1010.94 seconds
Started Apr 23 02:30:36 PM PDT 24
Finished Apr 23 02:47:28 PM PDT 24
Peak memory 202356 kb
Host smart-32fe8ff9-28e7-4759-97ce-68dbe5e1f482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123660335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1123660335
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.46249259
Short name T783
Test name
Test status
Simulation time 477797710542 ps
CPU time 997 seconds
Started Apr 23 02:30:34 PM PDT 24
Finished Apr 23 02:47:11 PM PDT 24
Peak memory 202248 kb
Host smart-6e52d1d6-d9b5-44a5-a3c4-4fe333ea1602
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=46249259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed
.46249259
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3557473479
Short name T323
Test name
Test status
Simulation time 345951426043 ps
CPU time 215.24 seconds
Started Apr 23 02:30:37 PM PDT 24
Finished Apr 23 02:34:13 PM PDT 24
Peak memory 202276 kb
Host smart-8152bffb-74f8-455c-9f8a-176d301064dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557473479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3557473479
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4184570707
Short name T766
Test name
Test status
Simulation time 593170948741 ps
CPU time 697.11 seconds
Started Apr 23 02:30:38 PM PDT 24
Finished Apr 23 02:42:15 PM PDT 24
Peak memory 202152 kb
Host smart-9bc5bab9-93d9-48b6-977a-cffaa349a6ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184570707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4184570707
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1845064205
Short name T724
Test name
Test status
Simulation time 75960542321 ps
CPU time 411.7 seconds
Started Apr 23 02:30:39 PM PDT 24
Finished Apr 23 02:37:31 PM PDT 24
Peak memory 202556 kb
Host smart-e01417c8-8571-4fb5-94dc-80d3ca957774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845064205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1845064205
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1789901256
Short name T595
Test name
Test status
Simulation time 40759804207 ps
CPU time 88.21 seconds
Started Apr 23 02:30:39 PM PDT 24
Finished Apr 23 02:32:08 PM PDT 24
Peak memory 202060 kb
Host smart-896cff68-ce8d-47ae-9ada-86d698c6834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789901256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1789901256
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.436285673
Short name T692
Test name
Test status
Simulation time 3464940200 ps
CPU time 4.79 seconds
Started Apr 23 02:30:37 PM PDT 24
Finished Apr 23 02:30:42 PM PDT 24
Peak memory 202000 kb
Host smart-7f0feb91-5ac0-4df8-8e96-28d849df7070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436285673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.436285673
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1731532842
Short name T440
Test name
Test status
Simulation time 5502955838 ps
CPU time 13.16 seconds
Started Apr 23 02:30:32 PM PDT 24
Finished Apr 23 02:30:46 PM PDT 24
Peak memory 202068 kb
Host smart-c3e2cb9c-9f40-46dd-95fa-bd4029355135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731532842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1731532842
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2904500942
Short name T734
Test name
Test status
Simulation time 362856456511 ps
CPU time 843.39 seconds
Started Apr 23 02:30:39 PM PDT 24
Finished Apr 23 02:44:43 PM PDT 24
Peak memory 202284 kb
Host smart-24ba473a-ca15-4944-80a8-64f90a25a2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904500942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2904500942
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.20554439
Short name T706
Test name
Test status
Simulation time 19317161498 ps
CPU time 73.04 seconds
Started Apr 23 02:30:40 PM PDT 24
Finished Apr 23 02:31:53 PM PDT 24
Peak memory 210960 kb
Host smart-b9361f3f-043b-4030-a5c6-530b4b7f3cde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20554439 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.20554439
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2042807566
Short name T349
Test name
Test status
Simulation time 460900106 ps
CPU time 1.65 seconds
Started Apr 23 02:30:53 PM PDT 24
Finished Apr 23 02:30:54 PM PDT 24
Peak memory 201924 kb
Host smart-4e507578-b35a-47e4-a154-438eb3db3d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042807566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2042807566
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2138209028
Short name T467
Test name
Test status
Simulation time 177991215468 ps
CPU time 201.96 seconds
Started Apr 23 02:30:50 PM PDT 24
Finished Apr 23 02:34:12 PM PDT 24
Peak memory 202244 kb
Host smart-8d487efb-3339-49cd-85f1-b8ed31499991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138209028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2138209028
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1180433247
Short name T156
Test name
Test status
Simulation time 479587703709 ps
CPU time 277.79 seconds
Started Apr 23 02:30:43 PM PDT 24
Finished Apr 23 02:35:21 PM PDT 24
Peak memory 202184 kb
Host smart-0536b009-ff55-49ad-a76d-86128192c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180433247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1180433247
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3104683161
Short name T794
Test name
Test status
Simulation time 503171524213 ps
CPU time 1137.84 seconds
Started Apr 23 02:30:44 PM PDT 24
Finished Apr 23 02:49:42 PM PDT 24
Peak memory 202192 kb
Host smart-45da0537-ae3b-4921-9f90-2e2622e940ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104683161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3104683161
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.457986237
Short name T215
Test name
Test status
Simulation time 485598914012 ps
CPU time 536.9 seconds
Started Apr 23 02:30:42 PM PDT 24
Finished Apr 23 02:39:39 PM PDT 24
Peak memory 202340 kb
Host smart-e571a3a5-ff1f-4d21-ac55-0c4a0bde2d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457986237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.457986237
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.292913117
Short name T178
Test name
Test status
Simulation time 335367585614 ps
CPU time 354.4 seconds
Started Apr 23 02:30:42 PM PDT 24
Finished Apr 23 02:36:37 PM PDT 24
Peak memory 202312 kb
Host smart-5eb6626a-cc5f-4ff2-be54-872315804fd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=292913117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.292913117
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.972681331
Short name T160
Test name
Test status
Simulation time 361282304347 ps
CPU time 144.2 seconds
Started Apr 23 02:30:46 PM PDT 24
Finished Apr 23 02:33:10 PM PDT 24
Peak memory 202260 kb
Host smart-ea101ec5-32cb-4bcd-9847-6b77bcd76220
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972681331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.972681331
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4065092083
Short name T501
Test name
Test status
Simulation time 193874353499 ps
CPU time 112.87 seconds
Started Apr 23 02:30:44 PM PDT 24
Finished Apr 23 02:32:37 PM PDT 24
Peak memory 202180 kb
Host smart-b3d33125-c956-4367-b4f4-e7c7b3d25462
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065092083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4065092083
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2533236114
Short name T202
Test name
Test status
Simulation time 116095054790 ps
CPU time 639.06 seconds
Started Apr 23 02:30:52 PM PDT 24
Finished Apr 23 02:41:31 PM PDT 24
Peak memory 202476 kb
Host smart-12d83535-4474-46c9-ba36-db08bc4e2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533236114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2533236114
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2849492113
Short name T544
Test name
Test status
Simulation time 24805469141 ps
CPU time 60.04 seconds
Started Apr 23 02:30:52 PM PDT 24
Finished Apr 23 02:31:52 PM PDT 24
Peak memory 201904 kb
Host smart-cc3b65be-008a-4c9a-8618-47115ffb4052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849492113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2849492113
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4018461696
Short name T356
Test name
Test status
Simulation time 5472541152 ps
CPU time 3.84 seconds
Started Apr 23 02:30:51 PM PDT 24
Finished Apr 23 02:30:55 PM PDT 24
Peak memory 201996 kb
Host smart-e4dfb660-233e-4363-af69-727caedbfd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018461696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4018461696
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3608460417
Short name T472
Test name
Test status
Simulation time 5752344581 ps
CPU time 13.34 seconds
Started Apr 23 02:30:43 PM PDT 24
Finished Apr 23 02:30:56 PM PDT 24
Peak memory 202008 kb
Host smart-208d4618-36ff-4b27-bf0d-a465427e23cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608460417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3608460417
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.213743540
Short name T618
Test name
Test status
Simulation time 333035001993 ps
CPU time 508.99 seconds
Started Apr 23 02:30:49 PM PDT 24
Finished Apr 23 02:39:18 PM PDT 24
Peak memory 202316 kb
Host smart-06531bfc-3c7f-4698-83ec-fb67691834f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213743540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
213743540
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.464816511
Short name T299
Test name
Test status
Simulation time 203090953799 ps
CPU time 122.74 seconds
Started Apr 23 02:30:51 PM PDT 24
Finished Apr 23 02:32:54 PM PDT 24
Peak memory 218596 kb
Host smart-3fa08663-b79a-4ba6-bddb-40c058ed8de9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464816511 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.464816511
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3156280111
Short name T505
Test name
Test status
Simulation time 450044993 ps
CPU time 0.71 seconds
Started Apr 23 02:31:02 PM PDT 24
Finished Apr 23 02:31:03 PM PDT 24
Peak memory 202036 kb
Host smart-53c2fe29-d8ce-4ce2-a17a-56e73891c8d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156280111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3156280111
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.647136789
Short name T266
Test name
Test status
Simulation time 163294264855 ps
CPU time 82.42 seconds
Started Apr 23 02:30:59 PM PDT 24
Finished Apr 23 02:32:22 PM PDT 24
Peak memory 202280 kb
Host smart-420a1cfb-8303-4c27-9159-7c920b65680d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647136789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.647136789
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3601453868
Short name T499
Test name
Test status
Simulation time 328208667103 ps
CPU time 211.96 seconds
Started Apr 23 02:31:00 PM PDT 24
Finished Apr 23 02:34:32 PM PDT 24
Peak memory 202248 kb
Host smart-53d30aee-286a-43fa-bb0c-a87b64f9829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601453868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3601453868
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.229368930
Short name T417
Test name
Test status
Simulation time 170046088366 ps
CPU time 48.85 seconds
Started Apr 23 02:30:56 PM PDT 24
Finished Apr 23 02:31:45 PM PDT 24
Peak memory 202252 kb
Host smart-f6edd206-788a-44cb-8cf2-2a5c9e5be315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229368930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.229368930
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.176764817
Short name T626
Test name
Test status
Simulation time 332098242049 ps
CPU time 350.3 seconds
Started Apr 23 02:30:56 PM PDT 24
Finished Apr 23 02:36:47 PM PDT 24
Peak memory 202204 kb
Host smart-1d4d6b7e-8d4b-45d6-90a1-61601a0d1a42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=176764817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.176764817
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3750200648
Short name T661
Test name
Test status
Simulation time 328405495507 ps
CPU time 144.51 seconds
Started Apr 23 02:30:55 PM PDT 24
Finished Apr 23 02:33:20 PM PDT 24
Peak memory 202268 kb
Host smart-f8982b2c-bdbf-4dc9-91dd-d7b3699ec790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750200648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3750200648
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3319953327
Short name T463
Test name
Test status
Simulation time 491689385928 ps
CPU time 286.25 seconds
Started Apr 23 02:30:56 PM PDT 24
Finished Apr 23 02:35:43 PM PDT 24
Peak memory 202200 kb
Host smart-65a7c9db-ad25-4f57-b020-8718e8cba0f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319953327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3319953327
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2812197048
Short name T739
Test name
Test status
Simulation time 221533734549 ps
CPU time 192.46 seconds
Started Apr 23 02:30:55 PM PDT 24
Finished Apr 23 02:34:08 PM PDT 24
Peak memory 202260 kb
Host smart-0df1a456-b05f-4a74-944b-34a01d2cbfce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812197048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2812197048
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2118638532
Short name T433
Test name
Test status
Simulation time 193745849743 ps
CPU time 82.82 seconds
Started Apr 23 02:30:56 PM PDT 24
Finished Apr 23 02:32:19 PM PDT 24
Peak memory 202156 kb
Host smart-7660896e-ce38-4cb5-8837-b7168a2307a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118638532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2118638532
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.72506012
Short name T88
Test name
Test status
Simulation time 133289587125 ps
CPU time 502.06 seconds
Started Apr 23 02:30:59 PM PDT 24
Finished Apr 23 02:39:22 PM PDT 24
Peak memory 202516 kb
Host smart-f321e4dc-9550-4d7a-b17e-57a3e0de3883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72506012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.72506012
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4176665408
Short name T687
Test name
Test status
Simulation time 27982093762 ps
CPU time 7.1 seconds
Started Apr 23 02:31:00 PM PDT 24
Finished Apr 23 02:31:07 PM PDT 24
Peak memory 202072 kb
Host smart-09e00f13-fc81-4049-973d-e27a67c855b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176665408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4176665408
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2001396457
Short name T584
Test name
Test status
Simulation time 4443889666 ps
CPU time 10.73 seconds
Started Apr 23 02:31:00 PM PDT 24
Finished Apr 23 02:31:11 PM PDT 24
Peak memory 201944 kb
Host smart-de71c879-a9d7-4072-ac28-197c9a45d4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001396457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2001396457
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.844771596
Short name T502
Test name
Test status
Simulation time 5596514125 ps
CPU time 4.18 seconds
Started Apr 23 02:30:52 PM PDT 24
Finished Apr 23 02:30:56 PM PDT 24
Peak memory 202076 kb
Host smart-b7a9f821-35ce-4c19-9130-a62b8eed64e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844771596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.844771596
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.66031912
Short name T541
Test name
Test status
Simulation time 86926773199 ps
CPU time 50.93 seconds
Started Apr 23 02:31:05 PM PDT 24
Finished Apr 23 02:31:56 PM PDT 24
Peak memory 201908 kb
Host smart-07849228-13a4-4e6a-b914-c9742ff22001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66031912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.66031912
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4191186481
Short name T267
Test name
Test status
Simulation time 97258242982 ps
CPU time 332.84 seconds
Started Apr 23 02:31:05 PM PDT 24
Finished Apr 23 02:36:38 PM PDT 24
Peak memory 202900 kb
Host smart-b2064843-94a5-41d2-952c-c9237407a873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191186481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.4191186481
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2758107757
Short name T482
Test name
Test status
Simulation time 393498085 ps
CPU time 0.82 seconds
Started Apr 23 02:31:19 PM PDT 24
Finished Apr 23 02:31:20 PM PDT 24
Peak memory 201952 kb
Host smart-134cdfff-ee1d-47ac-97e6-1117bf60de15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758107757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2758107757
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2028893428
Short name T773
Test name
Test status
Simulation time 328802623361 ps
CPU time 498.52 seconds
Started Apr 23 02:31:05 PM PDT 24
Finished Apr 23 02:39:24 PM PDT 24
Peak memory 202244 kb
Host smart-aea7cd92-50e3-4b5b-bd34-dc3c6377c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028893428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2028893428
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.714183649
Short name T713
Test name
Test status
Simulation time 169125476398 ps
CPU time 27.6 seconds
Started Apr 23 02:31:06 PM PDT 24
Finished Apr 23 02:31:34 PM PDT 24
Peak memory 202260 kb
Host smart-2ddb0490-42a4-4579-af90-fbebed396056
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=714183649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.714183649
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2318436215
Short name T750
Test name
Test status
Simulation time 324640716636 ps
CPU time 201 seconds
Started Apr 23 02:31:03 PM PDT 24
Finished Apr 23 02:34:25 PM PDT 24
Peak memory 202316 kb
Host smart-523958e1-872f-4f1b-bf1a-a636eab87233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318436215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2318436215
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2550241406
Short name T407
Test name
Test status
Simulation time 325971281299 ps
CPU time 137.71 seconds
Started Apr 23 02:31:06 PM PDT 24
Finished Apr 23 02:33:24 PM PDT 24
Peak memory 202068 kb
Host smart-67588021-ffa4-46a5-8266-2354f7b42b3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550241406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2550241406
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1842214528
Short name T338
Test name
Test status
Simulation time 374010564908 ps
CPU time 219.34 seconds
Started Apr 23 02:31:08 PM PDT 24
Finished Apr 23 02:34:48 PM PDT 24
Peak memory 202252 kb
Host smart-9f29fbe5-0b02-4f69-803b-7fdeac6af852
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842214528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1842214528
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.473914545
Short name T604
Test name
Test status
Simulation time 192718900755 ps
CPU time 30.48 seconds
Started Apr 23 02:31:05 PM PDT 24
Finished Apr 23 02:31:36 PM PDT 24
Peak memory 202248 kb
Host smart-e948adfb-6efd-4dd8-b6e1-f026b8dae835
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473914545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.473914545
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4045042025
Short name T361
Test name
Test status
Simulation time 47425070975 ps
CPU time 22.57 seconds
Started Apr 23 02:31:08 PM PDT 24
Finished Apr 23 02:31:31 PM PDT 24
Peak memory 202084 kb
Host smart-22abc9b4-1c2a-4346-be3b-3b9aefa847e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045042025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.4045042025
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.141463434
Short name T498
Test name
Test status
Simulation time 4797566199 ps
CPU time 12.36 seconds
Started Apr 23 02:31:07 PM PDT 24
Finished Apr 23 02:31:20 PM PDT 24
Peak memory 202040 kb
Host smart-310c2802-1ce5-4f5d-8586-04f49803c521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141463434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.141463434
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3320488327
Short name T600
Test name
Test status
Simulation time 5711713127 ps
CPU time 13.94 seconds
Started Apr 23 02:31:03 PM PDT 24
Finished Apr 23 02:31:18 PM PDT 24
Peak memory 202044 kb
Host smart-132c9f83-4c32-4e1d-90f6-0f1be356159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320488327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3320488327
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1263540507
Short name T614
Test name
Test status
Simulation time 141336985088 ps
CPU time 374.13 seconds
Started Apr 23 02:31:08 PM PDT 24
Finished Apr 23 02:37:22 PM PDT 24
Peak memory 202532 kb
Host smart-6f511968-9ad3-4f46-be46-03fc5cc5ebe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263540507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1263540507
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4038520821
Short name T385
Test name
Test status
Simulation time 422675220 ps
CPU time 0.84 seconds
Started Apr 23 02:31:22 PM PDT 24
Finished Apr 23 02:31:23 PM PDT 24
Peak memory 201960 kb
Host smart-2dcd1b17-edce-40d9-a608-7497c4c3f76a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038520821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4038520821
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1668173868
Short name T135
Test name
Test status
Simulation time 167992400973 ps
CPU time 354.27 seconds
Started Apr 23 02:31:16 PM PDT 24
Finished Apr 23 02:37:11 PM PDT 24
Peak memory 202188 kb
Host smart-6cabc846-f4cd-4b72-8ed3-a2bdfc9c50db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668173868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1668173868
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.506477122
Short name T539
Test name
Test status
Simulation time 178519685703 ps
CPU time 137.88 seconds
Started Apr 23 02:31:20 PM PDT 24
Finished Apr 23 02:33:38 PM PDT 24
Peak memory 202196 kb
Host smart-97615675-1026-4941-89e8-8f1efa1c6ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506477122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.506477122
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1074557823
Short name T530
Test name
Test status
Simulation time 162476600524 ps
CPU time 108.16 seconds
Started Apr 23 02:31:17 PM PDT 24
Finished Apr 23 02:33:05 PM PDT 24
Peak memory 202184 kb
Host smart-d4d134c5-cec1-42d1-a6d9-6c647db410ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074557823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1074557823
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1958245963
Short name T422
Test name
Test status
Simulation time 485463697816 ps
CPU time 551.78 seconds
Started Apr 23 02:31:14 PM PDT 24
Finished Apr 23 02:40:27 PM PDT 24
Peak memory 202308 kb
Host smart-38348c66-c0e9-460f-85e0-42c4c42d7e55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958245963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1958245963
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1009591130
Short name T307
Test name
Test status
Simulation time 486051946552 ps
CPU time 1132.82 seconds
Started Apr 23 02:31:11 PM PDT 24
Finished Apr 23 02:50:04 PM PDT 24
Peak memory 202332 kb
Host smart-ad8c06b9-0bc2-4d7c-8b79-38c58345bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009591130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1009591130
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4279210655
Short name T786
Test name
Test status
Simulation time 501770218322 ps
CPU time 305.49 seconds
Started Apr 23 02:31:16 PM PDT 24
Finished Apr 23 02:36:23 PM PDT 24
Peak memory 202200 kb
Host smart-5765bac0-a29e-4ac2-92ae-402ff471e749
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279210655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4279210655
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3713261584
Short name T304
Test name
Test status
Simulation time 572467918739 ps
CPU time 723.79 seconds
Started Apr 23 02:31:17 PM PDT 24
Finished Apr 23 02:43:21 PM PDT 24
Peak memory 202180 kb
Host smart-005fd00d-f9c6-4d31-bf3a-27c99d0ffa6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713261584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3713261584
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1055287180
Short name T784
Test name
Test status
Simulation time 200419876576 ps
CPU time 130.9 seconds
Started Apr 23 02:31:16 PM PDT 24
Finished Apr 23 02:33:27 PM PDT 24
Peak memory 202260 kb
Host smart-4f66f50a-9e46-4347-85f1-5cb96e7eef99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055287180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1055287180
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2843978274
Short name T49
Test name
Test status
Simulation time 75107739317 ps
CPU time 386.67 seconds
Started Apr 23 02:31:23 PM PDT 24
Finished Apr 23 02:37:50 PM PDT 24
Peak memory 202604 kb
Host smart-e7586122-8251-4f7a-815b-e8c5c26abd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843978274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2843978274
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3167663286
Short name T556
Test name
Test status
Simulation time 33879335038 ps
CPU time 78.52 seconds
Started Apr 23 02:31:19 PM PDT 24
Finished Apr 23 02:32:38 PM PDT 24
Peak memory 202064 kb
Host smart-2b602380-a911-4402-9144-e99f44ac9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167663286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3167663286
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3894928164
Short name T678
Test name
Test status
Simulation time 4293018045 ps
CPU time 2.34 seconds
Started Apr 23 02:31:22 PM PDT 24
Finished Apr 23 02:31:25 PM PDT 24
Peak memory 202056 kb
Host smart-f5c610e1-fdfb-4844-bae9-9bcfc4c3a52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894928164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3894928164
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.903882688
Short name T649
Test name
Test status
Simulation time 5676871649 ps
CPU time 3.76 seconds
Started Apr 23 02:31:10 PM PDT 24
Finished Apr 23 02:31:14 PM PDT 24
Peak memory 202028 kb
Host smart-5d6a93e5-a11d-4933-bdbe-37f19884597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903882688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.903882688
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2804992807
Short name T146
Test name
Test status
Simulation time 339178995429 ps
CPU time 842.23 seconds
Started Apr 23 02:31:22 PM PDT 24
Finished Apr 23 02:45:25 PM PDT 24
Peak memory 202280 kb
Host smart-b793dd7e-acc9-4206-92ce-1244f0fcf1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804992807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2804992807
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3756877986
Short name T36
Test name
Test status
Simulation time 96753249986 ps
CPU time 55.52 seconds
Started Apr 23 02:31:23 PM PDT 24
Finished Apr 23 02:32:19 PM PDT 24
Peak memory 211632 kb
Host smart-b6bf601f-56a8-4246-8256-ab4e8cd8fa97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756877986 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3756877986
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.218645827
Short name T397
Test name
Test status
Simulation time 436772126 ps
CPU time 0.82 seconds
Started Apr 23 02:31:47 PM PDT 24
Finished Apr 23 02:31:49 PM PDT 24
Peak memory 201920 kb
Host smart-6cca8ff9-4bbf-41a7-b207-2b68d39fd0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218645827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.218645827
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3637366800
Short name T235
Test name
Test status
Simulation time 349167146183 ps
CPU time 417.11 seconds
Started Apr 23 02:31:34 PM PDT 24
Finished Apr 23 02:38:32 PM PDT 24
Peak memory 202264 kb
Host smart-6b331620-36a5-4dd6-838b-7f8ab9bbf283
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637366800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3637366800
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3890763694
Short name T322
Test name
Test status
Simulation time 347854897529 ps
CPU time 395.63 seconds
Started Apr 23 02:31:35 PM PDT 24
Finished Apr 23 02:38:12 PM PDT 24
Peak memory 202192 kb
Host smart-038b9206-b75f-48c9-94d6-2ab97c6d767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890763694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3890763694
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1082792624
Short name T371
Test name
Test status
Simulation time 162729561782 ps
CPU time 92.1 seconds
Started Apr 23 02:31:26 PM PDT 24
Finished Apr 23 02:32:58 PM PDT 24
Peak memory 202284 kb
Host smart-58e83a93-23d7-455f-b69e-09ed9fd772a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082792624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1082792624
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1452706449
Short name T447
Test name
Test status
Simulation time 331942931374 ps
CPU time 238.58 seconds
Started Apr 23 02:31:28 PM PDT 24
Finished Apr 23 02:35:27 PM PDT 24
Peak memory 202244 kb
Host smart-941d9367-4a88-492f-843c-3970b1e95862
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452706449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1452706449
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2007773489
Short name T609
Test name
Test status
Simulation time 167229869244 ps
CPU time 180.4 seconds
Started Apr 23 02:31:27 PM PDT 24
Finished Apr 23 02:34:27 PM PDT 24
Peak memory 202240 kb
Host smart-4058cf48-bc1a-4ae8-889e-0ee5b97da95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007773489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2007773489
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.411089475
Short name T760
Test name
Test status
Simulation time 331625392991 ps
CPU time 755.76 seconds
Started Apr 23 02:31:26 PM PDT 24
Finished Apr 23 02:44:02 PM PDT 24
Peak memory 202244 kb
Host smart-59fded02-7d9e-4d7f-8a45-324e607479e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=411089475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.411089475
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2507803211
Short name T601
Test name
Test status
Simulation time 179133502735 ps
CPU time 452.14 seconds
Started Apr 23 02:31:34 PM PDT 24
Finished Apr 23 02:39:07 PM PDT 24
Peak memory 202308 kb
Host smart-7804cdd9-b0c5-4c9a-ad6f-844b8c0239f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507803211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2507803211
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.4003324000
Short name T719
Test name
Test status
Simulation time 405119000036 ps
CPU time 911.87 seconds
Started Apr 23 02:31:34 PM PDT 24
Finished Apr 23 02:46:46 PM PDT 24
Peak memory 202260 kb
Host smart-dfac166d-07cc-451c-9009-18cf667a82f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003324000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.4003324000
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3542456784
Short name T186
Test name
Test status
Simulation time 116333499497 ps
CPU time 411.19 seconds
Started Apr 23 02:31:36 PM PDT 24
Finished Apr 23 02:38:28 PM PDT 24
Peak memory 202496 kb
Host smart-d2164aa9-4a18-4d40-b70b-3cb2d798a36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542456784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3542456784
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1427217647
Short name T354
Test name
Test status
Simulation time 40302735232 ps
CPU time 27.45 seconds
Started Apr 23 02:31:38 PM PDT 24
Finished Apr 23 02:32:05 PM PDT 24
Peak memory 202004 kb
Host smart-f2211013-4cd0-4410-abf4-08284e594fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427217647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1427217647
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.621225770
Short name T677
Test name
Test status
Simulation time 4634875307 ps
CPU time 4.53 seconds
Started Apr 23 02:31:37 PM PDT 24
Finished Apr 23 02:31:42 PM PDT 24
Peak memory 202156 kb
Host smart-c86cf100-95e6-4a80-8a8c-2e87fe0b90c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621225770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.621225770
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3320789148
Short name T408
Test name
Test status
Simulation time 5742997817 ps
CPU time 4.67 seconds
Started Apr 23 02:31:26 PM PDT 24
Finished Apr 23 02:31:31 PM PDT 24
Peak memory 202084 kb
Host smart-e1654fc3-0072-48a6-81b0-a967534c57d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320789148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3320789148
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3713042230
Short name T455
Test name
Test status
Simulation time 98851508821 ps
CPU time 25.9 seconds
Started Apr 23 02:31:39 PM PDT 24
Finished Apr 23 02:32:06 PM PDT 24
Peak memory 202312 kb
Host smart-1d7a46c1-d083-49d9-8390-5110f3d76b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713042230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3713042230
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3426474018
Short name T690
Test name
Test status
Simulation time 353404601 ps
CPU time 1.48 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:26:06 PM PDT 24
Peak memory 201956 kb
Host smart-4d942768-ec96-4a74-a4a5-64a1bf484732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426474018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3426474018
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1186296881
Short name T157
Test name
Test status
Simulation time 509951164955 ps
CPU time 213.11 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:29:37 PM PDT 24
Peak memory 202168 kb
Host smart-bb592efb-4167-48ca-83a8-b55013df5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186296881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1186296881
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.541885967
Short name T588
Test name
Test status
Simulation time 496239111450 ps
CPU time 71.35 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:27:32 PM PDT 24
Peak memory 202100 kb
Host smart-502695c3-c6fc-4ec9-9fad-ef178a88a049
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=541885967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.541885967
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.917893201
Short name T327
Test name
Test status
Simulation time 327333050075 ps
CPU time 817.56 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:39:43 PM PDT 24
Peak memory 202316 kb
Host smart-38ce9e64-e2c9-4ad0-ae9e-a1f880219ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917893201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.917893201
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.313777479
Short name T630
Test name
Test status
Simulation time 333380175295 ps
CPU time 192.76 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:29:33 PM PDT 24
Peak memory 202044 kb
Host smart-66656790-5f4e-45c8-bdc6-058368df6e45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=313777479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.313777479
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.97118311
Short name T93
Test name
Test status
Simulation time 363844819044 ps
CPU time 66.51 seconds
Started Apr 23 02:26:10 PM PDT 24
Finished Apr 23 02:27:17 PM PDT 24
Peak memory 202244 kb
Host smart-3053f6e6-af4a-44ec-a2c3-cec199da9282
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97118311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wa
keup.97118311
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1199218153
Short name T714
Test name
Test status
Simulation time 210229944098 ps
CPU time 458.27 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:33:56 PM PDT 24
Peak memory 202056 kb
Host smart-f8f1760d-7df7-4eaf-b9da-38fb75d67e85
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199218153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1199218153
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3998165238
Short name T191
Test name
Test status
Simulation time 116649263144 ps
CPU time 610.8 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:36:24 PM PDT 24
Peak memory 202620 kb
Host smart-0c9f6865-16a3-48e6-99a0-823bd1753432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998165238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3998165238
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2991780647
Short name T445
Test name
Test status
Simulation time 30975639024 ps
CPU time 36.18 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:26:40 PM PDT 24
Peak memory 202048 kb
Host smart-5cf1f1e3-ec5a-410b-bdc1-a60f242f2512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991780647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2991780647
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3727770269
Short name T355
Test name
Test status
Simulation time 3220444626 ps
CPU time 8.01 seconds
Started Apr 23 02:26:18 PM PDT 24
Finished Apr 23 02:26:28 PM PDT 24
Peak memory 201888 kb
Host smart-5fd82629-5858-45c6-b50b-c4dfc7e528e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727770269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3727770269
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3048906987
Short name T343
Test name
Test status
Simulation time 6053622300 ps
CPU time 3.21 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:26:17 PM PDT 24
Peak memory 202076 kb
Host smart-16e477ec-2c37-4f2c-aa3b-c87f344146c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048906987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3048906987
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2378069252
Short name T37
Test name
Test status
Simulation time 484901142769 ps
CPU time 220.07 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:29:54 PM PDT 24
Peak memory 202268 kb
Host smart-afda9ad7-0abe-4106-a351-8fa042bdddb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378069252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2378069252
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.491116423
Short name T23
Test name
Test status
Simulation time 150546555940 ps
CPU time 84.04 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:27:28 PM PDT 24
Peak memory 210524 kb
Host smart-0c9034fc-6ee1-4510-a065-003f752b916e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491116423 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.491116423
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2729798743
Short name T781
Test name
Test status
Simulation time 312864112 ps
CPU time 0.84 seconds
Started Apr 23 02:26:06 PM PDT 24
Finished Apr 23 02:26:08 PM PDT 24
Peak memory 201928 kb
Host smart-1eb7b904-9d3b-4c19-afd8-1af17688811c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729798743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2729798743
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2104521898
Short name T256
Test name
Test status
Simulation time 664750194218 ps
CPU time 209.98 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:29:35 PM PDT 24
Peak memory 202232 kb
Host smart-e6a33675-baa8-4349-8382-b757c756c495
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104521898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2104521898
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3614376306
Short name T425
Test name
Test status
Simulation time 335169185007 ps
CPU time 846.57 seconds
Started Apr 23 02:26:10 PM PDT 24
Finished Apr 23 02:40:17 PM PDT 24
Peak memory 202348 kb
Host smart-0b333598-2c3a-47e7-b139-db048bff9cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614376306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3614376306
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1147946127
Short name T538
Test name
Test status
Simulation time 339077768314 ps
CPU time 791.38 seconds
Started Apr 23 02:26:10 PM PDT 24
Finished Apr 23 02:39:22 PM PDT 24
Peak memory 202232 kb
Host smart-cb2be59b-7285-47d2-9042-15f50bef2d7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147946127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1147946127
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.216007695
Short name T360
Test name
Test status
Simulation time 161988540539 ps
CPU time 363.11 seconds
Started Apr 23 02:26:03 PM PDT 24
Finished Apr 23 02:32:07 PM PDT 24
Peak memory 202280 kb
Host smart-dff3caec-632f-4b3d-b397-cee2de8cf0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216007695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.216007695
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.4283743615
Short name T454
Test name
Test status
Simulation time 163286037463 ps
CPU time 375.62 seconds
Started Apr 23 02:26:00 PM PDT 24
Finished Apr 23 02:32:17 PM PDT 24
Peak memory 202240 kb
Host smart-c609b6e3-a53c-4414-96d0-3872608063b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283743615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.4283743615
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3480532636
Short name T288
Test name
Test status
Simulation time 555562792543 ps
CPU time 1285.72 seconds
Started Apr 23 02:26:06 PM PDT 24
Finished Apr 23 02:47:32 PM PDT 24
Peak memory 202276 kb
Host smart-3191165e-6c90-4bec-8167-805458c44192
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480532636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3480532636
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4289384767
Short name T663
Test name
Test status
Simulation time 194161322853 ps
CPU time 107.71 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:27:58 PM PDT 24
Peak memory 202156 kb
Host smart-a084009c-9d63-4c9d-b85a-d77dd53043f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289384767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4289384767
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.42309317
Short name T31
Test name
Test status
Simulation time 121233072246 ps
CPU time 604.34 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:36:09 PM PDT 24
Peak memory 202532 kb
Host smart-0f64c798-fb94-4275-90f5-51015a3ddbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42309317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.42309317
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4289301403
Short name T403
Test name
Test status
Simulation time 31181470417 ps
CPU time 20.1 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:26:26 PM PDT 24
Peak memory 202092 kb
Host smart-4ce929cf-b80e-4ab0-aeeb-7942e6c6485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289301403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4289301403
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1818581994
Short name T480
Test name
Test status
Simulation time 5622155926 ps
CPU time 7.18 seconds
Started Apr 23 02:26:06 PM PDT 24
Finished Apr 23 02:26:13 PM PDT 24
Peak memory 202052 kb
Host smart-0739d47d-6639-4b8e-8f52-f35961146acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818581994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1818581994
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.550671619
Short name T2
Test name
Test status
Simulation time 6091357589 ps
CPU time 15.75 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:26:21 PM PDT 24
Peak memory 202044 kb
Host smart-dc017d3e-340e-4ee5-8dde-9df456f65b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550671619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.550671619
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3021524824
Short name T639
Test name
Test status
Simulation time 671087117076 ps
CPU time 282.41 seconds
Started Apr 23 02:26:08 PM PDT 24
Finished Apr 23 02:30:52 PM PDT 24
Peak memory 202340 kb
Host smart-aeba039e-03e2-47a4-81ce-0d9bc4288cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021524824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3021524824
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2487046970
Short name T12
Test name
Test status
Simulation time 265369104647 ps
CPU time 134.43 seconds
Started Apr 23 02:26:06 PM PDT 24
Finished Apr 23 02:28:21 PM PDT 24
Peak memory 210884 kb
Host smart-3d9c56a4-717d-479a-a57d-fdf3fe4c6644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487046970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2487046970
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2706402342
Short name T743
Test name
Test status
Simulation time 517331178 ps
CPU time 1.23 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:26:11 PM PDT 24
Peak memory 201980 kb
Host smart-f7f98b1c-957e-4b13-8e94-13e3387ec07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706402342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2706402342
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.650631733
Short name T11
Test name
Test status
Simulation time 187071427888 ps
CPU time 123.2 seconds
Started Apr 23 02:26:06 PM PDT 24
Finished Apr 23 02:28:10 PM PDT 24
Peak memory 202300 kb
Host smart-2f573428-1811-47f5-960f-e26e5be370d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650631733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.650631733
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.296848995
Short name T167
Test name
Test status
Simulation time 485449391352 ps
CPU time 181.62 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:29:07 PM PDT 24
Peak memory 202304 kb
Host smart-55484f65-dc5c-4dcb-a6ec-cb8a3c8bb7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296848995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.296848995
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.494316374
Short name T628
Test name
Test status
Simulation time 499500176527 ps
CPU time 83.71 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:27:28 PM PDT 24
Peak memory 202232 kb
Host smart-f8f3963f-7481-4c30-ad8a-300951a8ffcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=494316374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.494316374
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4280033395
Short name T448
Test name
Test status
Simulation time 165474538050 ps
CPU time 97.36 seconds
Started Apr 23 02:26:06 PM PDT 24
Finished Apr 23 02:27:44 PM PDT 24
Peak memory 202328 kb
Host smart-416ef45f-be6f-47a4-a2fd-4a194f2266ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280033395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4280033395
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2216910316
Short name T495
Test name
Test status
Simulation time 404123304584 ps
CPU time 130.83 seconds
Started Apr 23 02:26:11 PM PDT 24
Finished Apr 23 02:28:23 PM PDT 24
Peak memory 202276 kb
Host smart-2882777a-dddf-4b3d-be26-68a43b065386
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216910316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2216910316
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.231240205
Short name T1
Test name
Test status
Simulation time 109458403964 ps
CPU time 344.94 seconds
Started Apr 23 02:26:07 PM PDT 24
Finished Apr 23 02:31:52 PM PDT 24
Peak memory 202652 kb
Host smart-e2e3cef7-8ccb-41ab-8cd4-939569c7d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231240205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.231240205
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3046371589
Short name T341
Test name
Test status
Simulation time 21148944123 ps
CPU time 5.48 seconds
Started Apr 23 02:26:04 PM PDT 24
Finished Apr 23 02:26:10 PM PDT 24
Peak memory 202056 kb
Host smart-6933e515-7205-4826-8088-bab51532ef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046371589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3046371589
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4209323289
Short name T477
Test name
Test status
Simulation time 3092887054 ps
CPU time 2.59 seconds
Started Apr 23 02:26:08 PM PDT 24
Finished Apr 23 02:26:12 PM PDT 24
Peak memory 202000 kb
Host smart-0cc8db46-318b-4217-a120-ecf17db6eea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209323289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4209323289
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2812051176
Short name T394
Test name
Test status
Simulation time 5857648734 ps
CPU time 9.04 seconds
Started Apr 23 02:26:05 PM PDT 24
Finished Apr 23 02:26:14 PM PDT 24
Peak memory 202068 kb
Host smart-df47ada8-d9d2-4c7b-8196-f410bd41f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812051176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2812051176
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.752624081
Short name T197
Test name
Test status
Simulation time 265429395372 ps
CPU time 640.27 seconds
Started Apr 23 02:26:07 PM PDT 24
Finished Apr 23 02:36:48 PM PDT 24
Peak memory 202572 kb
Host smart-fe85e310-f0aa-4d7f-9ad3-45f4b1463ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752624081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.752624081
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1633592254
Short name T71
Test name
Test status
Simulation time 382876247 ps
CPU time 1.03 seconds
Started Apr 23 02:26:15 PM PDT 24
Finished Apr 23 02:26:16 PM PDT 24
Peak memory 201916 kb
Host smart-542b58e7-01bc-4f86-83e7-626d0f59ca6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633592254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1633592254
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.4152776138
Short name T699
Test name
Test status
Simulation time 173599766536 ps
CPU time 203.8 seconds
Started Apr 23 02:26:12 PM PDT 24
Finished Apr 23 02:29:36 PM PDT 24
Peak memory 202284 kb
Host smart-0d9394c5-f1a3-4a05-8d20-aee3c59e34b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152776138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.4152776138
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4084162309
Short name T703
Test name
Test status
Simulation time 179886339728 ps
CPU time 215.54 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:29:46 PM PDT 24
Peak memory 202276 kb
Host smart-be4cf353-b8b6-433a-b0fe-422457230976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084162309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4084162309
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1769206205
Short name T6
Test name
Test status
Simulation time 478948470157 ps
CPU time 147.48 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:28:37 PM PDT 24
Peak memory 202252 kb
Host smart-b861d649-5543-47a1-a263-ccc2c39e0916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769206205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1769206205
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4178097475
Short name T428
Test name
Test status
Simulation time 169158312799 ps
CPU time 417.84 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:33:08 PM PDT 24
Peak memory 202268 kb
Host smart-44f5f125-3f85-4c22-9412-b01db114c718
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178097475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.4178097475
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2231707168
Short name T294
Test name
Test status
Simulation time 161258925766 ps
CPU time 357.56 seconds
Started Apr 23 02:26:12 PM PDT 24
Finished Apr 23 02:32:10 PM PDT 24
Peak memory 202332 kb
Host smart-a09fdd86-627e-426d-8734-d504032b9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231707168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2231707168
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.982005567
Short name T13
Test name
Test status
Simulation time 492254671103 ps
CPU time 746.95 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:38:40 PM PDT 24
Peak memory 202220 kb
Host smart-b372aba0-37d9-4e84-8ea7-ab6b3ffbbbf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=982005567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.982005567
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.527712472
Short name T497
Test name
Test status
Simulation time 539918087498 ps
CPU time 1257.06 seconds
Started Apr 23 02:26:11 PM PDT 24
Finished Apr 23 02:47:08 PM PDT 24
Peak memory 202248 kb
Host smart-389d798c-3a1d-4f70-b992-a7848e06f0b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527712472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.527712472
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.327517954
Short name T413
Test name
Test status
Simulation time 605581978534 ps
CPU time 371.81 seconds
Started Apr 23 02:26:07 PM PDT 24
Finished Apr 23 02:32:20 PM PDT 24
Peak memory 202212 kb
Host smart-196a9272-fb34-4c85-a73f-cc3802f395e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327517954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.327517954
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2018117147
Short name T585
Test name
Test status
Simulation time 82221456080 ps
CPU time 460.72 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:33:51 PM PDT 24
Peak memory 202612 kb
Host smart-0e42deeb-acba-4b77-8c11-c1dce168cb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018117147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2018117147
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1343561005
Short name T650
Test name
Test status
Simulation time 44681867824 ps
CPU time 72.74 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:27:23 PM PDT 24
Peak memory 201996 kb
Host smart-12e40f30-9cf7-4c85-8d14-f8d4859b31c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343561005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1343561005
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.914495977
Short name T656
Test name
Test status
Simulation time 4116693670 ps
CPU time 2.1 seconds
Started Apr 23 02:26:09 PM PDT 24
Finished Apr 23 02:26:12 PM PDT 24
Peak memory 202060 kb
Host smart-7c350241-e329-4c40-a5eb-ebaec09ae224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914495977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.914495977
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3775810000
Short name T359
Test name
Test status
Simulation time 5961942776 ps
CPU time 14.42 seconds
Started Apr 23 02:26:07 PM PDT 24
Finished Apr 23 02:26:22 PM PDT 24
Peak memory 202008 kb
Host smart-918442a7-e752-4608-9815-5f545f8547b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775810000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3775810000
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.723017487
Short name T562
Test name
Test status
Simulation time 24903486965 ps
CPU time 8.26 seconds
Started Apr 23 02:26:12 PM PDT 24
Finished Apr 23 02:26:21 PM PDT 24
Peak memory 202088 kb
Host smart-553f6577-d969-4b6a-8e5d-fb79785426da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723017487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.723017487
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1394213025
Short name T41
Test name
Test status
Simulation time 84359960128 ps
CPU time 122.18 seconds
Started Apr 23 02:26:08 PM PDT 24
Finished Apr 23 02:28:11 PM PDT 24
Peak memory 218988 kb
Host smart-dc9845d6-2a93-408c-821d-958b017b2f84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394213025 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1394213025
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1822159773
Short name T771
Test name
Test status
Simulation time 478299048 ps
CPU time 1.65 seconds
Started Apr 23 02:26:10 PM PDT 24
Finished Apr 23 02:26:12 PM PDT 24
Peak memory 201940 kb
Host smart-5ee9598c-2086-456e-8a63-e4d798d4c0c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822159773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1822159773
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.208869286
Short name T183
Test name
Test status
Simulation time 332041776995 ps
CPU time 215.37 seconds
Started Apr 23 02:26:12 PM PDT 24
Finished Apr 23 02:29:48 PM PDT 24
Peak memory 202268 kb
Host smart-1de41873-28e9-4d65-8d51-dd41daeb3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208869286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.208869286
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1278756034
Short name T770
Test name
Test status
Simulation time 167993228432 ps
CPU time 163.22 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:29:01 PM PDT 24
Peak memory 202228 kb
Host smart-6717f2d5-cb95-4410-8807-cad04020778b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278756034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1278756034
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.352269075
Short name T532
Test name
Test status
Simulation time 332295951600 ps
CPU time 830.69 seconds
Started Apr 23 02:26:12 PM PDT 24
Finished Apr 23 02:40:03 PM PDT 24
Peak memory 202320 kb
Host smart-727dc11a-fc6f-4fd9-a03a-ce720b0ab6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352269075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.352269075
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2345877572
Short name T508
Test name
Test status
Simulation time 496374552348 ps
CPU time 307.94 seconds
Started Apr 23 02:26:07 PM PDT 24
Finished Apr 23 02:31:16 PM PDT 24
Peak memory 202332 kb
Host smart-2b333128-4936-49f7-8d84-9cbd79fc4fff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345877572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2345877572
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3141435785
Short name T236
Test name
Test status
Simulation time 524141659767 ps
CPU time 1276.81 seconds
Started Apr 23 02:26:11 PM PDT 24
Finished Apr 23 02:47:28 PM PDT 24
Peak memory 202208 kb
Host smart-6a3aeac8-93aa-4237-b63e-d2cb1e24689d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141435785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3141435785
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2796171680
Short name T373
Test name
Test status
Simulation time 604942306477 ps
CPU time 1272.6 seconds
Started Apr 23 02:26:16 PM PDT 24
Finished Apr 23 02:47:29 PM PDT 24
Peak memory 202168 kb
Host smart-e0d3cd28-89de-43f8-87d6-608e5981264c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796171680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2796171680
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4211298952
Short name T188
Test name
Test status
Simulation time 101492787086 ps
CPU time 374.38 seconds
Started Apr 23 02:26:13 PM PDT 24
Finished Apr 23 02:32:28 PM PDT 24
Peak memory 202568 kb
Host smart-e4062bb6-8d79-4bf7-bdd8-3c476fe65fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211298952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4211298952
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3886439539
Short name T698
Test name
Test status
Simulation time 30472675362 ps
CPU time 64.66 seconds
Started Apr 23 02:26:11 PM PDT 24
Finished Apr 23 02:27:16 PM PDT 24
Peak memory 202052 kb
Host smart-57263cf6-f77c-48f8-a852-dfbf4bdb334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886439539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3886439539
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1174800205
Short name T415
Test name
Test status
Simulation time 3379441642 ps
CPU time 1.74 seconds
Started Apr 23 02:26:16 PM PDT 24
Finished Apr 23 02:26:19 PM PDT 24
Peak memory 202020 kb
Host smart-5ea0fa12-b48f-4390-896c-0de2ff32e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174800205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1174800205
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.772873627
Short name T384
Test name
Test status
Simulation time 6060908352 ps
CPU time 4.31 seconds
Started Apr 23 02:26:14 PM PDT 24
Finished Apr 23 02:26:19 PM PDT 24
Peak memory 202072 kb
Host smart-224dccf9-e0bd-4064-a866-57c5d4181775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772873627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.772873627
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3025800010
Short name T658
Test name
Test status
Simulation time 375305844586 ps
CPU time 843.1 seconds
Started Apr 23 02:26:17 PM PDT 24
Finished Apr 23 02:40:21 PM PDT 24
Peak memory 202228 kb
Host smart-3d826af1-9dcb-4385-8a16-b1c1d123b515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025800010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3025800010
Directory /workspace/9.adc_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%