Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7451	1			T3	44		T8	46		T43	8
testmodes[AdcCtrlTestmodeNormal]	5742	1			T2	3		T3	50		T4	3
testmodes[AdcCtrlTestmodeLowpower]	6058	1			T1	1		T3	35		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4079	1			T3	14		T8	14		T43	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1814	1			T3	23		T8	17		T43	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1450	1			T3	7		T8	15		T44	26
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1746	1			T3	15		T8	18		T43	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2070	1			T2	2		T3	15		T4	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1573	1			T3	19		T5	1		T8	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1504	1			T3	14		T8	14		T44	25
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1520	1			T3	12		T8	16		T44	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2798	1			T3	9		T6	2		T8	12