Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21656

1

T1

27

T2

33

T3

147

auto[ADC_CTRL_FILTER_COND_OUT]

5669

1

T4

2

T6

11

T7

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21584

1

T2

11

T3

129

T6

11

auto[1]

5741

1

T1

27

T2

22

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T205	11		-	-		-	-
values[0]	73	1			T78	10		T206	3		T207	21
values[1]	418	1			T4	1		T121	16		T127	2
values[2]	555	1			T6	13		T41	13		T23	1
values[3]	680	1			T5	13		T42	13		T25	15
values[4]	820	1			T2	9		T34	31		T39	8
values[5]	689	1			T39	5		T22	1		T25	18
values[6]	826	1			T34	32		T23	1		T26	10
values[7]	662	1			T3	18		T5	24		T115	5
values[8]	463	1			T4	1		T42	8		T22	9
values[9]	3816	1			T1	27		T2	24		T4	1
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	613	1			T6	13		T23	1		T131	14
values[1]	2936	1			T4	1		T7	6		T9	1
values[2]	708	1			T5	13		T26	6		T53	22
values[3]	715	1			T2	9		T39	8		T11	19
values[4]	842	1			T34	63		T39	5		T41	14
values[5]	773	1			T3	18		T23	1		T26	10
values[6]	527	1			T5	24		T208	2		T124	23
values[7]	558	1			T2	11		T11	6		T22	9
values[8]	1124	1			T1	27		T2	13		T4	2
values[9]	216	1			T41	17		T142	1		T179	1
minimum	18313	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	13		T131	14		T121	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T23	1		T74	10		T78	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	13		T127	8		T90	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1683	1			T4	1		T7	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	13		T26	6		T53	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T208	8		T209	16		T80	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	1		T39	8		T25	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	14		T121	8		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T34	30		T39	5		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	14		T129	1		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	8		T26	6		T115	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T23	1		T124	14		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T5	16		T208	1		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T124	9		T74	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	1		T129	1		T130	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	4		T22	7		T123	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T1	14		T2	1		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T4	1		T6	11		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	17		T189	1		T210	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T142	1		T179	1		T211	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18174	1			T3	128		T8	146		T47	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T121	7		T127	1		T33	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T74	4		T78	9		T207	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T127	8		T212	2		T135	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	979	1			T7	5		T92	22		T28	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T53	11		T126	2		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T209	18		T80	9		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	8		T121	10		T126	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	5		T121	9		T213	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T34	33		T131	8		T115	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T125	14		T179	2		T153	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	10		T26	4		T115	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T124	8		T128	9		T214	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T5	8		T208	1		T12	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T124	14		T48	11		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T2	10		T130	9		T215	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	2		T22	2		T123	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	13		T2	12		T26	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T131	2		T78	16		T216	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T189	1		T210	9		T173	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T211	7		T217	6		T218	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T205	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T219	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T78	1		T206	3		T207	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T121	9		T127	1		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T4	1		T74	10		T78	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	13		T131	14		T90	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	13		T23	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	13		T42	13		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T25	15		T208	8		T209	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	1		T34	14		T39	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T41	14		T11	14		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T39	5		T22	1		T25	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T121	8		T125	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T34	16		T26	6		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T23	1		T129	1		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	8		T5	16		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T124	9		T128	1		T74	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	1		T130	8		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	1		T42	8		T22	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	457	1			T1	14		T2	2		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1892	1			T6	11		T7	1		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T78	9		T207	12		T161	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T121	7		T127	1		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T74	4		T78	4		T220	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T135	9		T143	8		T221	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T31	11		T153	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T53	11		T127	8		T212	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T209	18		T80	9		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	8		T34	17		T121	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	5		T153	14		T133	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T125	4		T126	5		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T121	9		T125	14		T213	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	16		T26	4		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T124	8		T214	9		T222	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	10		T5	8		T115	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	14		T128	9		T48	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T130	9		T215	10		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T22	2		T223	1		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T1	13		T2	22		T26	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1090	1			T7	5		T92	22		T11	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T131	1		T121	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T23	1		T74	5		T78	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	1		T127	9		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1328	1			T4	1		T7	6		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T26	1		T53	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T208	1		T209	19		T80	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	9		T39	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	10		T121	10		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T34	35		T39	1		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T41	1		T129	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	11		T26	5		T115	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T23	1		T124	9		T128	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	9		T208	2		T12	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T124	15		T74	1		T48	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	11		T129	1		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	5		T22	3		T123	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T1	14		T2	13		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T4	1		T6	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T41	1		T189	2		T210	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T142	1		T179	1		T211	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18313	1			T3	129		T8	146		T47	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	12		T131	13		T121	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T74	9		T207	8		T134	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T42	12		T127	7		T90	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1334	1			T38	47		T40	40		T41	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	12		T26	5		T53	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T208	7		T209	15		T80	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	7		T25	17		T121	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T11	9		T121	7		T133	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	28		T39	4		T53	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	13		T122	11		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	7		T26	5		T115	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T124	13		T134	21		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T5	15		T12	1		T189	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T124	8		T14	1		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T130	7		T225	12		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	1		T22	6		T123	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	13		T6	15		T25	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	10		T42	7		T122	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T41	16		T210	16		T173	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T211	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T205	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T219	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T78	10		T206	3		T207	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T121	8		T127	2		T33	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T4	1		T74	5		T78	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T6	1		T131	1		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T41	1		T23	1		T31	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	1		T42	1		T53	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T25	1		T208	1		T209	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	9		T34	18		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T41	1		T11	10		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T39	1		T22	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T121	10		T125	15		T213	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T34	17		T26	5		T131	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T23	1		T129	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	11		T5	9		T115	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T124	15		T128	10		T74	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	1		T130	10		T215	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	1		T42	1		T22	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	459	1			T1	14		T2	24		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1461	1			T6	1		T7	6		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T205	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T207	8		T134	10		T185	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T121	8		T33	1		T80	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T74	9		T220	12		T226	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	12		T131	13		T90	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T41	12		T153	12		T227	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T5	12		T42	12		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T25	14		T208	7		T209	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T34	13		T39	7		T26	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T41	13		T11	9		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	4		T25	17		T53	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T121	7		T228	4		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T34	15		T26	5		T115	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T122	11		T124	13		T134	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	7		T5	15		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	8		T14	1		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T130	7		T225	12		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T42	7		T22	6		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T1	13		T6	15		T41	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1521	1			T6	10		T38	47		T40	40

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23853

1

T2

33

T3

147

T5

24

auto[ADC_CTRL_FILTER_COND_OUT]

3472

1

T1

27

T4

3

T5

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21273

1

T2

22

T3

147

T4

3

auto[1]

6052

1

T1

27

T2

11

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T39	5		T153	3		-	-
values[0]	118	1			T124	22		T230	21		T146	28
values[1]	778	1			T4	1		T5	24		T34	32
values[2]	720	1			T2	13		T6	13		T34	31
values[3]	660	1			T1	27		T4	1		T6	16
values[4]	797	1			T41	14		T26	24		T123	27
values[5]	565	1			T2	9		T39	8		T42	13
values[6]	770	1			T41	13		T25	18		T53	22
values[7]	784	1			T2	11		T3	18		T6	11
values[8]	2884	1			T4	1		T5	13		T7	6
values[9]	929	1			T41	17		T42	8		T11	6
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1124	1			T2	13		T4	1		T5	24
values[1]	605	1			T6	13		T34	31		T122	12
values[2]	704	1			T1	27		T4	1		T6	16
values[3]	778	1			T2	9		T41	14		T42	13
values[4]	612	1			T39	8		T25	18		T53	22
values[5]	683	1			T6	11		T41	13		T26	10
values[6]	3087	1			T2	11		T3	18		T7	6
values[7]	543	1			T23	1		T131	14		T121	37
values[8]	680	1			T4	1		T5	13		T41	17
values[9]	196	1			T39	5		T42	8		T25	5
minimum	18313	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	1		T5	16		T34	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T4	1		T23	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	13		T122	12		T130	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T34	14		T33	3		T89	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T123	13		T30	1		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	14		T4	1		T6	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	1		T132	11		T210	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	14		T42	13		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T39	8		T25	18		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T209	16		T35	5		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	1		T75	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	11		T41	13		T26	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T2	1		T3	8		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T22	1		T25	15		T115	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T23	1		T131	14		T121	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T121	9		T130	1		T90	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T131	1		T115	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	1		T5	13		T41	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T39	5		T25	5		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T42	8		T15	1		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T232	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	12		T5	8		T34	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T124	21		T127	8		T74	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T130	9		T189	1		T233	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T34	17		T33	2		T89	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T123	14		T12	2		T31	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	13		T11	5		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	8		T132	9		T210	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T78	9		T234	4		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T53	11		T31	3		T80	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T209	18		T35	3		T78	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T31	1		T231	4		T153	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T26	4		T121	9		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T2	10		T3	10		T7	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T115	14		T126	2		T128	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T121	10		T125	14		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T121	7		T132	9		T207	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	8		T115	4		T208	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	2		T115	9		T215	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T173	8		T221	1		T161	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T236	12		T146	7		T237	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T39	5		T153	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T124	14		T230	11		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T146	14		T238	1		T239	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	16		T34	16		T22	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T4	1		T23	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T6	13		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	14		T124	9		T127	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T130	8		T30	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	14		T4	1		T6	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T123	13		T33	4		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	14		T26	14		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	1		T39	8		T208	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T42	13		T53	8		T209	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T25	18		T53	11		T89	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	13		T121	8		T123	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	1		T3	8		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T6	11		T22	1		T25	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T7	1		T9	1		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	1		T5	13		T115	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T25	5		T115	1		T121	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T41	17		T42	8		T11	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T124	8		T230	10		T159	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T146	14		T239	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	8		T34	16		T22	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T124	7		T74	4		T235	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	12		T179	8		T233	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	17		T124	14		T127	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T130	9		T31	11		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T1	13		T11	5		T126	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T123	14		T12	2		T80	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T26	10		T78	9		T235	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T2	8		T31	3		T207	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T209	18		T35	3		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T53	11		T89	12		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T121	9		T123	11		T78	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T2	10		T3	10		T153	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T26	4		T115	14		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	920	1			T7	5		T92	22		T28	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T115	9		T121	7		T48	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T115	4		T121	10		T208	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	2		T215	10		T240	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1