Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21662

1

T1

27

T2

33

T3

147

auto[ADC_CTRL_FILTER_COND_OUT]

5663

1

T4

2

T6

11

T7

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21526

1

T2

11

T3

129

T6

11

auto[1]

5799

1

T1

27

T2

22

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	279	1			T6	16		T25	5		T127	8
values[0]	17	1			T78	10		T304	7		-	-
values[1]	456	1			T4	1		T121	16		T127	2
values[2]	543	1			T6	13		T41	13		T23	1
values[3]	737	1			T5	13		T42	13		T25	15
values[4]	699	1			T2	9		T39	8		T41	14
values[5]	779	1			T34	31		T39	5		T22	1
values[6]	834	1			T34	32		T26	10		T115	49
values[7]	673	1			T3	18		T5	24		T23	1
values[8]	476	1			T2	11		T42	8		T22	9
values[9]	3520	1			T1	27		T2	13		T4	2
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	514	1			T4	1		T6	13		T23	1
values[1]	2871	1			T7	6		T9	1		T10	1
values[2]	747	1			T5	13		T26	6		T53	22
values[3]	734	1			T2	9		T39	8		T41	14
values[4]	729	1			T34	63		T39	5		T22	1
values[5]	875	1			T3	18		T23	1		T26	10
values[6]	518	1			T5	24		T208	2		T124	23
values[7]	587	1			T2	11		T42	8		T11	6
values[8]	1149	1			T1	27		T2	13		T4	2
values[9]	160	1			T142	1		T179	1		T305	1
minimum	18441	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	13		T131	14		T121	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T4	1		T23	1		T74	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	13		T127	8		T90	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1651	1			T7	1		T9	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	13		T26	6		T53	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T208	8		T209	16		T80	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	1		T39	8		T25	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	14		T11	14		T121	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T34	30		T39	5		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T129	1		T122	12		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	8		T26	6		T115	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T23	1		T124	14		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	16		T208	1		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T124	9		T74	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	1		T129	1		T130	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T42	8		T11	4		T22	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T1	14		T2	1		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T4	1		T6	11		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T305	1		T173	11		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T142	1		T179	1		T211	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18179	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T78	1		T206	3		T134	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T121	7		T33	2		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T74	4		T207	12		T264	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T127	8		T133	11		T135	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	949	1			T7	5		T92	22		T28	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T53	11		T179	8		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T209	18		T80	9		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	8		T121	10		T126	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	5		T121	9		T213	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	33		T131	8		T115	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T125	14		T179	2		T153	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	10		T26	4		T115	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T124	8		T128	9		T214	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T5	8		T208	1		T12	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	14		T48	11		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T2	10		T130	9		T215	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	2		T22	2		T123	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	13		T2	12		T26	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T131	2		T78	16		T216	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T173	8		T136	9		T138	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T211	7		T217	6		T218	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T66	1		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T78	9		T19	6		T183	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T6	16		T25	5		T180	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T127	8		T142	1		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T304	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T78	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T121	9		T127	1		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T4	1		T74	10		T206	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	13		T131	14		T90	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	13		T23	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	13		T42	13		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T25	15		T208	8		T209	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T39	8		T26	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T41	14		T11	14		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T34	14		T39	5		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T129	1		T121	8		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T34	16		T26	6		T115	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T122	12		T124	14		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	8		T5	16		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T23	1		T124	9		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T2	1		T129	1		T130	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T42	8		T22	7		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T1	14		T2	1		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1845	1			T4	1		T6	11		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T234	4		T136	9		T250	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T211	7		T217	6		T186	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T304	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T78	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T121	7		T127	1		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T74	4		T207	12		T220	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T133	11		T135	9		T143	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T31	11		T78	4		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T53	11		T127	8		T212	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T209	18		T80	9		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	8		T121	10		T126	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	5		T133	10		T227	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	17		T131	8		T124	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T121	9		T125	14		T213	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	16		T26	4		T115	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T124	8		T214	9		T222	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	10		T5	8		T115	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T124	14		T128	9		T48	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T2	10		T130	9		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T22	2		T156	12		T307	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	13		T2	12		T26	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1042	1			T7	5		T92	22		T11	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	1		T131	1		T121	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T4	1		T23	1		T74	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	1		T127	9		T90	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1288	1			T7	6		T9	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T26	1		T53	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T208	1		T209	19		T80	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	9		T39	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T41	1		T11	10		T121	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T34	35		T39	1		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T129	1		T122	1		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	11		T26	5		T115	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T23	1		T124	9		T128	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	9		T208	2		T12	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T124	15		T74	1		T48	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	11		T129	1		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T42	1		T11	5		T22	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T1	14		T2	13		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T4	1		T6	1		T131	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T305	1		T173	9		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T142	1		T179	1		T211	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18331	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T78	10		T206	3		T134	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	12		T131	13		T121	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T74	9		T207	8		T264	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T42	12		T127	7		T90	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1312	1			T38	47		T40	40		T41	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	12		T26	5		T53	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T208	7		T209	15		T80	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	7		T25	17		T121	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	13		T11	9		T121	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T34	28		T39	4		T53	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T122	11		T153	15		T228	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	7		T26	5		T115	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T124	13		T134	21		T224	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T5	15		T12	1		T189	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T124	8		T14	1		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T130	7		T225	12		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	7		T11	1		T22	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T1	13		T6	15		T41	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	10		T122	11		T127	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T173	10		T136	7		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T211	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T134	10		T185	3		T226	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T6	1		T25	1		T180	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T127	1		T142	1		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T304	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T78	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T121	8		T127	2		T33	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T4	1		T74	5		T206	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	1		T131	1		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T41	1		T23	1		T31	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T42	1		T53	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T25	1		T208	1		T209	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	9		T39	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	1		T11	10		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T34	18		T39	1		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T129	1		T121	10		T125	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	17		T26	5		T115	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	1		T124	9		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	11		T5	9		T115	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T23	1		T124	15		T128	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	11		T129	1		T130	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T42	1		T22	3		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T1	14		T2	13		T4	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1403	1			T4	1		T6	1		T7	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T6	15		T25	4		T234	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T127	7		T211	7		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T121	8		T33	1		T80	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T74	9		T207	8		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	12		T131	13		T90	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T41	12		T153	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	12		T42	12		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	14		T208	7		T209	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	7		T26	5		T121	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T41	13		T11	9		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T34	13		T39	4		T25	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T121	7		T153	15		T228	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T34	15		T26	5		T115	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T122	11		T124	13		T134	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	7		T5	15		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T124	8		T14	1		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T130	7		T225	12		T221	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T42	7		T22	6		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T1	13		T41	16		T26	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1484	1			T6	10		T38	47		T40	40

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27