Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23768

1

T1

27

T2

22

T3

129

auto[ADC_CTRL_FILTER_COND_OUT]

3557

1

T2

11

T3

18

T6

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21360

1

T2

11

T3

129

T4

2

auto[1]

5965

1

T1

27

T2

22

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	320	1			T33	4		T294	3		T153	3
values[0]	49	1			T115	27		T32	1		T18	1
values[1]	564	1			T2	9		T4	1		T34	31
values[2]	680	1			T4	1		T6	13		T42	21
values[3]	653	1			T2	11		T34	32		T130	17
values[4]	3112	1			T6	16		T7	6		T9	1
values[5]	955	1			T1	27		T5	13		T41	31
values[6]	533	1			T23	1		T26	10		T208	2
values[7]	805	1			T3	18		T11	6		T25	5
values[8]	430	1			T4	1		T129	1		T115	22
values[9]	912	1			T2	13		T5	24		T6	11
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	654	1			T6	13		T34	31		T41	13
values[1]	692	1			T4	1		T42	21		T131	12
values[2]	608	1			T2	11		T34	32		T130	17
values[3]	3076	1			T1	27		T6	16		T7	6
values[4]	851	1			T5	13		T41	17		T23	1
values[5]	677	1			T25	5		T208	2		T122	20
values[6]	722	1			T3	18		T11	6		T53	22
values[7]	475	1			T2	13		T4	1		T39	8
values[8]	877	1			T6	11		T39	5		T22	1
values[9]	161	1			T5	24		T134	15		T260	25
minimum	18532	1			T2	9		T3	129		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	13		T11	14		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T34	14		T41	13		T53	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	1		T42	13		T131	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T42	8		T124	27		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T130	8		T90	10		T75	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T34	16		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1747	1			T1	14		T7	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	16		T41	14		T121	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	13		T23	1		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T41	17		T25	15		T26	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	5		T208	1		T122	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T122	12		T30	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	4		T126	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	8		T53	11		T123	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	1		T4	1		T39	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T129	1		T78	1		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T23	1		T208	8		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	11		T39	5		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T5	16		T287	1		T289	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T134	15		T260	14		T262	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18203	1			T2	1		T3	128		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T115	13		T157	10		T137	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	5		T127	1		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	17		T115	4		T128	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	10		T125	4		T216	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	15		T213	12		T89	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T130	9		T14	1		T233	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	10		T34	16		T12	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T1	13		T7	5		T92	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T121	9		T80	9		T179	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T26	4		T126	2		T247	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T26	10		T74	4		T231	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T208	1		T153	14		T210	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T234	4		T173	5		T135	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	2		T126	5		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	10		T53	11		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	12		T115	9		T121	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T78	16		T132	9		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T123	14		T209	18		T280	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T125	14		T127	8		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T5	8		T287	8		T289	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T260	11		T262	3		T139	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	8		T3	1		T66	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T115	14		T157	11		T245	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T181	1		T166	1		T135	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T33	4		T294	1		T153	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T32	1		T18	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T115	13		T159	1		T308	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T4	1		T11	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	14		T41	13		T53	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	1		T6	13		T42	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T42	8		T124	14		T89	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T130	8		T31	1		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	1		T34	16		T124	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1774	1			T7	1		T9	1		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	16		T121	8		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T1	14		T5	13		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T41	31		T25	15		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T23	1		T26	6		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	4		T234	4		T228	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	4		T25	5		T122	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	8		T53	11		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	1		T115	13		T121	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T129	1		T78	1		T132	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	1		T5	16		T39	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	11		T39	5		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T181	10		T135	4		T222	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T294	2		T165	6		T245	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T115	14		T159	11		T308	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T2	8		T11	5		T127	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T34	17		T115	4		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T131	10		T125	4		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T124	8		T89	12		T133	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T130	9		T31	11		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	10		T34	16		T124	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T7	5		T92	22		T22	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T121	9		T12	2		T80	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	13		T126	2		T89	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	10		T74	4		T179	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T26	4		T208	1		T153	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T234	4		T173	5		T135	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	2		T48	3		T78	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	10		T53	11		T123	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T115	9		T121	7		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T78	16		T132	9		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	12		T5	8		T123	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T125	14		T127	8		T48	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	1		T11	10		T127	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T34	18		T41	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T42	1		T131	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T42	1		T124	17		T213	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T130	10		T90	1		T75	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	11		T34	17		T12	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T1	14		T7	6		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T41	1		T121	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	1		T23	1		T26	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T41	1		T25	1		T26	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T25	1		T208	2		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T122	1		T30	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	5		T126	6		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	11		T53	12		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	13		T4	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T129	1		T78	17		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T23	1		T208	1		T123	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	1		T39	1		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T5	9		T287	9		T289	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T134	1		T260	12		T262	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18354	1			T2	9		T3	129		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T115	15		T157	12		T137	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	12		T11	9		T210	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	13		T41	12		T53	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T42	12		T216	12		T309	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T42	7		T124	25		T89	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T130	7		T90	9		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	15		T12	1		T31	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T1	13		T38	47		T40	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	15		T41	13		T121	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T26	10		T90	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T41	16		T25	14		T26	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	4		T122	7		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T122	11		T234	3		T228	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	1		T133	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	7		T53	10		T123	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	7		T115	12		T121	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T132	10		T265	15		T272	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T208	7		T123	12		T209	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	10		T39	4		T25	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T5	15		T289	12		T278	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T134	14		T260	13		T262	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T221	5		T285	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T115	12		T157	9		T137	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T181	11		T166	1		T135	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T33	3		T294	3		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T32	1		T18	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T115	15		T159	12		T308	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	9		T4	1		T11	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T34	18		T41	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T6	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T42	1		T124	9		T89	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T130	10		T31	12		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	11		T34	17		T124	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T7	6		T9	1		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T121	10		T12	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	14		T5	1		T126	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T41	2		T25	1		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T23	1		T26	5		T208	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	4		T234	5		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T11	5		T25	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	11		T53	12		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	1		T115	10		T121	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T129	1		T78	17		T132	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	13		T5	9		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	1		T39	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T135	11		T186	1		T289	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T33	1		T153	2		T229	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T115	12		T308	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	9		T210	16		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T34	13		T41	12		T53	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	12		T42	12		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T42	7		T124	13		T89	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T130	7		T14	1		T216	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	15		T124	12		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T38	47		T40	40		T21	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	15		T121	7		T12	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	13		T5	12		T89	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T41	29		T25	14		T26	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T26	5		T153	15		T135	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T234	3		T228	5		T173	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T25	4		T122	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	7		T53	10		T122	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T115	12		T121	8		T122	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T132	10		T265	15		T310	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	15		T39	7		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	10		T39	4		T25	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27