Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23832

1

T1

27

T2

11

T3

147

auto[ADC_CTRL_FILTER_COND_OUT]

3493

1

T2

22

T4

2

T5

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21432

1

T1

27

T2

9

T3

147

auto[1]

5893

1

T2

24

T4

3

T5

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	57	1			T189	33		T311	1		T312	23
values[0]	31	1			T131	3		T261	13		T313	1
values[1]	691	1			T4	2		T5	24		T39	13
values[2]	684	1			T1	27		T4	1		T6	13
values[3]	726	1			T26	24		T115	32		T121	21
values[4]	697	1			T2	11		T208	8		T124	22
values[5]	3090	1			T3	18		T7	6		T9	1
values[6]	713	1			T34	31		T41	13		T22	9
values[7]	712	1			T2	9		T34	32		T26	10
values[8]	605	1			T5	13		T42	8		T22	1
values[9]	1007	1			T2	13		T6	27		T41	14
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	928	1			T1	27		T4	1		T5	24
values[1]	691	1			T4	2		T6	13		T39	5
values[2]	613	1			T2	11		T121	21		T208	8
values[3]	3195	1			T7	6		T9	1		T10	1
values[4]	724	1			T3	18		T41	17		T22	9
values[5]	645	1			T2	9		T34	31		T41	13
values[6]	721	1			T5	13		T34	32		T25	5
values[7]	610	1			T6	11		T41	14		T42	8
values[8]	651	1			T2	13		T42	13		T11	25
values[9]	216	1			T6	16		T181	8		T268	5
minimum	18331	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T1	14		T5	16		T39	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	1		T131	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	1		T6	13		T39	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	1		T115	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	1		T123	16		T125	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T121	11		T208	8		T90	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1749	1			T7	1		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T115	13		T122	12		T78	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	8		T41	17		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T22	7		T26	6		T131	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T26	6		T75	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	1		T34	14		T41	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T25	5		T53	11		T124	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	13		T34	16		T122	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T41	14		T42	8		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	11		T25	15		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	4		T115	13		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	1		T42	13		T11	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T181	1		T268	5		T249	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T6	16		T314	1		T315	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18183	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T221	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	13		T5	8		T89	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	2		T208	1		T127	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	10		T124	14		T223	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T115	4		T31	1		T231	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	10		T123	11		T125	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T121	10		T78	4		T303	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T7	5		T92	22		T28	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T115	14		T78	25		T80	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	10		T35	3		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T22	2		T227	8		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	4		T189	1		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	8		T34	17		T121	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T53	11		T124	7		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	16		T126	7		T209	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T213	12		T74	4		T165	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T123	14		T12	2		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	2		T115	9		T127	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	12		T11	5		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T181	7		T249	7		T187	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T314	3		T315	2		T183	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T66	1		T121	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T221	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T189	17		T311	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T312	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T313	1		T316	5		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T131	1		T261	1		T318	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	16		T39	13		T53	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	2		T129	1		T89	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	14		T4	1		T6	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T208	1		T127	8		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	14		T123	16		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T115	14		T121	11		T90	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T124	14		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T208	8		T78	2		T80	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1742	1			T3	8		T7	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T122	12		T130	1		T228	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T75	2		T240	1		T216	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T34	14		T41	13		T22	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T26	6		T53	11		T124	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T34	16		T121	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	8		T22	1		T25	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	13		T122	12		T209	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T41	14		T11	4		T115	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T2	1		T6	27		T42	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T189	16		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T312	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T316	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T131	2		T261	12		T318	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	8		T121	7		T89	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T89	12		T14	1		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	13		T124	14		T125	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T208	1		T127	8		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T26	10		T123	11		T125	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T115	18		T121	10		T78	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	10		T124	8		T48	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T78	25		T80	9		T303	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T3	10		T7	5		T92	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	2		T16	2		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T240	4		T216	17		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T34	17		T22	2		T294	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	4		T53	11		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	8		T34	16		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T74	4		T234	4		T165	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T209	18		T31	11		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	2		T115	9		T213	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	12		T11	5		T131	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	14		T5	9		T39	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T4	1		T131	3		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T6	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	1		T115	5		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	11		T123	12		T125	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T121	11		T208	1		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T7	6		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T115	15		T122	1		T78	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	11		T41	1		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	3		T26	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T26	5		T75	1		T189	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	9		T34	18		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T25	1		T53	12		T124	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T34	17		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T41	1		T42	1		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	1		T25	1		T123	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	5		T115	10		T127	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	13		T42	1		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T181	8		T268	1		T249	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T6	1		T314	4		T315	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18321	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	13		T5	15		T39	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T127	7		T89	9		T90	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	12		T39	4		T26	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T173	10		T235	13		T307	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T123	15		T33	1		T132	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T121	10		T208	7		T90	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T38	47		T40	40		T21	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T115	12		T122	11		T80	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	7		T41	16		T25	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T22	6		T26	5		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T26	5		T132	10		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	13		T41	12		T121	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T25	4		T53	10		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	12		T34	15		T122	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T41	13		T42	7		T74	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	10		T25	14		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	1		T115	12		T189	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	12		T11	9		T130	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T268	4		T161	13		T257	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T6	15		T315	13		T253	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T121	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T189	17		T311	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T312	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T313	1		T316	5		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T131	3		T261	13		T318	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	9		T39	2		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	2		T129	1		T89	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	14		T4	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T208	2		T127	9		T31	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	11		T123	12		T125	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T115	20		T121	11		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	11		T124	9		T48	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T208	1		T78	27		T80	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T3	11		T7	6		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T122	1		T130	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T75	2		T240	5		T216	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	18		T41	1		T22	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T26	5		T53	12		T124	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	9		T34	17		T121	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T42	1		T22	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T122	1		T209	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T41	1		T11	5		T115	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T2	13		T6	2		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T189	16		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T312	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T316	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	15		T39	11		T53	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T89	9		T90	9		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	13		T6	12		T124	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T127	7		T235	13		T254	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	13		T123	15		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T115	12		T121	10		T90	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T124	13		T173	5		T264	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T208	7		T80	10		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T3	7		T38	47		T40	40
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T122	11		T228	5		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T216	12		T132	10		T258	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	13		T41	12		T22	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T26	5		T53	10		T124	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T34	15		T121	7		T122	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T42	7		T25	4		T74	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	12		T122	11		T209	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	13		T11	1		T115	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T6	25		T42	12		T11	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27