Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23961

1

T1

27

T2

11

T3

147

auto[ADC_CTRL_FILTER_COND_OUT]

3364

1

T2

22

T4

2

T6

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21384

1

T1

27

T2

9

T3

147

auto[1]

5941

1

T2

24

T4

2

T5

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	193	1			T2	13		T6	16		T115	22
values[0]	27	1			T131	3		T164	14		T316	9
values[1]	726	1			T4	1		T5	24		T39	8
values[2]	619	1			T1	27		T4	2		T6	13
values[3]	730	1			T26	24		T115	27		T121	21
values[4]	717	1			T2	11		T208	8		T124	22
values[5]	3104	1			T3	18		T7	6		T9	1
values[6]	730	1			T2	9		T34	31		T41	13
values[7]	707	1			T34	32		T25	5		T26	10
values[8]	609	1			T5	13		T42	8		T22	1
values[9]	851	1			T6	11		T41	14		T42	13
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	619	1			T1	27		T5	24		T39	13
values[1]	737	1			T4	2		T6	13		T23	1
values[2]	605	1			T2	11		T115	27		T121	21
values[3]	3178	1			T7	6		T9	1		T10	1
values[4]	733	1			T3	18		T41	17		T22	9
values[5]	628	1			T2	9		T34	31		T41	13
values[6]	756	1			T5	13		T34	32		T25	5
values[7]	594	1			T6	11		T41	14		T42	8
values[8]	662	1			T2	13		T42	13		T11	25
values[9]	206	1			T6	16		T231	3		T189	33
minimum	18607	1			T3	129		T4	1		T8	146

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	14		T5	16		T39	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T129	1		T208	1		T89	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	1		T6	13		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T115	1		T127	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	1		T125	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T115	13		T121	11		T208	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1779	1			T7	1		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T122	12		T90	6		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	8		T41	17		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	7		T26	6		T131	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T26	6		T75	1		T216	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T34	14		T41	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	13		T25	5		T122	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T34	16		T53	11		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T41	14		T42	8		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	11		T25	15		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	4		T115	13		T130	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T42	13		T11	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T189	17		T249	1		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T6	16		T231	1		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18279	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T4	1		T131	1		T142	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	13		T5	8		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T208	1		T89	12		T210	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	10		T124	14		T123	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T115	4		T127	8		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	10		T125	4		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T115	14		T121	10		T78	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T7	5		T92	22		T28	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T78	9		T153	14		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	10		T31	3		T48	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T22	2		T35	3		T227	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T26	4		T216	17		T189	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T2	8		T34	17		T121	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T124	7		T126	2		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	16		T53	11		T126	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T213	12		T74	4		T234	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T123	14		T12	2		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	2		T115	9		T130	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	12		T11	5		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T189	16		T249	7		T187	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T231	2		T314	3		T315	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T66	1		T121	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T131	2		T179	8		T233	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T115	13		T293	1		T311	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T2	1		T6	16		T127	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T164	14		T316	5		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T131	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	16		T39	8		T53	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T129	1		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	14		T4	1		T6	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	1		T115	1		T127	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	14		T123	16		T125	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T115	13		T121	11		T90	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T124	14		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T208	8		T78	1		T153	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1758	1			T3	8		T7	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T122	12		T35	5		T283	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T75	2		T216	13		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T34	14		T41	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T25	5		T26	6		T122	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T34	16		T53	11		T121	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	13		T42	8		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T209	16		T31	1		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	14		T11	4		T130	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	11		T42	13		T11	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T115	9		T293	8		T319	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T2	12		T231	2		T186	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T316	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T131	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	8		T121	7		T89	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T208	1		T89	12		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	13		T124	14		T247	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T115	4		T127	8		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	10		T123	11		T125	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T115	14		T121	10		T78	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	10		T124	8		T48	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T78	9		T153	14		T303	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T3	10		T7	5		T92	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	3		T36	2		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T216	17		T189	1		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	8		T34	17		T22	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	4		T124	7		T126	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T34	16		T53	11		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T74	4		T234	4		T165	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T209	18		T31	11		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	2		T130	9		T213	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	5		T131	8		T123	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	14		T5	9		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T129	1		T208	2		T89	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T6	1		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	1		T115	5		T127	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	11		T125	5		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T115	15		T121	11		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T7	6		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T122	1		T90	1		T78	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	11		T41	1		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T22	3		T26	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T26	5		T75	1		T216	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	9		T34	18		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T25	1		T122	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	17		T53	12		T126	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T41	1		T42	1		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	1		T25	1		T123	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	5		T115	10		T130	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	13		T42	1		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T189	17		T249	8		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T6	1		T231	3		T314	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18400	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T4	1		T131	3		T142	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	13		T5	15		T39	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T89	9		T90	9		T210	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	12		T26	13		T124	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T127	7		T173	10		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T33	1		T132	10		T254	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T115	12		T121	10		T208	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T38	47		T40	40		T21	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T122	11		T90	5		T153	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	7		T41	16		T25	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	6		T26	5		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T26	5		T216	12		T132	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	13		T41	12		T121	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	12		T25	4		T122	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T34	15		T53	10		T209	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T41	13		T42	7		T74	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	10		T25	14		T123	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	1		T115	12		T130	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T42	12		T11	9		T127	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T189	16		T161	13		T320	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T6	15		T315	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T53	7		T121	8		T89	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T233	3		T224	10		T321	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T115	10		T293	9		T311	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T2	13		T6	1		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T164	1		T316	5		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T131	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	9		T39	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	1		T129	1		T208	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	14		T4	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	1		T115	5		T127	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T26	11		T123	12		T125	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T115	15		T121	11		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	11		T124	9		T48	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T208	1		T78	10		T153	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T3	11		T7	6		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T122	1		T35	7		T283	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T75	2		T216	18		T189	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	9		T34	18		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	1		T26	5		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	17		T53	12		T121	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T5	1		T42	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T209	19		T31	12		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T41	1		T11	5		T130	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	1		T42	1		T11	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T115	12		T319	9		T322	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T6	15		T127	7		T186	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T164	13		T316	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	15		T39	7		T53	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T89	9		T90	9		T210	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	13		T6	12		T39	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T127	7		T235	13		T135	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	13		T123	15		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T115	12		T121	10		T90	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T124	13		T80	10		T264	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T208	7		T153	15		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T3	7		T38	47		T40	40
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T122	11		T35	1		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T216	12		T132	10		T251	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	13		T41	12		T22	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	4		T26	5		T122	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	15		T53	10		T121	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	12		T42	7		T122	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T209	15		T214	3		T135	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	13		T11	1		T130	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	10		T42	12		T11	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27