Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23843

1

T2

33

T3

147

T5

24

auto[ADC_CTRL_FILTER_COND_OUT]

3482

1

T1

27

T4

3

T5

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21310

1

T2

22

T3

147

T4

2

auto[1]

6015

1

T1

27

T2

11

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T25	5		T208	2		T153	3
values[0]	65	1			T166	1		T146	28		T329	1
values[1]	884	1			T2	13		T4	1		T5	24
values[2]	654	1			T6	13		T34	31		T122	12
values[3]	683	1			T1	27		T4	1		T6	16
values[4]	796	1			T41	14		T26	24		T123	27
values[5]	516	1			T2	9		T39	8		T42	13
values[6]	818	1			T41	13		T25	18		T53	30
values[7]	733	1			T2	11		T3	18		T6	11
values[8]	2861	1			T7	6		T9	1		T10	1
values[9]	760	1			T4	1		T5	13		T39	5
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	872	1			T2	13		T5	24		T23	1
values[1]	573	1			T6	13		T34	31		T122	12
values[2]	725	1			T1	27		T4	1		T6	16
values[3]	811	1			T2	9		T41	14		T42	13
values[4]	598	1			T39	8		T25	18		T53	22
values[5]	691	1			T41	13		T26	10		T53	8
values[6]	3139	1			T2	11		T3	18		T6	11
values[7]	516	1			T5	13		T23	1		T131	14
values[8]	707	1			T4	1		T41	17		T42	8
values[9]	135	1			T39	5		T74	1		T173	19
minimum	18558	1			T3	129		T4	1		T8	146

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	1		T5	16		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T23	1		T124	22		T127	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	13		T122	12		T130	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T34	14		T33	3		T89	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T123	13		T30	1		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	14		T4	1		T6	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T80	15		T132	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T41	14		T42	13		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T39	8		T25	18		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T209	16		T35	5		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	6		T89	10		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T41	13		T53	8		T121	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1661	1			T2	1		T3	8		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T6	11		T22	1		T25	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T23	1		T131	14		T121	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	13		T115	13		T121	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T25	5		T131	1		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T41	17		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T39	5		T74	1		T173	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T299	1		T183	1		T330	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18239	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T4	1		T129	1		T244	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	12		T5	8		T131	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T124	21		T127	8		T74	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	9		T189	1		T233	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T34	17		T33	2		T89	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T123	14		T12	2		T31	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T1	13		T11	5		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	8		T80	3		T132	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T78	9		T234	4		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T53	11		T31	3		T80	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T209	18		T35	3		T78	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T26	4		T89	12		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T121	9		T123	11		T280	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T2	10		T3	10		T7	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T115	14		T126	2		T128	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T121	10		T133	10		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T115	9		T121	7		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	8		T115	4		T208	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	2		T215	10		T240	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T173	8		T149	14		T161	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T183	12		T330	2		T331	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	1		T34	16		T22	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T235	11		T143	8		T293	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T25	5		T208	1		T153	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T283	1		T254	5		T264	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T242	5		T163	14		T332	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T166	1		T146	14		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	1		T5	16		T34	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T4	1		T23	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	13		T122	12		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	14		T124	9		T127	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T130	8		T30	1		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	14		T4	1		T6	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T123	13		T33	4		T80	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	14		T26	14		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T39	8		T208	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	13		T209	16		T35	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T25	18		T53	11		T89	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T41	13		T53	8		T121	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T3	8		T26	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	11		T22	1		T25	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T7	1		T9	1		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T121	9		T130	1		T75	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T39	5		T131	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	1		T5	13		T41	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T208	1		T227	8		T237	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T264	12		T182	4		T289	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T163	13		T332	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T146	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	12		T5	8		T34	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T124	7		T74	4		T235	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T179	8		T233	9		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T34	17		T124	14		T127	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	9		T12	2		T31	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	13		T11	5		T126	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T123	14		T80	3		T294	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	10		T78	9		T235	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T2	8		T31	3		T207	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T209	18		T35	3		T231	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T53	11		T89	12		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T121	9		T123	11		T78	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T2	10		T3	10		T26	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T115	14		T126	2		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T7	5		T92	22		T28	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T121	7		T48	3		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T131	8		T115	4		T121	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	2		T115	9		T215	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	13		T5	9		T131	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T23	1		T124	23		T127	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T122	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T34	18		T33	4		T89	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T123	15		T30	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	14		T4	1		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	9		T80	4		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T41	1		T42	1		T78	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	1		T25	1		T53	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T209	19		T35	7		T78	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	5		T89	13		T31	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T41	1		T53	1		T121	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T2	11		T3	11		T7	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T6	1		T22	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T23	1		T131	1		T121	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T115	10		T121	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T25	1		T131	9		T115	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T41	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T39	1		T74	1		T173	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T299	1		T183	13		T330	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18362	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T4	1		T129	1		T244	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	15		T133	5		T37	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T124	20		T127	7		T90	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	12		T122	11		T130	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T34	13		T33	1		T89	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T123	12		T33	1		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	13		T6	15		T11	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T80	14		T132	10		T210	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	13		T42	12		T234	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T39	7		T25	17		T53	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T209	15		T35	1		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T26	5		T89	9		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T41	12		T53	7		T121	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T3	7		T38	47		T40	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	10		T25	14		T115	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T131	13		T121	10		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T5	12		T115	12		T121	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	4		T122	7		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	16		T42	7		T11	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T39	4		T173	10		T333	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T330	1		T188	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T34	15		T22	6		T124	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T235	12		T143	5		T275	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T25	1		T208	2		T153	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T283	1		T254	1		T264	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T242	1		T163	14		T332	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T166	1		T146	15		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	13		T5	9		T34	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	1		T23	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	1		T122	1		T179	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	18		T124	15		T127	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T130	10		T30	1		T12	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	14		T4	1		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T123	15		T33	3		T80	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T41	1		T26	11		T78	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	9		T39	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T42	1		T209	19		T35	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T25	1		T53	12		T89	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T41	1		T53	1		T121	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	11		T3	11		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	1		T22	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T7	6		T9	1		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T121	8		T130	1		T75	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	1		T131	9		T115	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	1		T5	1		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T25	4		T153	2		T227	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T254	4		T264	12		T334	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T242	4		T163	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T146	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	15		T34	15		T22	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T124	12		T90	9		T74	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	12		T122	11		T233	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	13		T124	8		T127	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T130	7		T12	1		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	13		T6	15		T11	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T123	12		T33	1		T80	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	13		T26	13		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T39	7		T208	7		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T42	12		T209	15		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	17		T53	10		T89	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T41	12		T53	7		T121	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	7		T26	10		T216	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	10		T25	14		T115	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T38	47		T40	40		T21	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T121	8		T132	10		T207	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T39	4		T121	10		T122	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	12		T41	16		T42	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27