Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T2	13		T5	9		T34	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T4	1		T23	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	1		T122	1		T130	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	18		T33	4		T89	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T123	15		T30	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	14		T4	1		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	9		T132	10		T210	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T41	1		T42	1		T78	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	1		T25	1		T53	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T209	19		T35	7		T78	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T31	2		T75	1		T231	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T41	1		T26	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T2	11		T3	11		T7	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T22	1		T25	1		T115	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T23	1		T131	1		T121	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T121	8		T130	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T131	9		T115	5		T208	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	1		T5	1		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T39	1		T25	1		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T42	1		T15	1		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T232	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	15		T34	15		T22	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T124	20		T127	7		T90	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	12		T122	11		T130	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T34	13		T33	1		T89	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T123	12		T33	1		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	13		T6	15		T11	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T132	10		T210	16		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T41	13		T42	12		T234	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	7		T25	17		T53	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T209	15		T35	1		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T153	15		T157	3		T241	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	10		T41	12		T26	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T3	7		T38	47		T40	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T25	14		T115	12		T216	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T131	13		T121	10		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T121	8		T90	6		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T122	7		T153	2		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	12		T41	16		T11	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T39	4		T25	4		T173	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T42	7		T146	9		T237	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	1		T153	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T124	9		T230	11		T159	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T146	15		T238	1		T239	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	9		T34	17		T22	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T23	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	13		T6	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T34	18		T124	15		T127	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T130	10		T30	1		T31	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	14		T4	1		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T123	15		T33	3		T12	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	1		T26	11		T78	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	9		T39	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	1		T53	1		T209	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T25	1		T53	12		T89	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T41	1		T121	10		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	11		T3	11		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T6	1		T22	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T7	6		T9	1		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	1		T5	1		T115	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T25	1		T115	5		T121	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T41	1		T42	1		T11	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T39	4		T153	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T124	13		T230	10		T242	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T146	13		T239	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	15		T34	15		T22	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T124	12		T90	9		T74	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	12		T122	11		T233	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T34	13		T124	8		T127	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T130	7		T14	1		T165	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	13		T6	15		T11	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T123	12		T33	1		T12	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T41	13		T26	13		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	7		T208	7		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T42	12		T53	7		T209	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	17		T53	10		T89	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T41	12		T121	7		T123	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	7		T26	5		T153	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	10		T25	14		T26	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T38	47		T40	40		T21	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	12		T115	12		T121	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T25	4		T121	10		T122	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	16		T42	7		T11	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27