Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23802

1

T3

129

T4

2

T5

37

auto[ADC_CTRL_FILTER_COND_OUT]

3523

1

T1

27

T2

33

T3

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21257

1

T2

22

T3

129

T4

2

auto[1]

6068

1

T1

27

T2

11

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T243	1		-	-		-	-
values[0]	80	1			T41	14		T23	1		T189	35
values[1]	710	1			T2	9		T4	1		T6	13
values[2]	3080	1			T5	13		T7	6		T9	1
values[3]	721	1			T2	11		T4	1		T6	11
values[4]	702	1			T4	1		T25	15		T131	3
values[5]	782	1			T2	13		T34	31		T39	8
values[6]	650	1			T208	8		T124	20		T213	13
values[7]	453	1			T3	18		T22	1		T129	1
values[8]	607	1			T5	24		T6	16		T11	19
values[9]	1227	1			T1	27		T34	32		T39	5
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	904	1			T2	9		T4	1		T5	13
values[1]	3208	1			T7	6		T9	1		T10	1
values[2]	659	1			T2	11		T4	1		T6	11
values[3]	701	1			T4	1		T39	8		T131	3
values[4]	612	1			T2	13		T34	31		T41	13
values[5]	743	1			T3	18		T129	1		T208	8
values[6]	563	1			T6	16		T22	1		T115	5
values[7]	458	1			T5	24		T11	19		T115	27
values[8]	979	1			T1	27		T34	32		T39	5
values[9]	163	1			T41	17		T129	1		T126	6
minimum	18335	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	13		T23	1		T89	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	1		T4	1		T6	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1730	1			T7	1		T9	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T126	1		T127	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T4	1		T6	11		T22	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	1		T26	6		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	1		T128	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T39	8		T131	1		T121	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	14		T41	13		T75	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T130	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T208	8		T124	13		T209	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	8		T129	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T22	1		T30	1		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	16		T115	1		T122	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	16		T11	14		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T115	13		T90	17		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T39	5		T42	8		T121	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T1	14		T34	16		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T126	1		T245	11		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T41	17		T129	1		T247	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18174	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T32	1		T248	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T89	12		T210	9		T133	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	8		T26	10		T53	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T7	5		T92	22		T11	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T126	2		T127	1		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T22	2		T78	4		T247	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T2	10		T26	4		T124	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T128	9		T153	2		T132	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T131	2		T121	10		T127	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T34	17		T80	3		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	12		T125	4		T31	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T124	7		T209	18		T210	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	10		T213	12		T78	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T214	16		T249	18		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T115	4		T124	14		T80	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T5	8		T11	5		T208	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T115	14		T235	11		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T121	7		T130	9		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	13		T34	16		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T126	5		T245	11		T252	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T247	13		T253	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T66	1		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T248	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T243	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T23	1		T189	1		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T41	14		T189	17		T254	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T89	10		T228	6		T133	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	1		T4	1		T6	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T5	13		T7	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T122	8		T126	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	1		T6	11		T22	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	1		T26	6		T124	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T4	1		T25	15		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	1		T121	11		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	14		T41	13		T75	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	1		T39	8		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T208	8		T124	13		T209	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T213	1		T33	4		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T22	1		T30	1		T214	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	8		T129	1		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	16		T11	14		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	16		T131	1		T115	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T39	5		T42	8		T121	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T1	14		T34	16		T41	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T189	1		T236	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T189	16		T255	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T89	12		T133	11		T173	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	8		T26	10		T53	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T7	5		T92	22		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T126	2		T127	1		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T22	2		T123	11		T48	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	10		T26	4		T124	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T128	9		T78	4		T247	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T131	2		T121	10		T127	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	17		T80	3		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	12		T125	4		T31	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T124	7		T209	18		T210	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T213	12		T48	11		T216	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T214	16		T250	11		T222	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	10		T124	14		T78	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	8		T11	5		T208	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T131	8		T115	18		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T121	7		T130	9		T126	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T1	13		T34	16		T115	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T23	1		T89	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	9		T4	1		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T7	6		T9	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T126	3		T127	2		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	1		T6	1		T22	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	11		T26	5		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	1		T128	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T39	1		T131	3		T121	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	18		T41	1		T75	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	13		T130	1		T125	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T208	1		T124	8		T209	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	11		T129	1		T213	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T22	1		T30	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T115	5		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	9		T11	10		T208	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T115	15		T90	2		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	1		T42	1		T121	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	14		T34	17		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T126	6		T245	12		T246	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T41	1		T129	1		T247	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18314	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T32	1		T248	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	12		T89	9		T210	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	12		T41	13		T42	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T38	47		T40	40		T11	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	1		T89	11		T37	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	10		T22	6		T25	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T26	5		T122	11		T124	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T153	12		T132	10		T228	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	7		T121	10		T127	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	13		T41	12		T80	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T216	12		T214	10		T143	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T208	7		T124	12		T209	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	7		T33	1		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T153	2		T214	10		T222	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	15		T122	11		T124	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T5	15		T11	9		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T115	12		T90	15		T235	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	4		T42	7		T121	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	13		T34	15		T25	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T245	10		T252	8		T256	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T41	16		T253	1		T257	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T248	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T243	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T23	1		T189	2		T236	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T41	1		T189	17		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T89	13		T228	1		T133	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	9		T4	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T5	1		T7	6		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	1		T126	3		T127	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	1		T6	1		T22	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	11		T26	5		T124	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	1		T25	1		T128	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T131	3		T121	11		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T34	18		T41	1		T75	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	13		T39	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T208	1		T124	8		T209	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T213	13		T33	3		T48	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T22	1		T30	1		T214	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	11		T129	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	9		T11	10		T208	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T131	9		T115	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T39	1		T42	1		T121	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T1	14		T34	17		T41	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T41	13		T189	16		T254	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T89	9		T228	5		T133	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	12		T42	12		T26	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T5	12		T38	47		T40	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T122	7		T33	1		T89	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	10		T22	6		T25	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T26	5		T124	13		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	14		T153	12		T228	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T121	10		T122	11		T127	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	13		T41	12		T80	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T39	7		T173	5		T214	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T208	7		T124	12		T209	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	1		T216	12		T258	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T214	10		T222	12		T241	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	7		T122	11		T124	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	15		T11	9		T153	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	15		T115	12		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T39	4		T42	7		T121	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T1	13		T34	15		T41	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27