Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23823

1

T1

27

T2

20

T3

147

auto[ADC_CTRL_FILTER_COND_OUT]

3502

1

T2

13

T4

3

T5

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21415

1

T1

27

T2

20

T3

147

auto[1]

5910

1

T2

13

T4

2

T5

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T250	12		-	-		-	-
values[0]	55	1			T11	6		T184	12		T259	5
values[1]	558	1			T39	8		T53	8		T115	27
values[2]	822	1			T41	30		T22	1		T25	33
values[3]	714	1			T42	8		T121	21		T122	12
values[4]	712	1			T2	13		T3	18		T5	13
values[5]	488	1			T34	31		T131	14		T31	19
values[6]	560	1			T1	27		T41	14		T25	5
values[7]	783	1			T6	27		T22	9		T121	16
values[8]	709	1			T2	9		T4	2		T39	5
values[9]	3600	1			T2	11		T4	1		T5	24
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	875	1			T39	8		T41	30		T11	6
values[1]	648	1			T22	1		T131	9		T124	20
values[2]	727	1			T5	13		T42	8		T125	15
values[3]	565	1			T2	13		T3	18		T34	32
values[4]	642	1			T1	27		T34	31		T131	14
values[5]	616	1			T6	11		T22	9		T25	5
values[6]	3127	1			T6	16		T7	6		T9	1
values[7]	708	1			T2	20		T4	2		T39	5
values[8]	895	1			T5	24		T11	19		T23	2
values[9]	186	1			T4	1		T6	13		T131	3
minimum	18336	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T39	8		T11	4		T25	33
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T41	30		T115	13		T123	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T131	1		T31	1		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T22	1		T124	13		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T42	8		T125	1		T89	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	13		T35	5		T90	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	8		T34	16		T42	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T122	12		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	14		T131	14		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	14		T53	11		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	11		T22	7		T25	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T129	1		T130	8		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T7	1		T9	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T6	16		T41	14		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	2		T121	9		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	2		T39	5		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	14		T121	8		T208	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T5	16		T23	2		T26	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T78	1		T260	10		T261	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T4	1		T6	13		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18174	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T33	4		T262	1		T263	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T115	14		T123	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T115	9		T123	11		T126	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T131	8		T31	1		T234	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T124	7		T213	12		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T125	14		T89	12		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	3		T216	17		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	10		T34	16		T121	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	12		T181	7		T173	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	13		T210	1		T264	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	17		T53	11		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T22	2		T26	4		T48	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T130	9		T31	11		T240	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T7	5		T92	22		T28	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T124	8		T125	4		T12	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	18		T121	7		T208	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T115	4		T127	1		T78	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	5		T121	9		T189	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	8		T26	10		T78	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T78	9		T260	11		T261	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T131	2		T127	8		T265	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T262	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T250	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T11	4		T184	2		T266	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T259	4		T163	11		T267	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	8		T53	8		T115	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T123	16		T33	4		T13	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	33		T131	1		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T41	30		T22	1		T115	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T42	8		T121	11		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T122	12		T30	1		T35	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	8		T34	16		T42	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	1		T5	13		T53	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T131	14		T48	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T34	14		T31	5		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	14		T25	5		T26	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T41	14		T129	1		T130	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	11		T22	7		T121	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	16		T125	1		T74	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	1		T208	1		T127	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	2		T39	5		T26	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1864	1			T2	1		T7	1		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T4	1		T5	16		T6	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T250	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T11	2		T184	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T259	1		T163	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T115	14		T123	14		T126	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T123	11		T179	2		T249	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T131	8		T135	4		T143	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T115	9		T124	7		T213	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T121	10		T125	14		T89	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	3		T133	10		T227	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	10		T34	16		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T2	12		T53	11		T207	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T48	11		T210	1		T264	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T34	17		T31	14		T181	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	13		T26	4		T189	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T130	9		T240	4		T153	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T22	2		T121	7		T80	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T125	4		T74	4		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	8		T208	1		T33	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	10		T115	4		T124	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T2	10		T7	5		T92	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	8		T131	2		T127	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T39	1		T11	5		T25	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T41	2		T115	10		T123	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T131	9		T31	2		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T22	1		T124	8		T213	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T42	1		T125	15		T89	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	1		T35	7		T90	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	11		T34	17		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	13		T122	1		T181	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	14		T131	1		T210	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	18		T53	12		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T22	3		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T129	1		T130	10		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T7	6		T9	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	1		T41	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T2	20		T121	8		T208	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	2		T39	1		T115	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	10		T121	10		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	9		T23	2		T26	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T78	10		T260	12		T261	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T4	1		T6	1		T131	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18313	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T33	3		T262	7		T263	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	7		T11	1		T25	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T41	28		T115	12		T123	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T234	3		T133	9		T268	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T124	12		T89	11		T165	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T42	7		T89	9		T269	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	12		T35	1		T90	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	7		T34	15		T42	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T122	11		T228	5		T173	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	13		T131	13		T264	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T34	13		T53	10		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T6	10		T22	6		T25	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T130	7		T153	12		T228	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T38	47		T40	40		T21	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	15		T41	13		T26	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T121	8		T124	8		T127	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T39	4		T270	11		T258	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	9		T121	7		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	15		T26	13		T153	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T260	9		T271	6		T272	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T6	12		T122	7		T127	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T33	1		T263	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T250	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T11	5		T184	11		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T259	4		T163	7		T267	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	1		T53	1		T115	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T123	12		T33	3		T13	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T25	2		T131	9		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T41	2		T22	1		T115	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T42	1		T121	11		T125	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T122	1		T30	1		T35	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	11		T34	17		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	13		T5	1		T53	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T131	1		T48	12		T210	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T34	18		T31	16		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	14		T25	1		T26	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	1		T129	1		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	1		T22	3		T121	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T125	5		T74	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	9		T208	2		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	2		T39	1		T26	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T2	11		T7	6		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T4	1		T5	9		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T11	1		T184	1		T266	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T259	1		T163	10		T267	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	7		T53	7		T115	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T123	15		T33	1		T270	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	31		T268	4		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T41	28		T115	12		T124	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T42	7		T121	10		T89	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T122	11		T35	1		T90	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	7		T34	15		T42	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	12		T53	10		T90	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T131	13		T264	13		T273	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T34	13		T31	3		T153	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	13		T25	4		T26	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T41	13		T130	7		T153	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	10		T22	6		T121	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	15		T74	9		T36	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T127	7		T33	1		T133	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T39	4		T26	18		T124	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T38	47		T40	40		T11	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T5	15		T6	12		T122	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27