Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23789

1

T1

27

T2

22

T3

129

auto[ADC_CTRL_FILTER_COND_OUT]

3536

1

T2

11

T3

18

T6

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21372

1

T2

11

T3

129

T4

2

auto[1]

5953

1

T1

27

T2

22

T3

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T186	3		-	-		-	-
values[0]	100	1			T4	1		T115	32		T80	18
values[1]	578	1			T2	9		T34	31		T41	13
values[2]	592	1			T4	1		T6	13		T42	21
values[3]	628	1			T2	11		T34	32		T130	18
values[4]	3137	1			T6	16		T7	6		T9	1
values[5]	992	1			T1	27		T5	13		T41	31
values[6]	533	1			T23	1		T26	10		T208	2
values[7]	734	1			T3	18		T11	6		T25	5
values[8]	453	1			T4	1		T53	22		T122	12
values[9]	1263	1			T2	13		T5	24		T6	11
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	858	1			T2	9		T4	1		T6	13
values[1]	642	1			T4	1		T42	21		T131	12
values[2]	662	1			T2	11		T6	16		T34	32
values[3]	3056	1			T7	6		T9	1		T10	1
values[4]	836	1			T1	27		T5	13		T41	17
values[5]	727	1			T25	5		T208	2		T122	20
values[6]	648	1			T3	18		T11	6		T53	22
values[7]	539	1			T2	13		T4	1		T39	8
values[8]	841	1			T6	11		T39	5		T22	1
values[9]	176	1			T5	24		T134	15		T286	8
minimum	18340	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T4	1		T6	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T34	14		T41	13		T53	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	1		T42	13		T131	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T42	8		T124	27		T89	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T130	8		T90	10		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	1		T6	16		T34	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1744	1			T7	1		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	14		T121	8		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	14		T5	13		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T41	17		T25	15		T26	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	5		T208	1		T122	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T122	12		T30	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	4		T126	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	8		T53	11		T123	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T4	1		T39	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T129	1		T127	8		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T23	1		T208	8		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	11		T39	5		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T5	16		T134	15		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T286	8		T260	14		T262	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T115	13		T288	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	8		T11	5		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T34	17		T115	4		T128	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T131	10		T125	4		T216	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	15		T89	12		T189	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T130	9		T31	11		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	10		T34	16		T213	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T7	5		T92	22		T22	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T121	9		T80	9		T231	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	13		T26	4		T126	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	10		T74	4		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T208	1		T153	14		T210	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T234	4		T173	5		T135	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	2		T126	5		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	10		T53	11		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	12		T115	9		T121	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T127	8		T78	16		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T123	14		T209	18		T280	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T125	14		T48	11		T215	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T5	8		T287	8		T289	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T260	11		T262	3		T139	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T115	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T186	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T4	1		T32	1		T18	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T115	14		T80	15		T268	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	1		T11	14		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T34	14		T41	13		T53	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T6	13		T42	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	8		T124	14		T133	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T130	9		T74	1		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T34	16		T124	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1771	1			T7	1		T9	1		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	16		T121	8		T12	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T1	14		T5	13		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T41	31		T25	15		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T23	1		T26	6		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T122	12		T234	4		T173	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	4		T25	5		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	8		T123	16		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T4	1		T122	12		T124	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	11		T127	8		T78	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T2	1		T5	16		T39	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T6	11		T39	5		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T186	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T253	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T115	18		T80	3		T251	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	8		T11	5		T131	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	17		T128	9		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T131	8		T125	4		T179	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	8		T133	11		T207	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T130	9		T14	1		T216	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	10		T34	16		T124	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T7	5		T92	22		T22	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T121	9		T12	2		T231	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	13		T126	2		T89	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	10		T74	4		T179	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T26	4		T208	1		T153	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T234	4		T173	5		T135	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	2		T48	3		T78	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	10		T123	11		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T124	14		T126	5		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T53	11		T127	8		T78	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T2	12		T5	8		T115	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T125	14		T48	11		T215	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	9		T4	1		T6	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T34	18		T41	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T42	1		T131	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T42	1		T124	17		T89	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T130	10		T90	1		T31	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	11		T6	1		T34	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T7	6		T9	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T41	1		T121	10		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	14		T5	1		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T41	1		T25	1		T26	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T25	1		T208	2		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T122	1		T30	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	5		T126	6		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	11		T53	12		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	13		T4	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T129	1		T127	9		T78	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T23	1		T208	1		T123	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	1		T39	1		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T5	9		T134	1		T287	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T286	1		T260	12		T262	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T115	15		T288	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	12		T11	9		T210	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T34	13		T41	12		T53	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T42	12		T216	12		T290	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T42	7		T124	25		T89	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T130	7		T90	9		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	15		T34	15		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T38	47		T40	40		T21	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	13		T121	7		T80	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	13		T5	12		T26	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T41	16		T25	14		T26	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T25	4		T122	7		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T122	11		T234	3		T228	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	1		T133	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	7		T53	10		T123	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	7		T115	12		T121	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T127	7		T132	10		T265	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T208	7		T123	12		T209	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	10		T39	4		T25	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T5	15		T134	14		T289	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T286	7		T260	13		T262	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T115	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T186	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T4	1		T32	1		T18	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T115	20		T80	4		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	9		T11	10		T131	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	18		T41	1		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	1		T6	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T42	1		T124	9		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T130	11		T74	1		T75	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	11		T34	17		T124	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T7	6		T9	1		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T121	10		T12	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	14		T5	1		T126	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T41	2		T25	1		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T23	1		T26	5		T208	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T122	1		T234	5		T173	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	5		T25	1		T48	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	11		T123	12		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	1		T122	1		T124	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T53	12		T127	9		T78	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T2	13		T5	9		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T6	1		T39	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T186	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T253	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T115	12		T80	14		T268	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	9		T210	16		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	13		T41	12		T53	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T6	12		T42	12		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T42	7		T124	13		T133	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T130	7		T14	1		T216	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T34	15		T124	12		T89	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T38	47		T40	40		T21	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	15		T121	7		T12	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	13		T5	12		T89	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T41	29		T25	14		T26	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T26	5		T122	7		T153	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T122	11		T234	3		T173	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	1		T25	4		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	7		T123	15		T228	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T122	11		T124	8		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T53	10		T127	7		T132	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T5	15		T39	7		T115	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	10		T39	4		T25	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27