Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24211

1

T1

27

T2

13

T3

129

auto[ADC_CTRL_FILTER_COND_OUT]

3114

1

T2

20

T3

18

T4

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21160

1

T2

20

T3

128

T4

1

auto[1]

6165

1

T1

27

T2

13

T3

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	826	1			T3	1		T4	1		T8	10
values[0]	25	1			T256	20		T291	5		-	-
values[1]	712	1			T1	27		T34	31		T23	1
values[2]	2968	1			T5	13		T7	6		T9	1
values[3]	713	1			T131	9		T124	20		T123	27
values[4]	535	1			T4	1		T6	16		T42	8
values[5]	786	1			T2	11		T115	5		T123	27
values[6]	519	1			T2	13		T4	1		T41	17
values[7]	658	1			T3	18		T6	24		T11	6
values[8]	793	1			T41	14		T42	13		T25	18
values[9]	910	1			T2	9		T5	24		T34	32
minimum	17880	1			T3	128		T8	136		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	738	1			T1	27		T34	31		T122	12
values[1]	2902	1			T5	13		T7	6		T9	1
values[2]	783	1			T42	8		T25	15		T131	9
values[3]	637	1			T4	1		T6	16		T208	2
values[4]	625	1			T2	11		T129	1		T115	5
values[5]	609	1			T2	13		T4	1		T6	24
values[6]	556	1			T3	18		T11	6		T23	1
values[7]	804	1			T41	14		T42	13		T11	19
values[8]	968	1			T2	9		T4	1		T5	24
values[9]	227	1			T25	5		T216	30		T133	20
minimum	18476	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	14		T34	14		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T122	12		T12	3		T244	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1686	1			T5	13		T7	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	8		T30	1		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T42	8		T25	15		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T131	1		T125	1		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	1		T90	7		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	16		T208	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T115	1		T78	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	1		T129	1		T123	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	1		T6	24		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T4	1		T41	17		T26	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T23	1		T53	8		T130	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	8		T11	4		T131	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T42	13		T131	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T41	14		T11	14		T25	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T4	1		T34	16		T22	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T5	16		T39	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T133	10		T207	1		T16	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T25	5		T216	13		T264	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18240	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T292	1		T293	1		T277	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	13		T34	17		T247	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	2		T249	25		T241	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T7	5		T92	22		T28	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T35	3		T165	6		T173	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T123	14		T234	4		T165	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T131	8		T125	14		T213	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T231	2		T189	16		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T208	1		T126	2		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T115	4		T78	16		T231	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	10		T123	11		T125	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	12		T48	3		T136	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T26	4		T121	9		T210	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	9		T31	11		T251	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	10		T11	2		T115	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	2		T115	14		T121	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	5		T89	12		T179	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T34	16		T22	2		T121	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	8		T5	8		T26	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T133	10		T207	1		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T216	17		T264	11		T159	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	1		T66	1		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T292	1		T293	8		T277	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	548	1			T3	1		T4	1		T8	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T26	6		T124	9		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T256	11		T291	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	14		T34	14		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T122	12		T12	3		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1690	1			T5	13		T7	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	8		T33	4		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T124	13		T123	13		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T131	1		T125	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	1		T42	8		T25	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	16		T208	1		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T115	1		T78	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T123	16		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	1		T74	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T4	1		T41	17		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	24		T23	1		T53	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	8		T11	4		T26	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T42	13		T115	13		T121	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T41	14		T25	18		T131	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T34	16		T22	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	1		T5	16		T39	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17741	1			T3	127		T8	136		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T22	2		T121	7		T16	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T124	14		T127	1		T209	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T256	9		T291	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	13		T34	17		T247	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	2		T249	25		T241	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T7	5		T92	22		T28	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T165	6		T173	13		T32	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T124	7		T123	14		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T131	8		T125	14		T213	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T231	2		T37	2		T212	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T208	1		T33	2		T235	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T115	4		T78	16		T231	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	10		T123	11		T125	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	12		T48	3		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T121	9		T210	9		T156	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T130	9		T31	11		T251	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	10		T11	2		T26	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T115	14		T121	10		T124	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T89	12		T179	8		T294	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T34	16		T131	2		T89	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	8		T5	8		T11	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	14		T34	18		T247	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T122	1		T12	4		T244	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T5	1		T7	6		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	1		T30	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T42	1		T25	1		T123	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T131	9		T125	15		T213	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	1		T90	1		T231	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	1		T208	2		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T115	5		T78	17		T231	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	11		T129	1		T123	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	13		T6	2		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T4	1		T41	1		T26	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T23	1		T53	1		T130	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	11		T11	5		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	1		T131	3		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	1		T11	10		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T4	1		T34	17		T22	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	9		T5	9		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T133	11		T207	2		T16	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T25	1		T216	18		T264	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18371	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T292	2		T293	9		T277	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	13		T34	13		T132	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T122	11		T12	1		T229	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T5	12		T38	47		T40	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T39	7		T33	1		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T42	7		T25	14		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T227	8		T235	13		T223	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T90	6		T189	16		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	15		T33	1		T295	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T227	2		T37	1		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T123	15		T80	14		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	22		T122	11		T254	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T41	16		T26	5		T121	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T53	7		T130	7		T90	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T3	7		T11	1		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T42	12		T115	12		T121	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T41	13		T11	9		T25	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T34	15		T22	6		T121	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	15		T39	4		T41	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T133	9		T16	1		T226	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T25	4		T216	12		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T153	12		T185	7		T241	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T277	8		T296	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	553	1			T3	1		T4	1		T8	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T26	1		T124	15		T127	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T256	10		T291	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	14		T34	18		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T122	1		T12	4		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T5	1		T7	6		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	1		T33	3		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T124	8		T123	15		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T131	9		T125	15		T213	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	1		T42	1		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T208	2		T33	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T115	5		T78	17		T231	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	11		T123	12		T125	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	13		T74	1		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T4	1		T41	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	2		T23	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	11		T11	5		T26	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T42	1		T115	15		T121	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	1		T25	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T34	17		T22	1		T131	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	9		T5	9		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T3	128		T8	136		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T22	6		T121	8		T16	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T26	5		T124	8		T209	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T256	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	13		T34	13		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T122	11		T12	1		T229	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T5	12		T38	47		T40	40
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	7		T33	1		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T124	12		T123	12		T234	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T35	1		T227	8		T223	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T42	7		T25	14		T90	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	15		T33	1		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T189	16		T227	2		T165	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T123	15		T80	14		T153	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	1		T235	12		T157	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T41	16		T121	7		T210	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	22		T53	7		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	7		T11	1		T26	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T42	12		T115	12		T121	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T41	13		T25	17		T131	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	15		T89	11		T228	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	15		T39	4		T41	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27