Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23893

1

T2

9

T3

147

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3432

1

T1

27

T2

24

T4

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21434

1

T2

33

T3

147

T4

2

auto[1]

5891

1

T1

27

T4

1

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	272	1			T23	1		T53	8		T125	5
values[0]	7	1			T253	7		-	-		-	-
values[1]	578	1			T4	1		T11	6		T22	9
values[2]	736	1			T41	31		T131	3		T124	43
values[3]	722	1			T23	1		T115	22		T122	8
values[4]	878	1			T2	9		T4	1		T5	37
values[5]	2862	1			T1	27		T6	11		T7	6
values[6]	712	1			T4	1		T11	19		T25	18
values[7]	749	1			T3	18		T6	13		T41	13
values[8]	640	1			T34	31		T26	6		T123	27
values[9]	857	1			T2	24		T6	16		T22	1
minimum	18312	1			T3	129		T8	146		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	724	1			T4	1		T41	31		T11	6
values[1]	753	1			T131	3		T124	23		T127	16
values[2]	736	1			T5	13		T23	1		T129	1
values[3]	3021	1			T2	9		T4	1		T5	24
values[4]	666	1			T1	27		T6	11		T34	32
values[5]	684	1			T4	1		T25	18		T121	17
values[6]	835	1			T3	18		T6	13		T34	31
values[7]	439	1			T2	13		T22	1		T122	12
values[8]	941	1			T2	11		T6	16		T23	1
values[9]	117	1			T247	20		T212	3		T258	10
minimum	18409	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T41	31		T33	3		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	1		T11	4		T22	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T124	9		T142	1		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T131	1		T127	8		T216	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	13		T122	8		T189	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T23	1		T129	1		T115	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T2	1		T4	1		T5	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T39	13		T42	21		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	11		T34	16		T26	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	14		T11	14		T25	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T121	8		T122	12		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T25	18		T12	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	8		T34	14		T123	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	13		T41	13		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T22	1		T89	12		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T122	12		T90	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T6	16		T23	1		T25	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T53	8		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T212	1		T258	10		T284	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T247	2		T273	11		T274	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18205	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T121	9		T297	1		T157	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	2		T31	11		T153	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	2		T22	2		T121	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T124	14		T181	10		T279	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T131	2		T127	8		T216	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T189	1		T207	12		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T115	23		T213	12		T78	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T2	8		T5	8		T7	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T131	8		T208	1		T209	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T34	16		T26	10		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	13		T11	5		T125	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T121	9		T123	14		T126	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	2		T48	3		T132	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	10		T34	17		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T53	11		T127	1		T280	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T89	8		T31	3		T264	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	12		T189	1		T138	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T130	9		T215	10		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	10		T125	4		T135	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T212	2		T284	9		T298	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T247	18		T187	12		T276	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	1		T66	1		T115	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T121	7		T157	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T23	1		T258	10		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	8		T125	1		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T253	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T115	1		T124	14		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T11	4		T22	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	31		T124	9		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T131	1		T124	13		T127	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T122	8		T189	1		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T23	1		T115	13		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T4	1		T5	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T39	8		T42	21		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T6	11		T7	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	14		T39	5		T25	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T121	8		T122	12		T123	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	1		T11	14		T25	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	8		T127	8		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	13		T41	13		T53	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T34	14		T123	16		T89	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T26	6		T90	7		T233	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T6	16		T22	1		T25	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	2		T122	12		T247	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T284	9		T289	12		T252	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T125	4		T247	5		T135	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T253	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T115	4		T124	8		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	2		T22	2		T121	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T124	14		T241	8		T279	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T131	2		T124	7		T127	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T189	1		T181	10		T207	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T115	9		T213	12		T78	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	8		T5	8		T26	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T131	8		T115	14		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T7	5		T34	16		T92	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	13		T208	1		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T121	9		T123	14		T126	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	5		T125	14		T12	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	10		T133	10		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T53	11		T127	1		T280	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	17		T123	11		T89	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T233	9		T165	13		T156	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T130	9		T215	10		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	22		T247	13		T189	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T41	2		T33	4		T31	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	1		T11	5		T22	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T124	15		T142	1		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T131	3		T127	9		T216	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T122	1		T189	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T23	1		T129	1		T115	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T2	9		T4	1		T5	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T39	2		T42	2		T131	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T34	17		T26	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	14		T11	10		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T121	10		T122	1		T123	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	1		T25	1		T12	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	11		T34	18		T123	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	1		T41	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T22	1		T89	9		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	13		T122	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T6	1		T23	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	11		T53	1		T125	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T212	3		T258	1		T284	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T247	20		T273	1		T274	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18354	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T121	8		T297	1		T157	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	29		T33	1		T153	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T22	6		T121	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T124	8		T254	15		T137	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T127	7		T216	12		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T122	7		T207	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T115	24		T80	10		T270	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T5	15		T38	47		T40	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	11		T42	19		T209	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	10		T34	15		T26	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	13		T11	9		T25	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T121	7		T122	11		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T25	17		T12	1		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	7		T34	13		T123	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	12		T41	12		T26	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T89	11		T31	3		T264	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T122	11		T90	6		T133	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T6	15		T25	14		T208	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T53	7		T135	11		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T258	9		T284	7		T298	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T273	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T124	13		T254	4		T20	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T121	8		T157	3		T278	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T23	1		T258	1		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T53	1		T125	5		T247	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T253	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T115	5		T124	9		T33	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	1		T11	5		T22	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	2		T124	15		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T131	3		T124	8		T127	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T122	1		T189	2		T181	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T23	1		T115	10		T213	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	9		T4	1		T5	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T39	1		T42	2		T131	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T6	1		T7	6		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	14		T39	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T121	10		T122	1		T123	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T11	10		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	11		T127	1		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T41	1		T53	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	18		T123	12		T89	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T26	1		T90	1		T233	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	1		T22	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	24		T122	1		T247	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T258	9		T284	7		T289	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T53	7		T135	11		T273	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T253	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T124	13		T33	1		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T22	6		T121	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	29		T124	8		T241	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T124	12		T127	7		T216	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T122	7		T207	8		T254	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T115	12		T80	10		T214	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	27		T26	5		T90	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T39	7		T42	19		T115	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T6	10		T34	15		T38	47
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	13		T39	4		T25	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T121	7		T122	11		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	9		T25	17		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	7		T127	7		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	12		T41	12		T53	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T34	13		T123	15		T89	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T26	5		T90	6		T233	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	15		T25	14		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T122	11		T222	12		T137	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27