Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27325

1

T1

27

T2

33

T3

147

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24086

1

T1

27

T2

11

T3

129

auto[ADC_CTRL_FILTER_COND_OUT]

3239

1

T2

22

T3

18

T4

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20960

1

T2

13

T3

128

T4

1

auto[1]

6365

1

T1

27

T2

20

T3

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23457

1

T1

14

T2

3

T3

136

auto[1]

3868

1

T1

13

T2

30

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	488	1			T3	1		T8	10		T44	1
values[0]	38	1			T279	12		T299	1		T256	20
values[1]	695	1			T34	31		T23	1		T122	12
values[2]	2966	1			T1	27		T5	13		T7	6
values[3]	670	1			T25	15		T131	9		T124	20
values[4]	628	1			T2	11		T4	1		T6	16
values[5]	732	1			T115	5		T123	27		T125	5
values[6]	569	1			T2	13		T4	1		T6	13
values[7]	579	1			T3	18		T6	11		T11	6
values[8]	836	1			T41	14		T42	13		T25	18
values[9]	1244	1			T2	9		T4	1		T5	24
minimum	17880	1			T3	128		T8	136		T47	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	882	1			T34	31		T23	1		T122	12
values[1]	2946	1			T1	27		T5	13		T7	6
values[2]	756	1			T131	9		T123	27		T125	15
values[3]	600	1			T4	1		T6	16		T42	8
values[4]	619	1			T2	11		T115	5		T123	27
values[5]	666	1			T4	1		T6	24		T41	17
values[6]	555	1			T2	13		T3	18		T11	6
values[7]	820	1			T41	14		T42	13		T11	19
values[8]	891	1			T2	9		T5	24		T39	5
values[9]	277	1			T4	1		T34	32		T22	9
minimum	18313	1			T3	129		T8	146		T47	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

4206

1

T1

13

T3

7

T5

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T34	14		T23	1		T122	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T12	3		T300	3		T229	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1697	1			T1	14		T5	13		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T39	8		T33	4		T35	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T125	1		T30	1		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T131	1		T123	13		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T42	8		T90	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	16		T25	15		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	1		T78	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T115	1		T123	16		T75	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	24		T41	17		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	1		T26	6		T53	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T121	11		T130	9		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T3	8		T11	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T41	14		T42	13		T25	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	14		T208	8		T127	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T22	1		T25	5		T26	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T5	16		T39	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T4	1		T34	16		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T22	7		T78	1		T216	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18173	1			T3	128		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T288	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T34	17		T247	5		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	2		T241	8		T279	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T1	13		T7	5		T92	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	3		T74	4		T280	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T125	14		T31	3		T234	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	8		T123	14		T213	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T189	16		T37	2		T212	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T208	1		T126	2		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	10		T78	16		T231	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T115	4		T123	11		T48	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T48	3		T210	9		T301	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	4		T121	9		T125	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T121	10		T130	9		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T2	12		T3	10		T11	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T131	2		T115	14		T124	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	5		T89	12		T179	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T26	10		T121	7		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	8		T5	8		T127	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T34	16		T181	10		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T22	2		T78	9		T216	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	455	1			T3	1		T8	10		T44	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T22	7		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T299	1		T256	11		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	14		T23	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	3		T300	3		T229	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1701	1			T1	14		T5	13		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	8		T33	4		T74	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T124	13		T125	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T25	15		T131	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T4	1		T42	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	16		T208	1		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T78	1		T231	1		T227	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T115	1		T123	16		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	13		T41	17		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	1		T4	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	11		T122	12		T130	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	8		T11	4		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T41	14		T42	13		T25	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T131	14		T208	8		T127	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T4	1		T34	16		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T2	1		T5	16		T39	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17741	1			T3	127		T8	136		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T218	8		T248	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T22	2		T302	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T256	9		T291	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T279	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	17		T247	5		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	2		T241	8		T292	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T1	13		T7	5		T92	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T74	4		T280	12		T165	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T124	7		T125	14		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T131	8		T213	12		T126	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	10		T189	16		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T208	1		T123	14		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T78	16		T231	4		T165	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T115	4		T123	11		T125	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T48	3		T210	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	12		T121	9		T235	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T130	9		T128	9		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T3	10		T11	2		T26	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T115	14		T121	10		T124	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T89	12		T294	2		T303	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T34	16		T26	10		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	8		T5	8		T11	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T66	1		T123	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T34	18		T23	1		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	4		T300	3		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T1	14		T5	1		T7	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	1		T33	3		T35	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T125	15		T30	1		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T131	9		T123	15		T213	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T42	1		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T25	1		T208	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	11		T78	17		T231	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T115	5		T123	12		T75	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	2		T41	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T26	5		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T121	11		T130	11		T128	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	13		T3	11		T11	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	1		T42	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T11	10		T208	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T22	1		T25	1		T26	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	9		T5	9		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T4	1		T34	17		T181	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T22	3		T78	10		T216	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18312	1			T3	129		T8	146		T47	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T288	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T34	13		T122	11		T153	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	1		T229	7		T270	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T1	13		T5	12		T38	47
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T39	7		T33	1		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T31	3		T234	3		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T123	12		T227	8		T223	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T42	7		T90	6		T189	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	15		T25	14		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T227	2		T37	1		T165	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T123	15		T80	14		T153	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	22		T41	16		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	5		T53	7		T121	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T121	10		T130	7		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	7		T11	1		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T41	13		T42	12		T25	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	9		T208	7		T127	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T25	4		T26	18		T121	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	15		T39	4		T41	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T34	15		T133	9		T264	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T22	6		T216	12		T273	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	451	1			T3	1		T8	10		T44	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T22	3		T302	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T299	1		T256	10		T291	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T279	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	18		T23	1		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	4		T300	3		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T1	14		T5	1		T7	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	1		T33	3		T74	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T124	8		T125	15		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T25	1		T131	9		T213	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	11		T4	1		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T208	2		T123	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T78	17		T231	5		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T115	5		T123	12		T125	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T6	1		T41	1		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	13		T4	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	1		T122	1		T130	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	11		T11	5		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T41	1		T42	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T131	1		T208	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	411	1			T4	1		T34	17		T22	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T2	9		T5	9		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T3	128		T8	136		T47	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T270	8		T248	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T22	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T256	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	13		T122	11		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T229	7		T270	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T1	13		T5	12		T38	47
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	7		T33	1		T74	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T124	12		T234	3		T165	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T25	14		T35	1		T233	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T42	7		T90	6		T189	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	15		T123	12		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T227	2		T165	11		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T123	15		T80	14		T153	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	12		T41	16		T210	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T121	7		T235	12		T136	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	10		T122	11		T130	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	7		T11	1		T26	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T41	13		T42	12		T25	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T131	13		T208	7		T127	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T34	15		T25	4		T26	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	15		T39	4		T41	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23119

1

T1

14

T2

33

T3

140

auto[1]

auto[0]

4206

1

T1

13

T3

7

T5

27