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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.32


Total test records in report: 918
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T791 /workspace/coverage/default/44.adc_ctrl_filters_polled.760829655 Apr 25 01:20:45 PM PDT 24 Apr 25 01:38:53 PM PDT 24 493551967832 ps
T792 /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3460527074 Apr 25 01:13:39 PM PDT 24 Apr 25 01:20:09 PM PDT 24 163151906613 ps
T793 /workspace/coverage/default/28.adc_ctrl_lowpower_counter.146525694 Apr 25 01:17:07 PM PDT 24 Apr 25 01:18:24 PM PDT 24 43319168823 ps
T93 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2675900082 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:45 PM PDT 24 388942759 ps
T794 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4019991657 Apr 25 12:47:53 PM PDT 24 Apr 25 12:47:57 PM PDT 24 312730553 ps
T54 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4183993661 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:56 PM PDT 24 8241955432 ps
T795 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2659444317 Apr 25 12:47:56 PM PDT 24 Apr 25 12:47:59 PM PDT 24 477955338 ps
T57 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.237709995 Apr 25 12:47:43 PM PDT 24 Apr 25 12:47:53 PM PDT 24 552480259 ps
T796 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.312934857 Apr 25 12:47:58 PM PDT 24 Apr 25 12:48:00 PM PDT 24 502339897 ps
T797 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3839286544 Apr 25 12:48:02 PM PDT 24 Apr 25 12:48:04 PM PDT 24 283012417 ps
T798 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3939724720 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:54 PM PDT 24 408545089 ps
T55 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3576737918 Apr 25 12:47:50 PM PDT 24 Apr 25 12:48:05 PM PDT 24 7827465810 ps
T61 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2936952347 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:43 PM PDT 24 554800376 ps
T62 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3930821539 Apr 25 12:47:51 PM PDT 24 Apr 25 12:47:58 PM PDT 24 541028382 ps
T799 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3230558470 Apr 25 12:47:37 PM PDT 24 Apr 25 12:47:40 PM PDT 24 361063977 ps
T800 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1699474640 Apr 25 12:47:56 PM PDT 24 Apr 25 12:47:59 PM PDT 24 408356115 ps
T801 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1004093675 Apr 25 12:47:54 PM PDT 24 Apr 25 12:47:57 PM PDT 24 523056339 ps
T50 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3897613046 Apr 25 12:47:41 PM PDT 24 Apr 25 12:49:14 PM PDT 24 27107755565 ps
T802 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.464747327 Apr 25 12:48:00 PM PDT 24 Apr 25 12:48:04 PM PDT 24 520435411 ps
T107 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.872674693 Apr 25 12:47:45 PM PDT 24 Apr 25 12:47:49 PM PDT 24 376654257 ps
T51 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3206233321 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:48 PM PDT 24 2760316433 ps
T803 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3644467046 Apr 25 12:48:00 PM PDT 24 Apr 25 12:48:02 PM PDT 24 503151065 ps
T804 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2381588912 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:54 PM PDT 24 311606870 ps
T67 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3826906236 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:54 PM PDT 24 443950743 ps
T63 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.730116954 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:55 PM PDT 24 594720954 ps
T64 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2696865708 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:46 PM PDT 24 466944407 ps
T94 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1488425780 Apr 25 12:47:46 PM PDT 24 Apr 25 12:47:53 PM PDT 24 1251774367 ps
T805 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3192083461 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:41 PM PDT 24 391717506 ps
T65 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3408596576 Apr 25 12:47:55 PM PDT 24 Apr 25 12:47:59 PM PDT 24 761739952 ps
T52 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3512847283 Apr 25 12:47:47 PM PDT 24 Apr 25 12:48:13 PM PDT 24 22138001104 ps
T70 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4193490387 Apr 25 12:47:54 PM PDT 24 Apr 25 12:47:57 PM PDT 24 442212866 ps
T806 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.339368009 Apr 25 12:48:04 PM PDT 24 Apr 25 12:48:06 PM PDT 24 474951447 ps
T807 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2199187723 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:41 PM PDT 24 507575657 ps
T95 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3810867411 Apr 25 12:47:51 PM PDT 24 Apr 25 12:47:55 PM PDT 24 556502587 ps
T808 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.460219869 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:54 PM PDT 24 341235824 ps
T108 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.317496872 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:46 PM PDT 24 2284234751 ps
T109 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4196284232 Apr 25 12:47:45 PM PDT 24 Apr 25 12:47:59 PM PDT 24 2562486026 ps
T56 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1486019095 Apr 25 12:47:47 PM PDT 24 Apr 25 12:48:03 PM PDT 24 4367620526 ps
T96 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.992252812 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:55 PM PDT 24 478238181 ps
T809 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3273383691 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:48 PM PDT 24 437103533 ps
T110 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2493633927 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:55 PM PDT 24 611190743 ps
T810 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3574349143 Apr 25 12:47:41 PM PDT 24 Apr 25 12:47:47 PM PDT 24 1484132529 ps
T337 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3109927727 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:47 PM PDT 24 4394024889 ps
T97 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.189184754 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:48 PM PDT 24 393380956 ps
T335 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.8764967 Apr 25 12:47:49 PM PDT 24 Apr 25 12:48:00 PM PDT 24 4226509622 ps
T811 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1440558566 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:55 PM PDT 24 523076912 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3582274711 Apr 25 12:47:43 PM PDT 24 Apr 25 12:47:46 PM PDT 24 408075002 ps
T111 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1035194669 Apr 25 12:47:46 PM PDT 24 Apr 25 12:47:56 PM PDT 24 4658488956 ps
T813 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3956116601 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:54 PM PDT 24 354292902 ps
T814 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2904836476 Apr 25 12:47:36 PM PDT 24 Apr 25 12:49:21 PM PDT 24 26592811035 ps
T112 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2501586146 Apr 25 12:47:51 PM PDT 24 Apr 25 12:48:00 PM PDT 24 5215338610 ps
T815 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1215931237 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:51 PM PDT 24 384609844 ps
T816 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2554662551 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:55 PM PDT 24 946417818 ps
T817 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2807816749 Apr 25 12:47:55 PM PDT 24 Apr 25 12:47:58 PM PDT 24 500621722 ps
T818 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2721587403 Apr 25 12:47:57 PM PDT 24 Apr 25 12:48:01 PM PDT 24 387074451 ps
T819 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3804782567 Apr 25 12:47:51 PM PDT 24 Apr 25 12:47:56 PM PDT 24 519154017 ps
T113 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.174607129 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:45 PM PDT 24 438391022 ps
T820 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3361804307 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:51 PM PDT 24 991836398 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2038708125 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:48 PM PDT 24 2750076513 ps
T98 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4259074524 Apr 25 12:47:37 PM PDT 24 Apr 25 12:47:41 PM PDT 24 1183565669 ps
T821 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2810048375 Apr 25 12:47:57 PM PDT 24 Apr 25 12:48:01 PM PDT 24 2553430814 ps
T99 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.409067807 Apr 25 12:47:35 PM PDT 24 Apr 25 12:47:53 PM PDT 24 14944979001 ps
T822 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3592936234 Apr 25 12:47:35 PM PDT 24 Apr 25 12:47:38 PM PDT 24 340571986 ps
T823 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3668685930 Apr 25 12:47:34 PM PDT 24 Apr 25 12:47:37 PM PDT 24 371554752 ps
T824 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3547633767 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:56 PM PDT 24 612334260 ps
T825 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2009342078 Apr 25 12:47:59 PM PDT 24 Apr 25 12:48:01 PM PDT 24 363443872 ps
T826 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1522035125 Apr 25 12:47:59 PM PDT 24 Apr 25 12:48:01 PM PDT 24 433385816 ps
T827 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3844372280 Apr 25 12:47:36 PM PDT 24 Apr 25 12:47:42 PM PDT 24 5492694587 ps
T336 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.547985218 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:54 PM PDT 24 8237682896 ps
T828 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2805412016 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:53 PM PDT 24 3541522398 ps
T829 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.630782021 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:09 PM PDT 24 575056587 ps
T71 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1355701275 Apr 25 12:47:48 PM PDT 24 Apr 25 12:48:00 PM PDT 24 8707812929 ps
T830 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1188170816 Apr 25 12:47:41 PM PDT 24 Apr 25 12:47:45 PM PDT 24 430373271 ps
T831 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.17926169 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:51 PM PDT 24 4979028814 ps
T832 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3827982138 Apr 25 12:47:51 PM PDT 24 Apr 25 12:47:56 PM PDT 24 517949790 ps
T833 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2326216626 Apr 25 12:48:04 PM PDT 24 Apr 25 12:48:06 PM PDT 24 672432549 ps
T834 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3379335945 Apr 25 12:47:54 PM PDT 24 Apr 25 12:47:59 PM PDT 24 515787507 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2182922658 Apr 25 12:47:36 PM PDT 24 Apr 25 12:47:41 PM PDT 24 523215218 ps
T836 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3319414247 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:56 PM PDT 24 4437721710 ps
T837 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.487512763 Apr 25 12:47:58 PM PDT 24 Apr 25 12:48:00 PM PDT 24 468592703 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.384624271 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:45 PM PDT 24 552988540 ps
T839 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2636809681 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:52 PM PDT 24 306872677 ps
T840 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3219045228 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:47 PM PDT 24 4300806192 ps
T841 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2016837154 Apr 25 12:47:59 PM PDT 24 Apr 25 12:48:02 PM PDT 24 471981305 ps
T100 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.631966846 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:52 PM PDT 24 1199490345 ps
T842 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1318030383 Apr 25 12:47:57 PM PDT 24 Apr 25 12:47:59 PM PDT 24 474757201 ps
T843 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1619671697 Apr 25 12:47:51 PM PDT 24 Apr 25 12:47:56 PM PDT 24 281127078 ps
T844 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1930633009 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:47 PM PDT 24 450452451 ps
T845 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3906002114 Apr 25 12:47:37 PM PDT 24 Apr 25 12:47:40 PM PDT 24 597380408 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4200909272 Apr 25 12:48:14 PM PDT 24 Apr 25 12:48:17 PM PDT 24 356975188 ps
T847 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.312945531 Apr 25 12:48:01 PM PDT 24 Apr 25 12:48:03 PM PDT 24 552625358 ps
T101 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.649159068 Apr 25 12:47:36 PM PDT 24 Apr 25 12:47:42 PM PDT 24 1226305144 ps
T102 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3792657763 Apr 25 12:47:57 PM PDT 24 Apr 25 12:48:00 PM PDT 24 537448101 ps
T848 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2202229438 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:52 PM PDT 24 316354903 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.473071055 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:41 PM PDT 24 345335683 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3811304658 Apr 25 12:47:35 PM PDT 24 Apr 25 12:47:40 PM PDT 24 5068371614 ps
T851 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1269883102 Apr 25 12:47:57 PM PDT 24 Apr 25 12:48:00 PM PDT 24 498719092 ps
T852 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.385691799 Apr 25 12:47:41 PM PDT 24 Apr 25 12:47:43 PM PDT 24 642753291 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1651288296 Apr 25 12:47:43 PM PDT 24 Apr 25 12:47:46 PM PDT 24 451251713 ps
T854 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2141856168 Apr 25 12:48:01 PM PDT 24 Apr 25 12:48:03 PM PDT 24 550769855 ps
T855 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3135505349 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:45 PM PDT 24 517909337 ps
T856 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3518384273 Apr 25 12:47:58 PM PDT 24 Apr 25 12:48:01 PM PDT 24 518763480 ps
T857 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2586903617 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:54 PM PDT 24 482788363 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.488044956 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:48 PM PDT 24 317002945 ps
T859 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2686642428 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:54 PM PDT 24 1125700241 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3094577222 Apr 25 12:47:42 PM PDT 24 Apr 25 12:47:46 PM PDT 24 498531112 ps
T861 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2632093446 Apr 25 12:47:48 PM PDT 24 Apr 25 12:48:02 PM PDT 24 4070326539 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.958027418 Apr 25 12:47:46 PM PDT 24 Apr 25 12:47:51 PM PDT 24 497848136 ps
T863 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1511165044 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:52 PM PDT 24 4439581184 ps
T864 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.468768883 Apr 25 12:47:48 PM PDT 24 Apr 25 12:48:01 PM PDT 24 2308144998 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2028430679 Apr 25 12:47:41 PM PDT 24 Apr 25 12:47:44 PM PDT 24 478399723 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1061508520 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:54 PM PDT 24 517988209 ps
T867 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1033130612 Apr 25 12:48:07 PM PDT 24 Apr 25 12:48:10 PM PDT 24 529772461 ps
T868 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4205962848 Apr 25 12:47:51 PM PDT 24 Apr 25 12:47:55 PM PDT 24 576112594 ps
T869 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1558943692 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:54 PM PDT 24 558103916 ps
T870 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3444055424 Apr 25 12:47:36 PM PDT 24 Apr 25 12:47:41 PM PDT 24 968203899 ps
T871 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4215476531 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:42 PM PDT 24 473628150 ps
T872 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2674943534 Apr 25 12:47:45 PM PDT 24 Apr 25 12:47:49 PM PDT 24 592476185 ps
T103 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.132389355 Apr 25 12:47:36 PM PDT 24 Apr 25 12:47:40 PM PDT 24 459721597 ps
T873 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1249224703 Apr 25 12:47:43 PM PDT 24 Apr 25 12:47:47 PM PDT 24 375222333 ps
T874 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1065740745 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:55 PM PDT 24 519082992 ps
T875 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.885696150 Apr 25 12:47:45 PM PDT 24 Apr 25 12:47:49 PM PDT 24 542276612 ps
T876 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2609073284 Apr 25 12:47:51 PM PDT 24 Apr 25 12:47:55 PM PDT 24 315113649 ps
T877 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.443145240 Apr 25 12:47:32 PM PDT 24 Apr 25 12:47:53 PM PDT 24 8231261686 ps
T878 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.971976450 Apr 25 12:47:37 PM PDT 24 Apr 25 12:47:40 PM PDT 24 358185950 ps
T104 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1693049316 Apr 25 12:47:38 PM PDT 24 Apr 25 12:47:41 PM PDT 24 384298357 ps
T879 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3004189153 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:57 PM PDT 24 4645781850 ps
T880 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.944630263 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:56 PM PDT 24 3372574802 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3310158606 Apr 25 12:47:35 PM PDT 24 Apr 25 12:47:43 PM PDT 24 5084280388 ps
T882 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3511194122 Apr 25 12:47:50 PM PDT 24 Apr 25 12:48:06 PM PDT 24 2816024502 ps
T883 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2495871062 Apr 25 12:47:43 PM PDT 24 Apr 25 12:47:47 PM PDT 24 359667872 ps
T884 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2136342904 Apr 25 12:47:35 PM PDT 24 Apr 25 12:47:38 PM PDT 24 366798312 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1307403973 Apr 25 12:47:48 PM PDT 24 Apr 25 12:48:15 PM PDT 24 8465710480 ps
T886 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3518990204 Apr 25 12:47:48 PM PDT 24 Apr 25 12:48:01 PM PDT 24 7983747290 ps
T887 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3986792841 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:56 PM PDT 24 3612104752 ps
T105 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3909532820 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:49 PM PDT 24 1148627930 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.846270745 Apr 25 12:47:49 PM PDT 24 Apr 25 12:48:11 PM PDT 24 4924532076 ps
T889 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2941334159 Apr 25 12:47:52 PM PDT 24 Apr 25 12:47:59 PM PDT 24 1945269780 ps
T890 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2819393213 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:58 PM PDT 24 8733575043 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3284601012 Apr 25 12:47:52 PM PDT 24 Apr 25 12:47:58 PM PDT 24 4318135029 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.313665138 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:55 PM PDT 24 374644964 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1869115985 Apr 25 12:47:45 PM PDT 24 Apr 25 12:47:48 PM PDT 24 316214824 ps
T894 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1515718827 Apr 25 12:47:55 PM PDT 24 Apr 25 12:48:01 PM PDT 24 438517573 ps
T895 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3040521720 Apr 25 12:47:58 PM PDT 24 Apr 25 12:48:02 PM PDT 24 831895790 ps
T896 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1210727486 Apr 25 12:47:57 PM PDT 24 Apr 25 12:47:59 PM PDT 24 343822977 ps
T897 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.999514368 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:55 PM PDT 24 671308726 ps
T898 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.117950176 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:56 PM PDT 24 393752784 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1890746506 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:53 PM PDT 24 504889472 ps
T900 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2609275213 Apr 25 12:48:20 PM PDT 24 Apr 25 12:48:22 PM PDT 24 399520211 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1706207706 Apr 25 12:47:50 PM PDT 24 Apr 25 12:48:01 PM PDT 24 4740347360 ps
T902 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1566482180 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:51 PM PDT 24 4552158153 ps
T903 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3173004423 Apr 25 12:47:43 PM PDT 24 Apr 25 12:47:46 PM PDT 24 2372838349 ps
T904 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.723674780 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:59 PM PDT 24 2363329109 ps
T905 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.455366020 Apr 25 12:47:49 PM PDT 24 Apr 25 12:47:54 PM PDT 24 320452462 ps
T906 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2680280089 Apr 25 12:47:54 PM PDT 24 Apr 25 12:47:58 PM PDT 24 461737465 ps
T907 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2309857652 Apr 25 12:47:50 PM PDT 24 Apr 25 12:47:55 PM PDT 24 507767336 ps
T908 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.325047248 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:52 PM PDT 24 356211542 ps
T909 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3638525074 Apr 25 12:47:43 PM PDT 24 Apr 25 12:47:46 PM PDT 24 568915341 ps
T106 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2809233102 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:49 PM PDT 24 1857971529 ps
T910 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3788668838 Apr 25 12:47:44 PM PDT 24 Apr 25 12:47:49 PM PDT 24 5401899622 ps
T911 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2089512758 Apr 25 12:47:41 PM PDT 24 Apr 25 12:47:44 PM PDT 24 447712475 ps
T912 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1418272877 Apr 25 12:47:45 PM PDT 24 Apr 25 12:47:48 PM PDT 24 657788729 ps
T913 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.515460448 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:55 PM PDT 24 4789897481 ps
T914 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.274584749 Apr 25 12:47:45 PM PDT 24 Apr 25 12:47:50 PM PDT 24 395422532 ps
T915 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3513782638 Apr 25 12:48:04 PM PDT 24 Apr 25 12:48:06 PM PDT 24 694937665 ps
T916 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1731379582 Apr 25 12:47:48 PM PDT 24 Apr 25 12:47:56 PM PDT 24 1327062951 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2402000611 Apr 25 12:47:40 PM PDT 24 Apr 25 12:47:43 PM PDT 24 1285332075 ps
T918 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3283390886 Apr 25 12:47:47 PM PDT 24 Apr 25 12:47:51 PM PDT 24 651741972 ps

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.295063661
Short name T3
Test name
Test status
Simulation time 260485332287 ps
CPU time 408.38 seconds
Started Apr 25 01:20:02 PM PDT 24
Finished Apr 25 01:26:51 PM PDT 24
Peak memory 202612 kb
Host smart-1a0d8518-9a27-481d-bf3a-f3fabedabb3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295063661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
295063661
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.46170042
Short name T6
Test name
Test status
Simulation time 548558374495 ps
CPU time 1213.79 seconds
Started Apr 25 01:13:21 PM PDT 24
Finished Apr 25 01:33:36 PM PDT 24
Peak memory 202332 kb
Host smart-b5b57b01-523d-4215-8f79-80dbc2aa43aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46170042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wa
keup.46170042
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1949821195
Short name T12
Test name
Test status
Simulation time 265371182720 ps
CPU time 612.88 seconds
Started Apr 25 01:13:24 PM PDT 24
Finished Apr 25 01:23:37 PM PDT 24
Peak memory 211016 kb
Host smart-b3119462-5345-43f9-acfa-ffbeb756b879
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949821195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1949821195
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2722555861
Short name T130
Test name
Test status
Simulation time 447826431156 ps
CPU time 559.02 seconds
Started Apr 25 01:13:31 PM PDT 24
Finished Apr 25 01:22:51 PM PDT 24
Peak memory 210816 kb
Host smart-5020201c-90d9-4a9c-8757-146d2725063f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722555861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2722555861
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.882533793
Short name T124
Test name
Test status
Simulation time 541815220973 ps
CPU time 1227.52 seconds
Started Apr 25 01:13:01 PM PDT 24
Finished Apr 25 01:33:29 PM PDT 24
Peak memory 202316 kb
Host smart-a6bb6e7f-58f4-47a5-a9e5-e0dc1294e078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882533793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.882533793
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1016021982
Short name T121
Test name
Test status
Simulation time 494503319541 ps
CPU time 1246.68 seconds
Started Apr 25 01:15:18 PM PDT 24
Finished Apr 25 01:36:06 PM PDT 24
Peak memory 202396 kb
Host smart-5aa41885-f27a-4fc8-b3bb-75a2cc3b98a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016021982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1016021982
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1726355687
Short name T133
Test name
Test status
Simulation time 507669740483 ps
CPU time 1232.47 seconds
Started Apr 25 01:13:33 PM PDT 24
Finished Apr 25 01:34:07 PM PDT 24
Peak memory 202192 kb
Host smart-c842787d-afbf-4b60-a1cd-b04f7aadb149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726355687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1726355687
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.410911877
Short name T26
Test name
Test status
Simulation time 488774645906 ps
CPU time 261.86 seconds
Started Apr 25 01:21:22 PM PDT 24
Finished Apr 25 01:25:45 PM PDT 24
Peak memory 202392 kb
Host smart-2e3a40bd-fe47-4cb4-896e-aa881b5991aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410911877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.410911877
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4016410338
Short name T153
Test name
Test status
Simulation time 488520055540 ps
CPU time 1065.28 seconds
Started Apr 25 01:12:47 PM PDT 24
Finished Apr 25 01:30:33 PM PDT 24
Peak memory 202320 kb
Host smart-ecbe7896-4256-4c47-8c3e-6b35e4726f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016410338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4016410338
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3440526539
Short name T264
Test name
Test status
Simulation time 502461762348 ps
CPU time 557.3 seconds
Started Apr 25 01:13:45 PM PDT 24
Finished Apr 25 01:23:03 PM PDT 24
Peak memory 202272 kb
Host smart-8c11b40f-4ac7-4258-9196-b23b142b0e13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440526539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3440526539
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1094630321
Short name T11
Test name
Test status
Simulation time 291723442034 ps
CPU time 270.26 seconds
Started Apr 25 01:13:16 PM PDT 24
Finished Apr 25 01:17:47 PM PDT 24
Peak memory 210956 kb
Host smart-d79c2c22-2168-4c27-832c-0b48a6d010ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094630321 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1094630321
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.4175281417
Short name T58
Test name
Test status
Simulation time 4446969472 ps
CPU time 11.78 seconds
Started Apr 25 01:12:54 PM PDT 24
Finished Apr 25 01:13:07 PM PDT 24
Peak memory 217852 kb
Host smart-ed78811b-5ee5-4191-889e-e51d89948607
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175281417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4175281417
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1996526649
Short name T221
Test name
Test status
Simulation time 336305106886 ps
CPU time 481.66 seconds
Started Apr 25 01:22:05 PM PDT 24
Finished Apr 25 01:30:08 PM PDT 24
Peak memory 211088 kb
Host smart-bfd0e560-c097-4e41-b367-b519794703a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996526649 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1996526649
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3069778737
Short name T189
Test name
Test status
Simulation time 595755615749 ps
CPU time 487.99 seconds
Started Apr 25 01:13:33 PM PDT 24
Finished Apr 25 01:21:42 PM PDT 24
Peak memory 202368 kb
Host smart-c16ca417-9b03-49ea-be77-e16a54b542a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069778737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3069778737
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2696865708
Short name T64
Test name
Test status
Simulation time 466944407 ps
CPU time 2.71 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:46 PM PDT 24
Peak memory 201376 kb
Host smart-ec79408b-283e-42bf-b0f3-ab840f7d0d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696865708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2696865708
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2157118025
Short name T5
Test name
Test status
Simulation time 328403823327 ps
CPU time 397.81 seconds
Started Apr 25 01:18:52 PM PDT 24
Finished Apr 25 01:25:31 PM PDT 24
Peak memory 202296 kb
Host smart-d9daeed5-440b-4bb4-bfee-c1ccea689a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157118025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2157118025
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2214671255
Short name T115
Test name
Test status
Simulation time 493395758405 ps
CPU time 1116.97 seconds
Started Apr 25 01:14:04 PM PDT 24
Finished Apr 25 01:32:42 PM PDT 24
Peak memory 202308 kb
Host smart-e3e9b6ef-f0eb-4cbb-9e8c-e9adcc41bbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214671255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2214671255
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3512847283
Short name T52
Test name
Test status
Simulation time 22138001104 ps
CPU time 23.04 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:48:13 PM PDT 24
Peak memory 201380 kb
Host smart-839511e5-733f-4b07-9ed7-a678f1034d75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512847283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3512847283
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3666492599
Short name T78
Test name
Test status
Simulation time 492130266164 ps
CPU time 1166.91 seconds
Started Apr 25 01:16:55 PM PDT 24
Finished Apr 25 01:36:22 PM PDT 24
Peak memory 202332 kb
Host smart-c52dbb2a-d692-4746-951b-8d62cbb8cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666492599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3666492599
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3684857507
Short name T173
Test name
Test status
Simulation time 335343458613 ps
CPU time 400.46 seconds
Started Apr 25 01:20:24 PM PDT 24
Finished Apr 25 01:27:08 PM PDT 24
Peak memory 202268 kb
Host smart-92011600-aadf-43b9-ab19-89c61ffd42f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684857507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3684857507
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2373532819
Short name T146
Test name
Test status
Simulation time 524844217624 ps
CPU time 71.97 seconds
Started Apr 25 01:18:01 PM PDT 24
Finished Apr 25 01:19:13 PM PDT 24
Peak memory 202312 kb
Host smart-326661c5-1b51-40f6-a029-bd4ef74910e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373532819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2373532819
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.583470590
Short name T89
Test name
Test status
Simulation time 378280168635 ps
CPU time 416.27 seconds
Started Apr 25 01:16:04 PM PDT 24
Finished Apr 25 01:23:01 PM PDT 24
Peak memory 202316 kb
Host smart-c972cc15-cdbb-4e1c-a6d8-efd753ea0f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583470590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.583470590
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.215127311
Short name T7
Test name
Test status
Simulation time 173865794591 ps
CPU time 76.18 seconds
Started Apr 25 01:14:54 PM PDT 24
Finished Apr 25 01:16:10 PM PDT 24
Peak memory 202288 kb
Host smart-56f04e70-8eb0-42b8-8f4d-9e6e503000ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=215127311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.215127311
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.517564599
Short name T165
Test name
Test status
Simulation time 546023373647 ps
CPU time 259.13 seconds
Started Apr 25 01:16:58 PM PDT 24
Finished Apr 25 01:21:18 PM PDT 24
Peak memory 202260 kb
Host smart-67773ed7-a321-4db7-9faf-13c0a395b9b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517564599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.517564599
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2379046804
Short name T163
Test name
Test status
Simulation time 482076062957 ps
CPU time 166.08 seconds
Started Apr 25 01:14:51 PM PDT 24
Finished Apr 25 01:17:38 PM PDT 24
Peak memory 202384 kb
Host smart-a741a5e0-1f6b-4add-8f89-98aa15893a93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379046804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2379046804
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.706531622
Short name T131
Test name
Test status
Simulation time 501476018630 ps
CPU time 264.88 seconds
Started Apr 25 01:13:18 PM PDT 24
Finished Apr 25 01:17:44 PM PDT 24
Peak memory 202384 kb
Host smart-d6fa534f-8a25-47b0-ac97-bcf1df7c2f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706531622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.706531622
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3866642841
Short name T222
Test name
Test status
Simulation time 384626549064 ps
CPU time 225.89 seconds
Started Apr 25 01:19:54 PM PDT 24
Finished Apr 25 01:23:40 PM PDT 24
Peak memory 202320 kb
Host smart-6d0ec62a-d509-420c-bd33-b2e31044a308
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866642841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3866642841
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.514923807
Short name T253
Test name
Test status
Simulation time 930095884548 ps
CPU time 643.74 seconds
Started Apr 25 01:16:46 PM PDT 24
Finished Apr 25 01:27:30 PM PDT 24
Peak memory 218108 kb
Host smart-55436c29-09ac-40dd-9107-c9878ee4a44d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514923807 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.514923807
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4183993661
Short name T54
Test name
Test status
Simulation time 8241955432 ps
CPU time 5.18 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201484 kb
Host smart-2ed9a780-ed44-410e-9cd0-6f5aac8c9386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183993661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.4183993661
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.772829622
Short name T256
Test name
Test status
Simulation time 609585924074 ps
CPU time 641.01 seconds
Started Apr 25 01:18:17 PM PDT 24
Finished Apr 25 01:28:58 PM PDT 24
Peak memory 202384 kb
Host smart-bc644003-8b71-4e3d-89dc-e8b041194c2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772829622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.772829622
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.871150010
Short name T187
Test name
Test status
Simulation time 494684597373 ps
CPU time 323.69 seconds
Started Apr 25 01:20:01 PM PDT 24
Finished Apr 25 01:25:26 PM PDT 24
Peak memory 202244 kb
Host smart-ec8fe233-c709-4378-b038-f71dd3da148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871150010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.871150010
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2701288143
Short name T260
Test name
Test status
Simulation time 509616861518 ps
CPU time 1120.32 seconds
Started Apr 25 01:12:53 PM PDT 24
Finished Apr 25 01:31:34 PM PDT 24
Peak memory 202308 kb
Host smart-0a17c2ae-a033-4fd4-a376-a51df601a660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701288143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2701288143
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1646884117
Short name T69
Test name
Test status
Simulation time 534022603 ps
CPU time 0.91 seconds
Started Apr 25 01:14:10 PM PDT 24
Finished Apr 25 01:14:12 PM PDT 24
Peak memory 201944 kb
Host smart-96fc9a45-61b6-4f43-9a22-0443141403e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646884117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1646884117
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1151529737
Short name T53
Test name
Test status
Simulation time 347981407721 ps
CPU time 819.13 seconds
Started Apr 25 01:21:03 PM PDT 24
Finished Apr 25 01:34:43 PM PDT 24
Peak memory 202268 kb
Host smart-77a44a8d-71be-4802-8069-521449be3e0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151529737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1151529737
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4282088139
Short name T211
Test name
Test status
Simulation time 342373787702 ps
CPU time 205.37 seconds
Started Apr 25 01:22:02 PM PDT 24
Finished Apr 25 01:25:30 PM PDT 24
Peak memory 202260 kb
Host smart-725bac7f-7414-415a-8770-e621c41ebbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282088139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4282088139
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1303299363
Short name T123
Test name
Test status
Simulation time 356000983889 ps
CPU time 161.11 seconds
Started Apr 25 01:16:06 PM PDT 24
Finished Apr 25 01:18:47 PM PDT 24
Peak memory 202248 kb
Host smart-376fbba2-da8c-4d82-a623-877d17625e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303299363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1303299363
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.328720294
Short name T277
Test name
Test status
Simulation time 333244201310 ps
CPU time 198.33 seconds
Started Apr 25 01:21:45 PM PDT 24
Finished Apr 25 01:25:04 PM PDT 24
Peak memory 202308 kb
Host smart-a609b354-fd4e-4d73-b666-a63710578a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328720294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.328720294
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3608688043
Short name T316
Test name
Test status
Simulation time 176143796027 ps
CPU time 202.23 seconds
Started Apr 25 01:16:30 PM PDT 24
Finished Apr 25 01:19:53 PM PDT 24
Peak memory 202368 kb
Host smart-b1ebfc94-b788-4fa5-a896-08aca78d7e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608688043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3608688043
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2644706880
Short name T220
Test name
Test status
Simulation time 322386894506 ps
CPU time 207.78 seconds
Started Apr 25 01:17:11 PM PDT 24
Finished Apr 25 01:20:40 PM PDT 24
Peak memory 202400 kb
Host smart-5dccd2a9-957b-4912-8dfb-60163edad8cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644706880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2644706880
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.405785641
Short name T275
Test name
Test status
Simulation time 490411526311 ps
CPU time 1115.71 seconds
Started Apr 25 01:14:40 PM PDT 24
Finished Apr 25 01:33:17 PM PDT 24
Peak memory 202292 kb
Host smart-8e58b396-1319-4dbf-880a-6d5b4a917934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405785641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
405785641
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2121341444
Short name T248
Test name
Test status
Simulation time 503181725729 ps
CPU time 671.49 seconds
Started Apr 25 01:16:40 PM PDT 24
Finished Apr 25 01:27:52 PM PDT 24
Peak memory 202320 kb
Host smart-a38ee685-a301-4e15-b51f-70d9c6c1e432
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121341444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2121341444
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3971935921
Short name T243
Test name
Test status
Simulation time 502658533294 ps
CPU time 121.61 seconds
Started Apr 25 01:17:34 PM PDT 24
Finished Apr 25 01:19:36 PM PDT 24
Peak memory 202280 kb
Host smart-0961d869-3db0-4476-82bc-32bca55b2e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971935921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3971935921
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1035194669
Short name T111
Test name
Test status
Simulation time 4658488956 ps
CPU time 6.52 seconds
Started Apr 25 12:47:46 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201464 kb
Host smart-69deb169-760f-4d91-8dc9-af697dc818cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035194669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1035194669
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3056039029
Short name T263
Test name
Test status
Simulation time 380524429071 ps
CPU time 344.26 seconds
Started Apr 25 01:14:10 PM PDT 24
Finished Apr 25 01:19:55 PM PDT 24
Peak memory 202264 kb
Host smart-de622251-4b0c-48a3-8c43-bcd0f08a5827
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056039029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3056039029
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.472740199
Short name T186
Test name
Test status
Simulation time 344929373054 ps
CPU time 101.7 seconds
Started Apr 25 01:20:04 PM PDT 24
Finished Apr 25 01:21:46 PM PDT 24
Peak memory 202292 kb
Host smart-0a49fe05-51bb-496c-82b1-b2f7e25b32fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472740199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.472740199
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1008974805
Short name T250
Test name
Test status
Simulation time 492475819946 ps
CPU time 1205.69 seconds
Started Apr 25 01:18:34 PM PDT 24
Finished Apr 25 01:38:41 PM PDT 24
Peak memory 202304 kb
Host smart-e5103c5a-9a2d-41c6-93a0-1890c430a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008974805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1008974805
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3864321900
Short name T22
Test name
Test status
Simulation time 334911676476 ps
CPU time 407.26 seconds
Started Apr 25 01:20:13 PM PDT 24
Finished Apr 25 01:27:02 PM PDT 24
Peak memory 202304 kb
Host smart-7c3cd1c6-5e07-4be9-a507-a36ba79870f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864321900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3864321900
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4238573823
Short name T183
Test name
Test status
Simulation time 322029538489 ps
CPU time 52.36 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:13:39 PM PDT 24
Peak memory 202372 kb
Host smart-bf785ab8-c203-4ab7-8672-3618501ac90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238573823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4238573823
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.640305367
Short name T90
Test name
Test status
Simulation time 547218973339 ps
CPU time 142.21 seconds
Started Apr 25 01:13:51 PM PDT 24
Finished Apr 25 01:16:13 PM PDT 24
Peak memory 202264 kb
Host smart-104160f0-3211-44f3-9828-64424b54bd2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640305367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.640305367
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2932539896
Short name T252
Test name
Test status
Simulation time 720337231227 ps
CPU time 1878.68 seconds
Started Apr 25 01:14:26 PM PDT 24
Finished Apr 25 01:45:45 PM PDT 24
Peak memory 202656 kb
Host smart-de94c4cb-bdd6-4868-bcbb-ba84493ff518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932539896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2932539896
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2351074523
Short name T259
Test name
Test status
Simulation time 53972295294 ps
CPU time 167.72 seconds
Started Apr 25 01:14:34 PM PDT 24
Finished Apr 25 01:17:22 PM PDT 24
Peak memory 211080 kb
Host smart-0e7c062b-f255-44f8-ba98-64e0ff6387aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351074523 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2351074523
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.203969653
Short name T312
Test name
Test status
Simulation time 360643537945 ps
CPU time 776.14 seconds
Started Apr 25 01:17:33 PM PDT 24
Finished Apr 25 01:30:29 PM PDT 24
Peak memory 202388 kb
Host smart-40ffbd5e-12bc-4238-baff-6c7ba030a991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203969653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.203969653
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.203336589
Short name T205
Test name
Test status
Simulation time 574422727284 ps
CPU time 321.98 seconds
Started Apr 25 01:20:38 PM PDT 24
Finished Apr 25 01:26:06 PM PDT 24
Peak memory 202348 kb
Host smart-4143e470-1d90-44f7-b622-11e7fbfa5cc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203336589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.203336589
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2988267683
Short name T282
Test name
Test status
Simulation time 82011521432 ps
CPU time 60.44 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:14:21 PM PDT 24
Peak memory 211072 kb
Host smart-d52167a2-261f-4537-be64-b3e0dc83b056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988267683 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2988267683
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.499416480
Short name T196
Test name
Test status
Simulation time 73649081969 ps
CPU time 226.64 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:16:33 PM PDT 24
Peak memory 202744 kb
Host smart-68fcfc68-9776-4adb-a982-4768f5ce4427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499416480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.499416480
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3458793199
Short name T197
Test name
Test status
Simulation time 143283690649 ps
CPU time 745.1 seconds
Started Apr 25 01:13:33 PM PDT 24
Finished Apr 25 01:25:58 PM PDT 24
Peak memory 202584 kb
Host smart-319cfe1d-4467-442f-bf26-473b509d9682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458793199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3458793199
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3134994461
Short name T219
Test name
Test status
Simulation time 535162499949 ps
CPU time 1207.97 seconds
Started Apr 25 01:14:59 PM PDT 24
Finished Apr 25 01:35:07 PM PDT 24
Peak memory 202244 kb
Host smart-7936f983-3f84-4e00-9c5b-45d9bac53d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134994461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3134994461
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3933825686
Short name T236
Test name
Test status
Simulation time 487531521671 ps
CPU time 388.99 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:19:33 PM PDT 24
Peak memory 202316 kb
Host smart-0c120a08-befc-44e9-955d-63d30efed465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933825686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3933825686
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1329481507
Short name T278
Test name
Test status
Simulation time 171383774200 ps
CPU time 36.4 seconds
Started Apr 25 01:20:24 PM PDT 24
Finished Apr 25 01:21:03 PM PDT 24
Peak memory 202232 kb
Host smart-3ad486c1-d1c0-4784-9745-a59616a06b7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329481507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1329481507
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1908512563
Short name T304
Test name
Test status
Simulation time 167426310980 ps
CPU time 141.26 seconds
Started Apr 25 01:21:16 PM PDT 24
Finished Apr 25 01:23:38 PM PDT 24
Peak memory 202284 kb
Host smart-28e79929-3a6e-4703-97ef-738f05809b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908512563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1908512563
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.989404428
Short name T279
Test name
Test status
Simulation time 498185659333 ps
CPU time 1184.27 seconds
Started Apr 25 01:21:34 PM PDT 24
Finished Apr 25 01:41:19 PM PDT 24
Peak memory 202288 kb
Host smart-7cb2e72c-7362-4a02-9a09-f407cb8e94fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989404428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.989404428
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3066993756
Short name T14
Test name
Test status
Simulation time 58969593166 ps
CPU time 176.05 seconds
Started Apr 25 01:12:44 PM PDT 24
Finished Apr 25 01:15:41 PM PDT 24
Peak memory 211008 kb
Host smart-fc63091e-7a5f-408f-beeb-a402ffd69205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066993756 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3066993756
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4176986275
Short name T288
Test name
Test status
Simulation time 485655689018 ps
CPU time 1059.18 seconds
Started Apr 25 01:12:48 PM PDT 24
Finished Apr 25 01:30:28 PM PDT 24
Peak memory 202408 kb
Host smart-2ee60c2e-1619-4000-a507-a7c3464f2a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176986275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4176986275
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3152746804
Short name T199
Test name
Test status
Simulation time 126627818188 ps
CPU time 593.3 seconds
Started Apr 25 01:13:53 PM PDT 24
Finished Apr 25 01:23:48 PM PDT 24
Peak memory 210888 kb
Host smart-26001ac6-a99d-4098-8c4c-72f74ce96d4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152746804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3152746804
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3590657506
Short name T149
Test name
Test status
Simulation time 495521122277 ps
CPU time 754.76 seconds
Started Apr 25 01:15:52 PM PDT 24
Finished Apr 25 01:28:28 PM PDT 24
Peak memory 202284 kb
Host smart-5c63d804-9cb8-4bbd-aeaa-b68b6daf2339
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590657506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3590657506
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2634383948
Short name T232
Test name
Test status
Simulation time 488537585328 ps
CPU time 1171.39 seconds
Started Apr 25 01:16:18 PM PDT 24
Finished Apr 25 01:35:50 PM PDT 24
Peak memory 202332 kb
Host smart-5d1eaae9-34eb-4b75-b5ec-f71e510dfc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634383948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2634383948
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.4151133695
Short name T32
Test name
Test status
Simulation time 485445493352 ps
CPU time 548.52 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:22:08 PM PDT 24
Peak memory 202380 kb
Host smart-350ed213-382f-4a6e-b9ed-a503e9af97cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151133695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
4151133695
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2357143887
Short name T273
Test name
Test status
Simulation time 358276190639 ps
CPU time 859.65 seconds
Started Apr 25 01:18:30 PM PDT 24
Finished Apr 25 01:32:51 PM PDT 24
Peak memory 202244 kb
Host smart-59114281-304f-4d52-a80f-c9ddcddc2e4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357143887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2357143887
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2922413774
Short name T161
Test name
Test status
Simulation time 523684552970 ps
CPU time 316.53 seconds
Started Apr 25 01:21:02 PM PDT 24
Finished Apr 25 01:26:20 PM PDT 24
Peak memory 202240 kb
Host smart-e20315ca-2b97-47d2-ab9e-0311acce1654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922413774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2922413774
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.533891285
Short name T314
Test name
Test status
Simulation time 444545417795 ps
CPU time 415.95 seconds
Started Apr 25 01:13:08 PM PDT 24
Finished Apr 25 01:20:04 PM PDT 24
Peak memory 218608 kb
Host smart-8af204a5-b2e7-4900-b476-25128cb82278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533891285 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.533891285
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3356175348
Short name T330
Test name
Test status
Simulation time 248295671333 ps
CPU time 165.24 seconds
Started Apr 25 01:13:31 PM PDT 24
Finished Apr 25 01:16:17 PM PDT 24
Peak memory 211244 kb
Host smart-7dafbafe-9925-44f8-9ca3-cc87357c51dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356175348 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3356175348
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.4188653752
Short name T551
Test name
Test status
Simulation time 334513870174 ps
CPU time 201.24 seconds
Started Apr 25 01:13:38 PM PDT 24
Finished Apr 25 01:17:00 PM PDT 24
Peak memory 202252 kb
Host smart-4849b1b1-b3fd-4a95-8068-2663656d759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188653752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.4188653752
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3738295812
Short name T339
Test name
Test status
Simulation time 20183117889 ps
CPU time 59.69 seconds
Started Apr 25 01:14:10 PM PDT 24
Finished Apr 25 01:15:10 PM PDT 24
Peak memory 210896 kb
Host smart-2b7b0211-2ffe-4a03-81b8-46c235280397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738295812 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3738295812
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2796319962
Short name T127
Test name
Test status
Simulation time 515307225340 ps
CPU time 203.72 seconds
Started Apr 25 01:17:27 PM PDT 24
Finished Apr 25 01:20:51 PM PDT 24
Peak memory 202384 kb
Host smart-95d1fc04-28b2-42de-ba9e-c27bdcf91284
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796319962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2796319962
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4234179114
Short name T262
Test name
Test status
Simulation time 311895280294 ps
CPU time 199.77 seconds
Started Apr 25 01:19:22 PM PDT 24
Finished Apr 25 01:22:45 PM PDT 24
Peak memory 210952 kb
Host smart-447a6c77-46aa-4335-8647-114209237146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234179114 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4234179114
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2448011496
Short name T285
Test name
Test status
Simulation time 523376947010 ps
CPU time 270.6 seconds
Started Apr 25 01:20:31 PM PDT 24
Finished Apr 25 01:25:03 PM PDT 24
Peak memory 202388 kb
Host smart-67cc4d59-65dc-42f0-a097-5e1e5b3a127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448011496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2448011496
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3909532820
Short name T105
Test name
Test status
Simulation time 1148627930 ps
CPU time 2.85 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:49 PM PDT 24
Peak memory 201340 kb
Host smart-d0217c5d-d7f3-43f1-88ff-6b2fb349a53d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909532820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3909532820
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.409067807
Short name T99
Test name
Test status
Simulation time 14944979001 ps
CPU time 15.17 seconds
Started Apr 25 12:47:35 PM PDT 24
Finished Apr 25 12:47:53 PM PDT 24
Peak memory 201452 kb
Host smart-a10bebb7-cc9a-4a2d-b4ce-f4473ba5ecc8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409067807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.409067807
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2686642428
Short name T859
Test name
Test status
Simulation time 1125700241 ps
CPU time 2.45 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201160 kb
Host smart-506cfbed-0927-49cb-831c-7d0dac69c359
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686642428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2686642428
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3361804307
Short name T820
Test name
Test status
Simulation time 991836398 ps
CPU time 1.08 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:51 PM PDT 24
Peak memory 201184 kb
Host smart-7bdb908f-fe76-4b0a-9b0b-08d8c6bd4429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361804307 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3361804307
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2136342904
Short name T884
Test name
Test status
Simulation time 366798312 ps
CPU time 1.17 seconds
Started Apr 25 12:47:35 PM PDT 24
Finished Apr 25 12:47:38 PM PDT 24
Peak memory 201140 kb
Host smart-e6daed7f-1ac2-49c8-ba7f-2315b7a9a446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136342904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2136342904
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1651288296
Short name T853
Test name
Test status
Simulation time 451251713 ps
CPU time 1.67 seconds
Started Apr 25 12:47:43 PM PDT 24
Finished Apr 25 12:47:46 PM PDT 24
Peak memory 201220 kb
Host smart-233fe4f9-032f-4110-9ffd-7ec90a5cf440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651288296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1651288296
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3310158606
Short name T881
Test name
Test status
Simulation time 5084280388 ps
CPU time 6.27 seconds
Started Apr 25 12:47:35 PM PDT 24
Finished Apr 25 12:47:43 PM PDT 24
Peak memory 201384 kb
Host smart-9812bb7b-2938-4509-a6ec-ced690c929eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310158606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3310158606
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3668685930
Short name T823
Test name
Test status
Simulation time 371554752 ps
CPU time 1.64 seconds
Started Apr 25 12:47:34 PM PDT 24
Finished Apr 25 12:47:37 PM PDT 24
Peak memory 201380 kb
Host smart-a826d6b0-20b9-4896-85e5-96f01966a696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668685930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3668685930
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.443145240
Short name T877
Test name
Test status
Simulation time 8231261686 ps
CPU time 19.51 seconds
Started Apr 25 12:47:32 PM PDT 24
Finished Apr 25 12:47:53 PM PDT 24
Peak memory 201472 kb
Host smart-065e4d7a-0eb9-47ec-8455-4e85a754013c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443145240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.443145240
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3040521720
Short name T895
Test name
Test status
Simulation time 831895790 ps
CPU time 2.76 seconds
Started Apr 25 12:47:58 PM PDT 24
Finished Apr 25 12:48:02 PM PDT 24
Peak memory 201436 kb
Host smart-bb2dad73-5f64-41fc-927c-cf326be87814
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040521720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3040521720
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3897613046
Short name T50
Test name
Test status
Simulation time 27107755565 ps
CPU time 91.68 seconds
Started Apr 25 12:47:41 PM PDT 24
Finished Apr 25 12:49:14 PM PDT 24
Peak memory 201448 kb
Host smart-1378bfdf-d39e-4c86-abfe-04748d70131d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897613046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3897613046
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3574349143
Short name T810
Test name
Test status
Simulation time 1484132529 ps
CPU time 4.4 seconds
Started Apr 25 12:47:41 PM PDT 24
Finished Apr 25 12:47:47 PM PDT 24
Peak memory 201212 kb
Host smart-7181d6e6-23a8-47fe-ac6e-9b4e906e5d78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574349143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3574349143
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2674943534
Short name T872
Test name
Test status
Simulation time 592476185 ps
CPU time 1.49 seconds
Started Apr 25 12:47:45 PM PDT 24
Finished Apr 25 12:47:49 PM PDT 24
Peak memory 211192 kb
Host smart-576edd60-7496-4135-9ae5-c4f58b581cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674943534 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2674943534
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3592936234
Short name T822
Test name
Test status
Simulation time 340571986 ps
CPU time 1.5 seconds
Started Apr 25 12:47:35 PM PDT 24
Finished Apr 25 12:47:38 PM PDT 24
Peak memory 201128 kb
Host smart-189c76c2-091e-465c-8218-e39c15ade72c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592936234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3592936234
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2028430679
Short name T865
Test name
Test status
Simulation time 478399723 ps
CPU time 1.23 seconds
Started Apr 25 12:47:41 PM PDT 24
Finished Apr 25 12:47:44 PM PDT 24
Peak memory 201164 kb
Host smart-713ee757-0032-4b12-b3d2-a5ea47a2f5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028430679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2028430679
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2810048375
Short name T821
Test name
Test status
Simulation time 2553430814 ps
CPU time 2.55 seconds
Started Apr 25 12:47:57 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201476 kb
Host smart-a1546897-bc5e-4d6b-b22e-7778a60b0bda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810048375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2810048375
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.958027418
Short name T862
Test name
Test status
Simulation time 497848136 ps
CPU time 2.82 seconds
Started Apr 25 12:47:46 PM PDT 24
Finished Apr 25 12:47:51 PM PDT 24
Peak memory 217356 kb
Host smart-987147b2-67f4-40ec-b57a-7212f306690b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958027418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.958027418
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3811304658
Short name T850
Test name
Test status
Simulation time 5068371614 ps
CPU time 2.75 seconds
Started Apr 25 12:47:35 PM PDT 24
Finished Apr 25 12:47:40 PM PDT 24
Peak memory 201500 kb
Host smart-219443b2-5875-4bed-8ae4-8901b193c705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811304658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3811304658
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1558943692
Short name T869
Test name
Test status
Simulation time 558103916 ps
CPU time 2.09 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201304 kb
Host smart-64a80f6a-d0e1-4762-9ff8-f760c2a1466d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558943692 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1558943692
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2089512758
Short name T911
Test name
Test status
Simulation time 447712475 ps
CPU time 1.88 seconds
Started Apr 25 12:47:41 PM PDT 24
Finished Apr 25 12:47:44 PM PDT 24
Peak memory 201208 kb
Host smart-df379fe1-c139-4af9-aea9-0ca067ab79bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089512758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2089512758
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3192083461
Short name T805
Test name
Test status
Simulation time 391717506 ps
CPU time 1.49 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:41 PM PDT 24
Peak memory 201200 kb
Host smart-c8a47c21-2707-4b64-bc74-df5a5545e4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192083461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3192083461
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.723674780
Short name T904
Test name
Test status
Simulation time 2363329109 ps
CPU time 5.47 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201284 kb
Host smart-0a31b815-c9d6-451e-b571-cb820f16b72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723674780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.723674780
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3408596576
Short name T65
Test name
Test status
Simulation time 761739952 ps
CPU time 2.57 seconds
Started Apr 25 12:47:55 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 217436 kb
Host smart-4271cb62-4d74-4ce5-8e86-8d6f3c9a3b36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408596576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3408596576
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3109927727
Short name T337
Test name
Test status
Simulation time 4394024889 ps
CPU time 4.28 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:47 PM PDT 24
Peak memory 201476 kb
Host smart-196e9641-f1db-4bd5-9f28-99323363e4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109927727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3109927727
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.385691799
Short name T852
Test name
Test status
Simulation time 642753291 ps
CPU time 1.22 seconds
Started Apr 25 12:47:41 PM PDT 24
Finished Apr 25 12:47:43 PM PDT 24
Peak memory 201316 kb
Host smart-09615c7a-a5d5-4df1-926d-de19403f07ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385691799 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.385691799
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3792657763
Short name T102
Test name
Test status
Simulation time 537448101 ps
CPU time 1.9 seconds
Started Apr 25 12:47:57 PM PDT 24
Finished Apr 25 12:48:00 PM PDT 24
Peak memory 201084 kb
Host smart-b9dad1a8-866b-4fb5-90c8-cbc9ccd0f9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792657763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3792657763
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2659444317
Short name T795
Test name
Test status
Simulation time 477955338 ps
CPU time 1.7 seconds
Started Apr 25 12:47:56 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201192 kb
Host smart-2af06547-df33-452a-bbc6-306528f8061c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659444317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2659444317
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.17926169
Short name T831
Test name
Test status
Simulation time 4979028814 ps
CPU time 5.27 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:51 PM PDT 24
Peak memory 201520 kb
Host smart-497bc25f-3ef8-4204-9fef-6dedf5897a25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17926169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ct
rl_same_csr_outstanding.17926169
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3444055424
Short name T870
Test name
Test status
Simulation time 968203899 ps
CPU time 2.21 seconds
Started Apr 25 12:47:36 PM PDT 24
Finished Apr 25 12:47:41 PM PDT 24
Peak memory 201536 kb
Host smart-7493713a-74a7-47cb-8a5e-5c8f04b5f7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444055424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3444055424
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.630782021
Short name T829
Test name
Test status
Simulation time 575056587 ps
CPU time 1.22 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:09 PM PDT 24
Peak memory 201292 kb
Host smart-5d448503-41c9-400c-b6e8-95a83f0a3271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630782021 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.630782021
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.885696150
Short name T875
Test name
Test status
Simulation time 542276612 ps
CPU time 1.43 seconds
Started Apr 25 12:47:45 PM PDT 24
Finished Apr 25 12:47:49 PM PDT 24
Peak memory 200816 kb
Host smart-b5bc2e24-5024-4253-8504-037f96356430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885696150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.885696150
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2721587403
Short name T818
Test name
Test status
Simulation time 387074451 ps
CPU time 1.56 seconds
Started Apr 25 12:47:57 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201228 kb
Host smart-76b76b2c-e030-4969-a449-30350c46007d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721587403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2721587403
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.468768883
Short name T864
Test name
Test status
Simulation time 2308144998 ps
CPU time 8.77 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201256 kb
Host smart-66f4f117-bf9c-4ab6-a828-394f5d088ea2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468768883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.468768883
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3930821539
Short name T62
Test name
Test status
Simulation time 541028382 ps
CPU time 3.67 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 209508 kb
Host smart-a429ae84-d486-486e-9730-d206b268ef2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930821539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3930821539
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3004189153
Short name T879
Test name
Test status
Simulation time 4645781850 ps
CPU time 4.17 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:57 PM PDT 24
Peak memory 201532 kb
Host smart-9f6651b2-dd17-493d-9319-e276d60d5718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004189153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3004189153
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3956116601
Short name T813
Test name
Test status
Simulation time 354292902 ps
CPU time 1.64 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201180 kb
Host smart-7227adeb-da7e-4117-a150-8cefb16db3b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956116601 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3956116601
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.189184754
Short name T97
Test name
Test status
Simulation time 393380956 ps
CPU time 0.98 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:48 PM PDT 24
Peak memory 201120 kb
Host smart-e8dcb01c-4bac-4613-bb24-beccaa98d66d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189184754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.189184754
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.460219869
Short name T808
Test name
Test status
Simulation time 341235824 ps
CPU time 1.38 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201244 kb
Host smart-0bbe3656-c514-4e88-b829-e5cd5de23973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460219869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.460219869
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2632093446
Short name T861
Test name
Test status
Simulation time 4070326539 ps
CPU time 10.6 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:48:02 PM PDT 24
Peak memory 201552 kb
Host smart-f6c1bae0-cc47-4a7f-b57b-9e5b8be2f241
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632093446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2632093446
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.313665138
Short name T892
Test name
Test status
Simulation time 374644964 ps
CPU time 1.69 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201412 kb
Host smart-60f8958d-9e0d-4ff1-bb20-df037925d13b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313665138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.313665138
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1486019095
Short name T56
Test name
Test status
Simulation time 4367620526 ps
CPU time 12.52 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 201500 kb
Host smart-2ccb1942-7896-4559-9ee7-607513a6c5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486019095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1486019095
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3513782638
Short name T915
Test name
Test status
Simulation time 694937665 ps
CPU time 1.17 seconds
Started Apr 25 12:48:04 PM PDT 24
Finished Apr 25 12:48:06 PM PDT 24
Peak memory 201304 kb
Host smart-8a5e1f6f-c2a0-4a96-a451-9e17886699f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513782638 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3513782638
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2141856168
Short name T854
Test name
Test status
Simulation time 550769855 ps
CPU time 0.89 seconds
Started Apr 25 12:48:01 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 201128 kb
Host smart-df2a5343-7462-4195-94e1-21957c86e3bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141856168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2141856168
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3094577222
Short name T860
Test name
Test status
Simulation time 498531112 ps
CPU time 0.91 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:46 PM PDT 24
Peak memory 201160 kb
Host smart-0720df48-bb8e-4d12-8d97-1a706df65e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094577222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3094577222
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2805412016
Short name T828
Test name
Test status
Simulation time 3541522398 ps
CPU time 7.41 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:53 PM PDT 24
Peak memory 201424 kb
Host smart-d9ced226-1212-44a3-974d-cb4a1f4d4f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805412016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2805412016
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1061508520
Short name T866
Test name
Test status
Simulation time 517988209 ps
CPU time 1.09 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201228 kb
Host smart-3e6675d2-0f3b-41c9-a9a8-b84af80fbe0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061508520 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1061508520
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3810867411
Short name T95
Test name
Test status
Simulation time 556502587 ps
CPU time 1.11 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201108 kb
Host smart-42da1512-a309-4c69-b5de-65dcca0e18f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810867411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3810867411
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.117950176
Short name T898
Test name
Test status
Simulation time 393752784 ps
CPU time 1.54 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201216 kb
Host smart-cfd428b1-93cc-4b32-bb05-d84f8e547d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117950176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.117950176
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2501586146
Short name T112
Test name
Test status
Simulation time 5215338610 ps
CPU time 5.99 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:48:00 PM PDT 24
Peak memory 201368 kb
Host smart-03722bc6-1608-44a1-be2e-b48a27f06efa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501586146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2501586146
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.944630263
Short name T880
Test name
Test status
Simulation time 3372574802 ps
CPU time 2.99 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 211276 kb
Host smart-0cf4479c-ad34-486e-b736-f4a51c296436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944630263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.944630263
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3576737918
Short name T55
Test name
Test status
Simulation time 7827465810 ps
CPU time 11.96 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:48:05 PM PDT 24
Peak memory 201484 kb
Host smart-8fb89914-72d4-43b8-a3e6-ea00a0a58025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576737918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3576737918
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.999514368
Short name T897
Test name
Test status
Simulation time 671308726 ps
CPU time 1.19 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201192 kb
Host smart-eea7c21f-8bc7-4b99-935e-17072d0c19f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999514368 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.999514368
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1515718827
Short name T894
Test name
Test status
Simulation time 438517573 ps
CPU time 1.84 seconds
Started Apr 25 12:47:55 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201196 kb
Host smart-19bf8e8b-3b42-4022-a163-5a235afb1ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515718827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1515718827
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4200909272
Short name T846
Test name
Test status
Simulation time 356975188 ps
CPU time 0.87 seconds
Started Apr 25 12:48:14 PM PDT 24
Finished Apr 25 12:48:17 PM PDT 24
Peak memory 201148 kb
Host smart-7052e12d-54d2-4b76-9910-ce2f0f75c03c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200909272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4200909272
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.846270745
Short name T888
Test name
Test status
Simulation time 4924532076 ps
CPU time 17.49 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:48:11 PM PDT 24
Peak memory 201428 kb
Host smart-2b96f293-20ce-4dc3-ac79-119d3ce23155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846270745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.846270745
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2554662551
Short name T816
Test name
Test status
Simulation time 946417818 ps
CPU time 2.77 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 210728 kb
Host smart-2d2a84d9-026c-4416-9028-d2442cb0d1ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554662551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2554662551
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3284601012
Short name T891
Test name
Test status
Simulation time 4318135029 ps
CPU time 3.12 seconds
Started Apr 25 12:47:52 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 201492 kb
Host smart-b5cee886-1d16-4f3f-8dcf-b56dd53104f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284601012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3284601012
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2326216626
Short name T833
Test name
Test status
Simulation time 672432549 ps
CPU time 0.95 seconds
Started Apr 25 12:48:04 PM PDT 24
Finished Apr 25 12:48:06 PM PDT 24
Peak memory 201304 kb
Host smart-308d702c-01db-4044-80c7-75232428a2bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326216626 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2326216626
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2675900082
Short name T93
Test name
Test status
Simulation time 388942759 ps
CPU time 1.16 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:45 PM PDT 24
Peak memory 201132 kb
Host smart-6014152b-1b1b-4b69-800a-732f081e6fea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675900082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2675900082
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2309857652
Short name T907
Test name
Test status
Simulation time 507767336 ps
CPU time 1.97 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201208 kb
Host smart-4a6eda5d-0f3d-46d2-9996-e54aea7aa58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309857652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2309857652
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2941334159
Short name T889
Test name
Test status
Simulation time 1945269780 ps
CPU time 4.64 seconds
Started Apr 25 12:47:52 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201132 kb
Host smart-171d178c-95d6-4545-ace9-f64835a30833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941334159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2941334159
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1249224703
Short name T873
Test name
Test status
Simulation time 375222333 ps
CPU time 1.72 seconds
Started Apr 25 12:47:43 PM PDT 24
Finished Apr 25 12:47:47 PM PDT 24
Peak memory 201512 kb
Host smart-2dbdb65f-c67c-4953-b5c1-f1e2dd7bee1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249224703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1249224703
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.8764967
Short name T335
Test name
Test status
Simulation time 4226509622 ps
CPU time 6.46 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:48:00 PM PDT 24
Peak memory 201516 kb
Host smart-d3ad43cc-1cae-4433-bdfc-87c34c5cf653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8764967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg
_err.8764967
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3826906236
Short name T67
Test name
Test status
Simulation time 443950743 ps
CPU time 1.55 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201300 kb
Host smart-21fd44d9-ed91-4aea-a5bd-56ff2fb6d296
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826906236 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3826906236
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.174607129
Short name T113
Test name
Test status
Simulation time 438391022 ps
CPU time 1.61 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:45 PM PDT 24
Peak memory 201116 kb
Host smart-06f7be21-89af-4144-ac97-abacc537cf6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174607129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.174607129
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3804782567
Short name T819
Test name
Test status
Simulation time 519154017 ps
CPU time 1.85 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201208 kb
Host smart-b8a49043-6b17-4d0b-a656-1193fedd10a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804782567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3804782567
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3219045228
Short name T840
Test name
Test status
Simulation time 4300806192 ps
CPU time 3.63 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:47 PM PDT 24
Peak memory 201476 kb
Host smart-0d366e8a-13f7-41b7-a2a9-cc6bf7b73966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219045228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3219045228
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3379335945
Short name T834
Test name
Test status
Simulation time 515787507 ps
CPU time 2.98 seconds
Started Apr 25 12:47:54 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201532 kb
Host smart-311c28e3-aea1-4f01-9731-7055932fd535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379335945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3379335945
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1706207706
Short name T901
Test name
Test status
Simulation time 4740347360 ps
CPU time 6.58 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201404 kb
Host smart-814dd562-569c-492c-b401-3cba3e68a71c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706207706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1706207706
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3283390886
Short name T918
Test name
Test status
Simulation time 651741972 ps
CPU time 0.95 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:51 PM PDT 24
Peak memory 201268 kb
Host smart-602c53b5-49e0-4417-a080-2b70270c643c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283390886 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3283390886
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2493633927
Short name T110
Test name
Test status
Simulation time 611190743 ps
CPU time 1.18 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201248 kb
Host smart-8a4ca58b-a139-4d9c-a5c9-922d10f01301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493633927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2493633927
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3273383691
Short name T809
Test name
Test status
Simulation time 437103533 ps
CPU time 1.6 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:48 PM PDT 24
Peak memory 201144 kb
Host smart-e84d611a-a5f6-4dd1-a47a-f8a0e2e6263d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273383691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3273383691
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.317496872
Short name T108
Test name
Test status
Simulation time 2284234751 ps
CPU time 2.94 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:46 PM PDT 24
Peak memory 200560 kb
Host smart-c2dac647-2538-4f64-a07a-301deec1b367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317496872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.317496872
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3547633767
Short name T824
Test name
Test status
Simulation time 612334260 ps
CPU time 2.73 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 217424 kb
Host smart-a9f2df3b-06d1-4664-98d2-89a487599120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547633767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3547633767
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3518990204
Short name T886
Test name
Test status
Simulation time 7983747290 ps
CPU time 9.01 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201480 kb
Host smart-6a5bfd48-83cc-41ab-a4f9-154edf802830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518990204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3518990204
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4259074524
Short name T98
Test name
Test status
Simulation time 1183565669 ps
CPU time 2.93 seconds
Started Apr 25 12:47:37 PM PDT 24
Finished Apr 25 12:47:41 PM PDT 24
Peak memory 201344 kb
Host smart-21428c12-2254-4591-8d57-c0b539c2321d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259074524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4259074524
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2402000611
Short name T917
Test name
Test status
Simulation time 1285332075 ps
CPU time 1.32 seconds
Started Apr 25 12:47:40 PM PDT 24
Finished Apr 25 12:47:43 PM PDT 24
Peak memory 201252 kb
Host smart-7bd174b7-e1d2-41b3-b840-353a82aedf58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402000611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2402000611
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.384624271
Short name T838
Test name
Test status
Simulation time 552988540 ps
CPU time 2.09 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:45 PM PDT 24
Peak memory 201308 kb
Host smart-68a3f492-57ac-4251-a821-156923f0caf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384624271 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.384624271
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.992252812
Short name T96
Test name
Test status
Simulation time 478238181 ps
CPU time 1.3 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201228 kb
Host smart-09793e1b-86b1-44c2-be78-537dcf483469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992252812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.992252812
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3939724720
Short name T798
Test name
Test status
Simulation time 408545089 ps
CPU time 1.6 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201160 kb
Host smart-fc68ef6b-405d-42fc-8764-aa6ec32c5b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939724720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3939724720
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3206233321
Short name T51
Test name
Test status
Simulation time 2760316433 ps
CPU time 8.1 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:48 PM PDT 24
Peak memory 201268 kb
Host smart-6bc52af1-e70b-4d9d-b4fe-6a8f3d03449f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206233321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3206233321
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3135505349
Short name T855
Test name
Test status
Simulation time 517909337 ps
CPU time 2.31 seconds
Started Apr 25 12:47:42 PM PDT 24
Finished Apr 25 12:47:45 PM PDT 24
Peak memory 201264 kb
Host smart-77d789b8-19ad-4c95-9512-ff0c3197aa2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135505349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3135505349
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.515460448
Short name T913
Test name
Test status
Simulation time 4789897481 ps
CPU time 3.7 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201464 kb
Host smart-b8e17cfe-2fcc-426c-8bdb-58590b350296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515460448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.515460448
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1215931237
Short name T815
Test name
Test status
Simulation time 384609844 ps
CPU time 0.87 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:51 PM PDT 24
Peak memory 201156 kb
Host smart-a0f48477-f6d1-4cfd-ab7c-2e334c0885d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215931237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1215931237
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2586903617
Short name T857
Test name
Test status
Simulation time 482788363 ps
CPU time 0.93 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201192 kb
Host smart-c729c278-93fa-4e5b-963d-b990a83e5e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586903617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2586903617
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1269883102
Short name T851
Test name
Test status
Simulation time 498719092 ps
CPU time 1.75 seconds
Started Apr 25 12:47:57 PM PDT 24
Finished Apr 25 12:48:00 PM PDT 24
Peak memory 201196 kb
Host smart-c8f64ab0-45f4-4557-952b-cb8aa8601df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269883102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1269883102
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2495871062
Short name T883
Test name
Test status
Simulation time 359667872 ps
CPU time 1.5 seconds
Started Apr 25 12:47:43 PM PDT 24
Finished Apr 25 12:47:47 PM PDT 24
Peak memory 201200 kb
Host smart-36d7f722-354d-463b-94db-31fd074bb9f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495871062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2495871062
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1619671697
Short name T843
Test name
Test status
Simulation time 281127078 ps
CPU time 1.19 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201196 kb
Host smart-288e9646-ff79-443b-bcc2-2584589caeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619671697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1619671697
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4019991657
Short name T794
Test name
Test status
Simulation time 312730553 ps
CPU time 1.36 seconds
Started Apr 25 12:47:53 PM PDT 24
Finished Apr 25 12:47:57 PM PDT 24
Peak memory 201228 kb
Host smart-b98477b7-5fad-40cb-b140-1ec87b0a72dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019991657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4019991657
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.339368009
Short name T806
Test name
Test status
Simulation time 474951447 ps
CPU time 0.78 seconds
Started Apr 25 12:48:04 PM PDT 24
Finished Apr 25 12:48:06 PM PDT 24
Peak memory 201152 kb
Host smart-2f4e2ba8-2f90-46f8-95ea-9a852f7f98dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339368009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.339368009
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3644467046
Short name T803
Test name
Test status
Simulation time 503151065 ps
CPU time 0.9 seconds
Started Apr 25 12:48:00 PM PDT 24
Finished Apr 25 12:48:02 PM PDT 24
Peak memory 201184 kb
Host smart-28cdb6c1-340e-4bf7-873c-7326930f0419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644467046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3644467046
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4205962848
Short name T868
Test name
Test status
Simulation time 576112594 ps
CPU time 0.71 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201120 kb
Host smart-20990df5-91cc-4beb-9054-c74698ac9d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205962848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.4205962848
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2016837154
Short name T841
Test name
Test status
Simulation time 471981305 ps
CPU time 1.71 seconds
Started Apr 25 12:47:59 PM PDT 24
Finished Apr 25 12:48:02 PM PDT 24
Peak memory 201060 kb
Host smart-8e8d33d5-bd08-4ae2-a0f4-2d516a64ee4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016837154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2016837154
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.649159068
Short name T101
Test name
Test status
Simulation time 1226305144 ps
CPU time 3 seconds
Started Apr 25 12:47:36 PM PDT 24
Finished Apr 25 12:47:42 PM PDT 24
Peak memory 201372 kb
Host smart-318e31aa-1af5-49bb-9ecb-98cf85de86f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649159068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.649159068
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2904836476
Short name T814
Test name
Test status
Simulation time 26592811035 ps
CPU time 103.39 seconds
Started Apr 25 12:47:36 PM PDT 24
Finished Apr 25 12:49:21 PM PDT 24
Peak memory 201424 kb
Host smart-d5c5c8b9-1f6b-4f39-8531-3dbfffd05179
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904836476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2904836476
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1488425780
Short name T94
Test name
Test status
Simulation time 1251774367 ps
CPU time 3.63 seconds
Started Apr 25 12:47:46 PM PDT 24
Finished Apr 25 12:47:53 PM PDT 24
Peak memory 201160 kb
Host smart-3b56abbe-3a11-4cde-8df1-a3a1e00e5bd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488425780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1488425780
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1188170816
Short name T830
Test name
Test status
Simulation time 430373271 ps
CPU time 1.03 seconds
Started Apr 25 12:47:41 PM PDT 24
Finished Apr 25 12:47:45 PM PDT 24
Peak memory 201232 kb
Host smart-913420ad-668d-4942-ad9b-79f31715ef5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188170816 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1188170816
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.488044956
Short name T858
Test name
Test status
Simulation time 317002945 ps
CPU time 1.06 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:48 PM PDT 24
Peak memory 201188 kb
Host smart-41da5b7a-8a35-4ff5-bb0f-aac3c7e322e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488044956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.488044956
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2202229438
Short name T848
Test name
Test status
Simulation time 316354903 ps
CPU time 0.84 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:52 PM PDT 24
Peak memory 201200 kb
Host smart-47e88ae9-08fb-472f-b4e4-14dff14c7283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202229438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2202229438
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2038708125
Short name T114
Test name
Test status
Simulation time 2750076513 ps
CPU time 2.39 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:48 PM PDT 24
Peak memory 201476 kb
Host smart-fe2fdb50-4fa7-4baa-beb8-9bcdaf77ca67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038708125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2038708125
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2182922658
Short name T835
Test name
Test status
Simulation time 523215218 ps
CPU time 2.88 seconds
Started Apr 25 12:47:36 PM PDT 24
Finished Apr 25 12:47:41 PM PDT 24
Peak memory 201448 kb
Host smart-f094a8bc-4275-4b66-8c7b-55763099a73a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182922658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2182922658
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1307403973
Short name T885
Test name
Test status
Simulation time 8465710480 ps
CPU time 22.91 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:48:15 PM PDT 24
Peak memory 201380 kb
Host smart-4bb902eb-a09d-450b-b7d2-039bd15a3dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307403973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1307403973
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1065740745
Short name T874
Test name
Test status
Simulation time 519082992 ps
CPU time 1.92 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201196 kb
Host smart-8a3b7c8f-495f-435f-b5cc-3ac2faa13379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065740745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1065740745
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2807816749
Short name T817
Test name
Test status
Simulation time 500621722 ps
CPU time 1.75 seconds
Started Apr 25 12:47:55 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 201100 kb
Host smart-da8f8551-6902-47f9-a89c-3e64a719c67e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807816749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2807816749
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2680280089
Short name T906
Test name
Test status
Simulation time 461737465 ps
CPU time 1.47 seconds
Started Apr 25 12:47:54 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 201156 kb
Host smart-ecd94a7d-c07b-4a55-9613-ed18cd8633c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680280089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2680280089
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1699474640
Short name T800
Test name
Test status
Simulation time 408356115 ps
CPU time 1.53 seconds
Started Apr 25 12:47:56 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201124 kb
Host smart-31c51426-ddf6-4f52-a41b-79346475eb0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699474640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1699474640
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.312945531
Short name T847
Test name
Test status
Simulation time 552625358 ps
CPU time 0.96 seconds
Started Apr 25 12:48:01 PM PDT 24
Finished Apr 25 12:48:03 PM PDT 24
Peak memory 201196 kb
Host smart-9bf81bef-6b31-466a-b3fd-d2d26c794ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312945531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.312945531
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1318030383
Short name T842
Test name
Test status
Simulation time 474757201 ps
CPU time 0.91 seconds
Started Apr 25 12:47:57 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201232 kb
Host smart-3382d319-6a5d-4ac0-bfa4-b2a222429fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318030383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1318030383
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.312934857
Short name T796
Test name
Test status
Simulation time 502339897 ps
CPU time 0.91 seconds
Started Apr 25 12:47:58 PM PDT 24
Finished Apr 25 12:48:00 PM PDT 24
Peak memory 201216 kb
Host smart-b0370c88-71fb-4e5d-b0df-be715510c617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312934857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.312934857
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.487512763
Short name T837
Test name
Test status
Simulation time 468592703 ps
CPU time 0.76 seconds
Started Apr 25 12:47:58 PM PDT 24
Finished Apr 25 12:48:00 PM PDT 24
Peak memory 201224 kb
Host smart-83e5ccdb-e8b9-43aa-9623-d01bbd2b738a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487512763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.487512763
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2009342078
Short name T825
Test name
Test status
Simulation time 363443872 ps
CPU time 0.82 seconds
Started Apr 25 12:47:59 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201148 kb
Host smart-384fc890-1eac-4a38-b6e1-9704d99e3f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009342078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2009342078
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2609073284
Short name T876
Test name
Test status
Simulation time 315113649 ps
CPU time 1.36 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201128 kb
Host smart-b2c6d949-2c33-41cb-8e68-0b7f0d6a9841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609073284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2609073284
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2809233102
Short name T106
Test name
Test status
Simulation time 1857971529 ps
CPU time 2.63 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:49 PM PDT 24
Peak memory 201444 kb
Host smart-187da240-1da4-477f-b897-21238651f01c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809233102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2809233102
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.631966846
Short name T100
Test name
Test status
Simulation time 1199490345 ps
CPU time 6.14 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:52 PM PDT 24
Peak memory 201364 kb
Host smart-1f119ac0-5df9-44b8-9692-28f7670d51de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631966846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.631966846
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1731379582
Short name T916
Test name
Test status
Simulation time 1327062951 ps
CPU time 3.91 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201132 kb
Host smart-b5d325b8-cb26-477e-aa9f-eb7d97c69c25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731379582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1731379582
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3906002114
Short name T845
Test name
Test status
Simulation time 597380408 ps
CPU time 1.22 seconds
Started Apr 25 12:47:37 PM PDT 24
Finished Apr 25 12:47:40 PM PDT 24
Peak memory 201268 kb
Host smart-b9ad3165-1524-4d54-9b36-c4c8f60bc2eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906002114 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3906002114
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2636809681
Short name T839
Test name
Test status
Simulation time 306872677 ps
CPU time 1.37 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:52 PM PDT 24
Peak memory 201176 kb
Host smart-016d8a99-0f3b-4b6b-aaaa-cce6b97ba031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636809681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2636809681
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1869115985
Short name T893
Test name
Test status
Simulation time 316214824 ps
CPU time 0.99 seconds
Started Apr 25 12:47:45 PM PDT 24
Finished Apr 25 12:47:48 PM PDT 24
Peak memory 201152 kb
Host smart-6035336a-07f3-46ba-b1ac-8b2a0e43a0ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869115985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1869115985
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3319414247
Short name T836
Test name
Test status
Simulation time 4437721710 ps
CPU time 3.44 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201484 kb
Host smart-ba2d209f-4245-4a88-997f-2bddf4bfbf20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319414247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3319414247
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1440558566
Short name T811
Test name
Test status
Simulation time 523076912 ps
CPU time 2.5 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 201468 kb
Host smart-5117b497-51b7-4a84-9799-78d6288c9d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440558566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1440558566
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3788668838
Short name T910
Test name
Test status
Simulation time 5401899622 ps
CPU time 2.29 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:49 PM PDT 24
Peak memory 201448 kb
Host smart-519bdb1f-5a0b-4803-be8f-69dd06bebdec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788668838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3788668838
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2609275213
Short name T900
Test name
Test status
Simulation time 399520211 ps
CPU time 0.91 seconds
Started Apr 25 12:48:20 PM PDT 24
Finished Apr 25 12:48:22 PM PDT 24
Peak memory 201196 kb
Host smart-b9e99f6d-1432-4848-a8de-31783ed236d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609275213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2609275213
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2381588912
Short name T804
Test name
Test status
Simulation time 311606870 ps
CPU time 1.01 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201164 kb
Host smart-52c49b23-08f4-414b-a90e-e573d15a5b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381588912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2381588912
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.464747327
Short name T802
Test name
Test status
Simulation time 520435411 ps
CPU time 1.87 seconds
Started Apr 25 12:48:00 PM PDT 24
Finished Apr 25 12:48:04 PM PDT 24
Peak memory 201180 kb
Host smart-3a109850-73a5-463c-8298-13059f08157c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464747327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.464747327
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1004093675
Short name T801
Test name
Test status
Simulation time 523056339 ps
CPU time 0.82 seconds
Started Apr 25 12:47:54 PM PDT 24
Finished Apr 25 12:47:57 PM PDT 24
Peak memory 201200 kb
Host smart-c523ddde-7771-41eb-bc10-c420b6241a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004093675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1004093675
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3839286544
Short name T797
Test name
Test status
Simulation time 283012417 ps
CPU time 1.33 seconds
Started Apr 25 12:48:02 PM PDT 24
Finished Apr 25 12:48:04 PM PDT 24
Peak memory 201148 kb
Host smart-c18f5ccf-7ecc-4a51-bd6a-bb0882e5e459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839286544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3839286544
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1522035125
Short name T826
Test name
Test status
Simulation time 433385816 ps
CPU time 0.86 seconds
Started Apr 25 12:47:59 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201084 kb
Host smart-6c2214f0-6b9f-4043-bdeb-96f11c984bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522035125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1522035125
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3827982138
Short name T832
Test name
Test status
Simulation time 517949790 ps
CPU time 1.77 seconds
Started Apr 25 12:47:51 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201108 kb
Host smart-6c7cf226-9b63-4e0d-97b2-3f5515b9e3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827982138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3827982138
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1210727486
Short name T896
Test name
Test status
Simulation time 343822977 ps
CPU time 1.02 seconds
Started Apr 25 12:47:57 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201216 kb
Host smart-ed84bf72-32c2-44ad-be79-bdda0f307b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210727486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1210727486
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1033130612
Short name T867
Test name
Test status
Simulation time 529772461 ps
CPU time 1.88 seconds
Started Apr 25 12:48:07 PM PDT 24
Finished Apr 25 12:48:10 PM PDT 24
Peak memory 201236 kb
Host smart-8a3e92c8-e3f6-4566-b8f9-e549ed2ebc48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033130612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1033130612
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3518384273
Short name T856
Test name
Test status
Simulation time 518763480 ps
CPU time 1.59 seconds
Started Apr 25 12:47:58 PM PDT 24
Finished Apr 25 12:48:01 PM PDT 24
Peak memory 201208 kb
Host smart-1797f785-95dc-4bb6-a0f9-ea66f968fd9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518384273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3518384273
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.237709995
Short name T57
Test name
Test status
Simulation time 552480259 ps
CPU time 2.06 seconds
Started Apr 25 12:47:43 PM PDT 24
Finished Apr 25 12:47:53 PM PDT 24
Peak memory 201308 kb
Host smart-2dd0ee3b-c731-4880-9b11-dc7db9beee08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237709995 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.237709995
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1693049316
Short name T104
Test name
Test status
Simulation time 384298357 ps
CPU time 0.98 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:41 PM PDT 24
Peak memory 201116 kb
Host smart-e4767cf3-7b6b-4e97-9945-93bb224a710c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693049316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1693049316
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1890746506
Short name T899
Test name
Test status
Simulation time 504889472 ps
CPU time 1.82 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:53 PM PDT 24
Peak memory 201188 kb
Host smart-86334085-a28d-4d3e-a908-6183a5d75c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890746506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1890746506
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3844372280
Short name T827
Test name
Test status
Simulation time 5492694587 ps
CPU time 3.84 seconds
Started Apr 25 12:47:36 PM PDT 24
Finished Apr 25 12:47:42 PM PDT 24
Peak memory 201448 kb
Host smart-35b19d41-eaba-4ea0-9930-45dba9336048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844372280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3844372280
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.274584749
Short name T914
Test name
Test status
Simulation time 395422532 ps
CPU time 2.79 seconds
Started Apr 25 12:47:45 PM PDT 24
Finished Apr 25 12:47:50 PM PDT 24
Peak memory 201404 kb
Host smart-f3670f7b-d2fb-4f60-a87c-c18dee7b73ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274584749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.274584749
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1355701275
Short name T71
Test name
Test status
Simulation time 8707812929 ps
CPU time 7.53 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:48:00 PM PDT 24
Peak memory 201516 kb
Host smart-b1e95bb1-049b-4358-b67c-8d64beba1c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355701275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1355701275
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3638525074
Short name T909
Test name
Test status
Simulation time 568915341 ps
CPU time 1.7 seconds
Started Apr 25 12:47:43 PM PDT 24
Finished Apr 25 12:47:46 PM PDT 24
Peak memory 201248 kb
Host smart-26bd33fa-d2a7-43f8-9634-490491638c5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638525074 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3638525074
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.132389355
Short name T103
Test name
Test status
Simulation time 459721597 ps
CPU time 1.83 seconds
Started Apr 25 12:47:36 PM PDT 24
Finished Apr 25 12:47:40 PM PDT 24
Peak memory 201156 kb
Host smart-b033d864-3e8f-4b31-854e-586cdd6287b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132389355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.132389355
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3230558470
Short name T799
Test name
Test status
Simulation time 361063977 ps
CPU time 1.4 seconds
Started Apr 25 12:47:37 PM PDT 24
Finished Apr 25 12:47:40 PM PDT 24
Peak memory 201200 kb
Host smart-a8cea127-3f7d-4738-b511-0b7a23523233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230558470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3230558470
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4196284232
Short name T109
Test name
Test status
Simulation time 2562486026 ps
CPU time 6.33 seconds
Started Apr 25 12:47:45 PM PDT 24
Finished Apr 25 12:47:59 PM PDT 24
Peak memory 201224 kb
Host smart-594ef891-c9a4-4f52-9aba-20fbe3116ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196284232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4196284232
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.730116954
Short name T63
Test name
Test status
Simulation time 594720954 ps
CPU time 3.56 seconds
Started Apr 25 12:47:48 PM PDT 24
Finished Apr 25 12:47:55 PM PDT 24
Peak memory 217736 kb
Host smart-8f107352-daa4-45fd-980e-e0e9978be87a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730116954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.730116954
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1566482180
Short name T902
Test name
Test status
Simulation time 4552158153 ps
CPU time 4.23 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:51 PM PDT 24
Peak memory 201468 kb
Host smart-1958d2e1-785b-47f7-8f64-2e0d53c45bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566482180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1566482180
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4193490387
Short name T70
Test name
Test status
Simulation time 442212866 ps
CPU time 1.29 seconds
Started Apr 25 12:47:54 PM PDT 24
Finished Apr 25 12:47:57 PM PDT 24
Peak memory 201264 kb
Host smart-a04329c2-0c29-4e6e-a31a-a8e85aeae462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193490387 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4193490387
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1418272877
Short name T912
Test name
Test status
Simulation time 657788729 ps
CPU time 0.92 seconds
Started Apr 25 12:47:45 PM PDT 24
Finished Apr 25 12:47:48 PM PDT 24
Peak memory 200860 kb
Host smart-c806c8c4-a0a2-4402-bfb2-706f2e5accce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418272877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1418272877
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.455366020
Short name T905
Test name
Test status
Simulation time 320452462 ps
CPU time 0.8 seconds
Started Apr 25 12:47:49 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201136 kb
Host smart-c5621f57-f5cc-4e5d-9f4c-8c564ae8192a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455366020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.455366020
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3173004423
Short name T903
Test name
Test status
Simulation time 2372838349 ps
CPU time 1.87 seconds
Started Apr 25 12:47:43 PM PDT 24
Finished Apr 25 12:47:46 PM PDT 24
Peak memory 201300 kb
Host smart-e5311ec2-69a1-46eb-b121-8ed910450f59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173004423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3173004423
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3582274711
Short name T812
Test name
Test status
Simulation time 408075002 ps
CPU time 2.36 seconds
Started Apr 25 12:47:43 PM PDT 24
Finished Apr 25 12:47:46 PM PDT 24
Peak memory 201456 kb
Host smart-1e350706-b975-4b4a-bb4d-962990e5a209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582274711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3582274711
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1511165044
Short name T863
Test name
Test status
Simulation time 4439581184 ps
CPU time 12.79 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:52 PM PDT 24
Peak memory 201452 kb
Host smart-540b89df-20d5-46ab-8863-73c9c0bb589e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511165044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1511165044
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.325047248
Short name T908
Test name
Test status
Simulation time 356211542 ps
CPU time 1.51 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:52 PM PDT 24
Peak memory 201300 kb
Host smart-451c2e12-3a1e-4be2-a5a8-44cb1a682664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325047248 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.325047248
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.872674693
Short name T107
Test name
Test status
Simulation time 376654257 ps
CPU time 1.2 seconds
Started Apr 25 12:47:45 PM PDT 24
Finished Apr 25 12:47:49 PM PDT 24
Peak memory 201176 kb
Host smart-3c26baaa-a3ba-49cc-a409-336d5b492378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872674693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.872674693
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2199187723
Short name T807
Test name
Test status
Simulation time 507575657 ps
CPU time 1.06 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:41 PM PDT 24
Peak memory 201200 kb
Host smart-5c425c3e-17f2-480e-9cd2-b6b626f61bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199187723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2199187723
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3511194122
Short name T882
Test name
Test status
Simulation time 2816024502 ps
CPU time 11.85 seconds
Started Apr 25 12:47:50 PM PDT 24
Finished Apr 25 12:48:06 PM PDT 24
Peak memory 201260 kb
Host smart-9fb1295b-ba7d-427b-843e-a356da9874b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511194122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3511194122
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2936952347
Short name T61
Test name
Test status
Simulation time 554800376 ps
CPU time 2.39 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:43 PM PDT 24
Peak memory 217472 kb
Host smart-2622f33b-553f-4231-8eda-0fa9b4b3d181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936952347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2936952347
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.547985218
Short name T336
Test name
Test status
Simulation time 8237682896 ps
CPU time 13.61 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:54 PM PDT 24
Peak memory 201352 kb
Host smart-ca14c753-d31c-4b9e-8386-3d13513b4f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547985218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.547985218
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1930633009
Short name T844
Test name
Test status
Simulation time 450452451 ps
CPU time 1.06 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:47 PM PDT 24
Peak memory 201228 kb
Host smart-967dad1e-5498-44b1-8eef-36402b5d7691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930633009 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1930633009
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.473071055
Short name T849
Test name
Test status
Simulation time 345335683 ps
CPU time 0.91 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:41 PM PDT 24
Peak memory 201120 kb
Host smart-28c4a9ec-4f2e-439d-bbbb-909d3b53637b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473071055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.473071055
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.971976450
Short name T878
Test name
Test status
Simulation time 358185950 ps
CPU time 0.99 seconds
Started Apr 25 12:47:37 PM PDT 24
Finished Apr 25 12:47:40 PM PDT 24
Peak memory 201228 kb
Host smart-0201648c-e927-4c17-8b01-bc0afd260283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971976450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.971976450
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3986792841
Short name T887
Test name
Test status
Simulation time 3612104752 ps
CPU time 9.02 seconds
Started Apr 25 12:47:44 PM PDT 24
Finished Apr 25 12:47:56 PM PDT 24
Peak memory 201512 kb
Host smart-cf502693-18d7-45e6-bf93-0d0a01326ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986792841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3986792841
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4215476531
Short name T871
Test name
Test status
Simulation time 473628150 ps
CPU time 2.53 seconds
Started Apr 25 12:47:38 PM PDT 24
Finished Apr 25 12:47:42 PM PDT 24
Peak memory 201420 kb
Host smart-401222b9-dcc0-4bac-b4ea-46502241b0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215476531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4215476531
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2819393213
Short name T890
Test name
Test status
Simulation time 8733575043 ps
CPU time 7.97 seconds
Started Apr 25 12:47:47 PM PDT 24
Finished Apr 25 12:47:58 PM PDT 24
Peak memory 201484 kb
Host smart-6ef1dd1c-a91d-43fd-a955-a2f177d93364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819393213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2819393213
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3617135226
Short name T778
Test name
Test status
Simulation time 494053569 ps
CPU time 1.67 seconds
Started Apr 25 01:12:56 PM PDT 24
Finished Apr 25 01:12:59 PM PDT 24
Peak memory 201928 kb
Host smart-1e7a6265-d84b-4916-b110-08fc61d7a9c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617135226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3617135226
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1381148219
Short name T739
Test name
Test status
Simulation time 182005589036 ps
CPU time 94.92 seconds
Started Apr 25 01:12:57 PM PDT 24
Finished Apr 25 01:14:32 PM PDT 24
Peak memory 202332 kb
Host smart-61fb66d9-a1af-4c32-8263-df50c0c5cb34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381148219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1381148219
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1803393087
Short name T607
Test name
Test status
Simulation time 324317303742 ps
CPU time 205.83 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:16:12 PM PDT 24
Peak memory 202280 kb
Host smart-65cafa29-1e5a-4a8c-93ff-a8ebcc396ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803393087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1803393087
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3832666225
Short name T177
Test name
Test status
Simulation time 326537236312 ps
CPU time 356.52 seconds
Started Apr 25 01:12:56 PM PDT 24
Finished Apr 25 01:18:54 PM PDT 24
Peak memory 202216 kb
Host smart-b7507025-ebf1-4c21-8c89-d93a43e0418d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832666225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3832666225
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2935757212
Short name T399
Test name
Test status
Simulation time 331217333308 ps
CPU time 222.45 seconds
Started Apr 25 01:12:46 PM PDT 24
Finished Apr 25 01:16:30 PM PDT 24
Peak memory 202352 kb
Host smart-3a0f0af0-33d8-4cca-8c47-131d2eb5a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935757212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2935757212
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2694713133
Short name T360
Test name
Test status
Simulation time 486203012982 ps
CPU time 1130.27 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:31:36 PM PDT 24
Peak memory 202268 kb
Host smart-5b642d66-f2b6-45c9-b47b-0492bb16eaf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694713133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2694713133
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3951934839
Short name T296
Test name
Test status
Simulation time 329741782918 ps
CPU time 691.15 seconds
Started Apr 25 01:12:47 PM PDT 24
Finished Apr 25 01:24:19 PM PDT 24
Peak memory 202348 kb
Host smart-12cba929-df80-4f9e-be1e-95dec215bb71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951934839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3951934839
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1744116139
Short name T497
Test name
Test status
Simulation time 599167518020 ps
CPU time 1408.43 seconds
Started Apr 25 01:12:46 PM PDT 24
Finished Apr 25 01:36:16 PM PDT 24
Peak memory 202292 kb
Host smart-864e1728-b6b9-4881-b492-36449f8fabdd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744116139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1744116139
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.529685066
Short name T766
Test name
Test status
Simulation time 26962932910 ps
CPU time 33.81 seconds
Started Apr 25 01:12:46 PM PDT 24
Finished Apr 25 01:13:21 PM PDT 24
Peak memory 202128 kb
Host smart-37cf15d7-3907-46b7-9a8b-067eed90ae09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529685066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.529685066
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2694855071
Short name T668
Test name
Test status
Simulation time 3254063538 ps
CPU time 8.06 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:12:55 PM PDT 24
Peak memory 202092 kb
Host smart-9ff84b74-6798-482b-884a-65c62b786362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694855071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2694855071
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2548967223
Short name T694
Test name
Test status
Simulation time 5878454701 ps
CPU time 3.96 seconds
Started Apr 25 01:12:47 PM PDT 24
Finished Apr 25 01:12:52 PM PDT 24
Peak memory 202148 kb
Host smart-4957be5b-57e8-4564-b8c8-c1e459dcb222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548967223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2548967223
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1423676244
Short name T315
Test name
Test status
Simulation time 668245346752 ps
CPU time 366.28 seconds
Started Apr 25 01:12:47 PM PDT 24
Finished Apr 25 01:18:54 PM PDT 24
Peak memory 202328 kb
Host smart-82854296-5002-47a4-bb07-1c9d84b05767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423676244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1423676244
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1025001082
Short name T515
Test name
Test status
Simulation time 513297309 ps
CPU time 0.95 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:12:54 PM PDT 24
Peak memory 201892 kb
Host smart-67e43358-1d4f-4160-a34d-f101ac117f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025001082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1025001082
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3887388673
Short name T298
Test name
Test status
Simulation time 186706410153 ps
CPU time 224.31 seconds
Started Apr 25 01:12:54 PM PDT 24
Finished Apr 25 01:16:39 PM PDT 24
Peak memory 202336 kb
Host smart-5cfc91cc-6156-4e9a-b0f9-5613a8d058c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887388673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3887388673
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2555689620
Short name T531
Test name
Test status
Simulation time 482740055296 ps
CPU time 272.6 seconds
Started Apr 25 01:12:46 PM PDT 24
Finished Apr 25 01:17:20 PM PDT 24
Peak memory 202280 kb
Host smart-aac38aa2-4497-498b-8889-80885946d01f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555689620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2555689620
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2786384504
Short name T602
Test name
Test status
Simulation time 167846612841 ps
CPU time 159.33 seconds
Started Apr 25 01:12:46 PM PDT 24
Finished Apr 25 01:15:26 PM PDT 24
Peak memory 202236 kb
Host smart-e2b7d88d-ed33-4fae-bced-473075e895c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786384504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2786384504
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3783653877
Short name T469
Test name
Test status
Simulation time 568219176013 ps
CPU time 380.51 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:19:07 PM PDT 24
Peak memory 202380 kb
Host smart-7ab919bd-34cb-488d-b02c-f5403e517336
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783653877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3783653877
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.822437560
Short name T462
Test name
Test status
Simulation time 612318537077 ps
CPU time 87.53 seconds
Started Apr 25 01:12:46 PM PDT 24
Finished Apr 25 01:14:15 PM PDT 24
Peak memory 202280 kb
Host smart-7614ceba-fa1a-402b-a785-04eab8df7d86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822437560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.822437560
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1531169261
Short name T45
Test name
Test status
Simulation time 98297838988 ps
CPU time 491.42 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:21:04 PM PDT 24
Peak memory 202680 kb
Host smart-805a3f31-f75f-47ac-96b2-17cee4966a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531169261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1531169261
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1659427627
Short name T342
Test name
Test status
Simulation time 26849609977 ps
CPU time 3.78 seconds
Started Apr 25 01:12:50 PM PDT 24
Finished Apr 25 01:12:54 PM PDT 24
Peak memory 202096 kb
Host smart-1a0c124d-00f5-443a-bf1c-7e11afe6b7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659427627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1659427627
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1192903041
Short name T392
Test name
Test status
Simulation time 4605903152 ps
CPU time 11.25 seconds
Started Apr 25 01:12:55 PM PDT 24
Finished Apr 25 01:13:07 PM PDT 24
Peak memory 202132 kb
Host smart-b7d278f4-4dc1-466c-9a42-930d48260f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192903041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1192903041
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.870874515
Short name T60
Test name
Test status
Simulation time 4204679481 ps
CPU time 2.09 seconds
Started Apr 25 01:12:50 PM PDT 24
Finished Apr 25 01:12:52 PM PDT 24
Peak memory 217928 kb
Host smart-0a07628c-26ab-40bb-8f91-a0c66e4080b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870874515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.870874515
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2235227853
Short name T610
Test name
Test status
Simulation time 5725260830 ps
CPU time 14.13 seconds
Started Apr 25 01:12:54 PM PDT 24
Finished Apr 25 01:13:09 PM PDT 24
Peak memory 202072 kb
Host smart-c06afc00-2e39-43f4-bf83-5e406f704c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235227853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2235227853
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1914047695
Short name T367
Test name
Test status
Simulation time 43919409992 ps
CPU time 93.45 seconds
Started Apr 25 01:12:55 PM PDT 24
Finished Apr 25 01:14:29 PM PDT 24
Peak memory 202388 kb
Host smart-4bc05eda-982f-429a-8f4c-2ecf30d88021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914047695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1914047695
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.733241797
Short name T91
Test name
Test status
Simulation time 43820186208 ps
CPU time 103.16 seconds
Started Apr 25 01:12:53 PM PDT 24
Finished Apr 25 01:14:37 PM PDT 24
Peak memory 211060 kb
Host smart-73220797-c96a-455d-be57-3f849ad865dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733241797 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.733241797
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1977408037
Short name T413
Test name
Test status
Simulation time 445096035 ps
CPU time 0.72 seconds
Started Apr 25 01:13:27 PM PDT 24
Finished Apr 25 01:13:28 PM PDT 24
Peak memory 202012 kb
Host smart-29b6e873-a6f0-416f-a06c-1ed652016798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977408037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1977408037
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.699648953
Short name T292
Test name
Test status
Simulation time 378420928535 ps
CPU time 477 seconds
Started Apr 25 01:13:27 PM PDT 24
Finished Apr 25 01:21:25 PM PDT 24
Peak memory 202284 kb
Host smart-a3e519da-4295-4fde-94a9-31bd410acf7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699648953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.699648953
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.272636748
Short name T308
Test name
Test status
Simulation time 231806876656 ps
CPU time 138.8 seconds
Started Apr 25 01:13:40 PM PDT 24
Finished Apr 25 01:15:59 PM PDT 24
Peak memory 202316 kb
Host smart-dd138378-ed75-459e-bf10-e86a9faa81af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272636748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.272636748
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1066080507
Short name T181
Test name
Test status
Simulation time 490494557008 ps
CPU time 234.18 seconds
Started Apr 25 01:13:28 PM PDT 24
Finished Apr 25 01:17:23 PM PDT 24
Peak memory 202332 kb
Host smart-21dd5dfe-6b12-4f2c-855c-1126efe8147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066080507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1066080507
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.66005612
Short name T526
Test name
Test status
Simulation time 167297762830 ps
CPU time 90.4 seconds
Started Apr 25 01:13:31 PM PDT 24
Finished Apr 25 01:15:02 PM PDT 24
Peak memory 202320 kb
Host smart-fc58a426-b240-4003-b90c-2f623a81db71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=66005612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt
_fixed.66005612
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.4247858283
Short name T246
Test name
Test status
Simulation time 489524842551 ps
CPU time 294.34 seconds
Started Apr 25 01:13:25 PM PDT 24
Finished Apr 25 01:18:19 PM PDT 24
Peak memory 202116 kb
Host smart-b382e77a-8bac-467a-96d6-c29e0f48c8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247858283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.4247858283
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2443169753
Short name T355
Test name
Test status
Simulation time 163828881271 ps
CPU time 191.89 seconds
Started Apr 25 01:13:20 PM PDT 24
Finished Apr 25 01:16:33 PM PDT 24
Peak memory 202284 kb
Host smart-2bfd9d0a-c614-40bd-9735-f5c34bc667ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443169753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2443169753
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1719681805
Short name T620
Test name
Test status
Simulation time 197961920014 ps
CPU time 122.57 seconds
Started Apr 25 01:13:26 PM PDT 24
Finished Apr 25 01:15:29 PM PDT 24
Peak memory 202412 kb
Host smart-83f094f9-1ddc-4c17-b741-992cbdb07e14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719681805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1719681805
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2746987119
Short name T407
Test name
Test status
Simulation time 606694838015 ps
CPU time 1368.63 seconds
Started Apr 25 01:13:26 PM PDT 24
Finished Apr 25 01:36:15 PM PDT 24
Peak memory 202308 kb
Host smart-c8781109-74c6-4f20-9bbf-ebf77b1c8d43
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746987119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2746987119
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.762442038
Short name T764
Test name
Test status
Simulation time 76818007632 ps
CPU time 328 seconds
Started Apr 25 01:13:25 PM PDT 24
Finished Apr 25 01:18:53 PM PDT 24
Peak memory 202672 kb
Host smart-b2c4f795-fad9-4fd8-9e20-b95b5a764054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762442038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.762442038
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3878154403
Short name T612
Test name
Test status
Simulation time 31340389719 ps
CPU time 77.47 seconds
Started Apr 25 01:13:26 PM PDT 24
Finished Apr 25 01:14:44 PM PDT 24
Peak memory 202056 kb
Host smart-42b382e8-4e7b-4f39-9f26-c513c18aa32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878154403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3878154403
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1536963894
Short name T347
Test name
Test status
Simulation time 3158094427 ps
CPU time 4.7 seconds
Started Apr 25 01:13:27 PM PDT 24
Finished Apr 25 01:13:32 PM PDT 24
Peak memory 202132 kb
Host smart-8ca3d774-d68f-4973-ae2b-9c387ff2f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536963894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1536963894
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.804099267
Short name T669
Test name
Test status
Simulation time 5994667629 ps
CPU time 6.29 seconds
Started Apr 25 01:13:23 PM PDT 24
Finished Apr 25 01:13:30 PM PDT 24
Peak memory 202128 kb
Host smart-a193dfcc-a027-4436-99b4-f3b4ac95111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804099267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.804099267
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.308347913
Short name T195
Test name
Test status
Simulation time 87632052887 ps
CPU time 324.96 seconds
Started Apr 25 01:13:27 PM PDT 24
Finished Apr 25 01:18:52 PM PDT 24
Peak memory 202688 kb
Host smart-6574c45b-d8e9-4d65-acd9-984f22bd6067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308347913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
308347913
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.362502417
Short name T299
Test name
Test status
Simulation time 29944812622 ps
CPU time 72.98 seconds
Started Apr 25 01:13:29 PM PDT 24
Finished Apr 25 01:14:42 PM PDT 24
Peak memory 210648 kb
Host smart-35b1955b-9b9f-4b2b-8c95-d2974d74bd95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362502417 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.362502417
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3772971571
Short name T732
Test name
Test status
Simulation time 525643402 ps
CPU time 0.94 seconds
Started Apr 25 01:13:31 PM PDT 24
Finished Apr 25 01:13:33 PM PDT 24
Peak memory 201984 kb
Host smart-2c20ca30-6368-40d5-9f9c-260b9fde4fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772971571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3772971571
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.172831885
Short name T294
Test name
Test status
Simulation time 163164985558 ps
CPU time 92.08 seconds
Started Apr 25 01:13:30 PM PDT 24
Finished Apr 25 01:15:03 PM PDT 24
Peak memory 202384 kb
Host smart-5c624cbe-6758-40d5-b733-f982e6512da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172831885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.172831885
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2699659503
Short name T374
Test name
Test status
Simulation time 493611764994 ps
CPU time 536.85 seconds
Started Apr 25 01:13:30 PM PDT 24
Finished Apr 25 01:22:28 PM PDT 24
Peak memory 202308 kb
Host smart-65be360c-6739-4094-82c0-0e99790b3508
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699659503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2699659503
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.654941394
Short name T244
Test name
Test status
Simulation time 158444610709 ps
CPU time 368.45 seconds
Started Apr 25 01:13:27 PM PDT 24
Finished Apr 25 01:19:36 PM PDT 24
Peak memory 202240 kb
Host smart-fb0bdd5a-5d3d-4836-8fe2-bfc67b02c005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654941394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.654941394
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.296646175
Short name T341
Test name
Test status
Simulation time 496035656974 ps
CPU time 609.23 seconds
Started Apr 25 01:13:33 PM PDT 24
Finished Apr 25 01:23:43 PM PDT 24
Peak memory 202256 kb
Host smart-24cee834-165d-41d6-acad-8f4b81bc8e94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=296646175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.296646175
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.970540635
Short name T137
Test name
Test status
Simulation time 540846580199 ps
CPU time 456.95 seconds
Started Apr 25 01:13:30 PM PDT 24
Finished Apr 25 01:21:08 PM PDT 24
Peak memory 202348 kb
Host smart-d3d0fab9-24c5-492c-8c04-d8bb046c7687
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970540635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.970540635
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1625931930
Short name T433
Test name
Test status
Simulation time 584709123811 ps
CPU time 684.96 seconds
Started Apr 25 01:13:32 PM PDT 24
Finished Apr 25 01:24:57 PM PDT 24
Peak memory 202360 kb
Host smart-87187734-a52b-45db-af61-89b343077974
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625931930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1625931930
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.828201464
Short name T451
Test name
Test status
Simulation time 48340243721 ps
CPU time 108.86 seconds
Started Apr 25 01:13:30 PM PDT 24
Finished Apr 25 01:15:20 PM PDT 24
Peak memory 202128 kb
Host smart-2df00460-84c8-434f-8b26-a8727d720848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828201464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.828201464
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2041353384
Short name T432
Test name
Test status
Simulation time 2677167238 ps
CPU time 6.44 seconds
Started Apr 25 01:13:32 PM PDT 24
Finished Apr 25 01:13:39 PM PDT 24
Peak memory 202128 kb
Host smart-4945c263-af37-4e8b-902b-37da2a2d35f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041353384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2041353384
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.230963386
Short name T785
Test name
Test status
Simulation time 6083304773 ps
CPU time 15.99 seconds
Started Apr 25 01:13:33 PM PDT 24
Finished Apr 25 01:13:49 PM PDT 24
Peak memory 202112 kb
Host smart-3cf3b7b6-508c-44d2-97f9-675705943bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230963386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.230963386
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3624958453
Short name T546
Test name
Test status
Simulation time 409040040 ps
CPU time 1.09 seconds
Started Apr 25 01:13:42 PM PDT 24
Finished Apr 25 01:13:44 PM PDT 24
Peak memory 202012 kb
Host smart-6c293180-d23b-4163-a4a2-449c99e4a019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624958453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3624958453
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.569144373
Short name T289
Test name
Test status
Simulation time 163147728673 ps
CPU time 382.9 seconds
Started Apr 25 01:13:37 PM PDT 24
Finished Apr 25 01:20:00 PM PDT 24
Peak memory 202308 kb
Host smart-0c3c2a6b-27f0-446d-b00c-5bb724af2086
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569144373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.569144373
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.250188578
Short name T576
Test name
Test status
Simulation time 160164985034 ps
CPU time 192.01 seconds
Started Apr 25 01:13:38 PM PDT 24
Finished Apr 25 01:16:51 PM PDT 24
Peak memory 202372 kb
Host smart-da9953c6-4b45-473b-a92d-f81fa85ab60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250188578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.250188578
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3460527074
Short name T792
Test name
Test status
Simulation time 163151906613 ps
CPU time 389.97 seconds
Started Apr 25 01:13:39 PM PDT 24
Finished Apr 25 01:20:09 PM PDT 24
Peak memory 202312 kb
Host smart-6b09df32-9d80-492e-b918-d77c6455b6a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460527074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3460527074
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3244424531
Short name T496
Test name
Test status
Simulation time 497580516721 ps
CPU time 279.43 seconds
Started Apr 25 01:13:31 PM PDT 24
Finished Apr 25 01:18:11 PM PDT 24
Peak memory 202332 kb
Host smart-cea3e0d4-6d90-4c7c-aee3-8d144ea35aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244424531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3244424531
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3852803250
Short name T507
Test name
Test status
Simulation time 486132497142 ps
CPU time 613.31 seconds
Started Apr 25 01:13:30 PM PDT 24
Finished Apr 25 01:23:44 PM PDT 24
Peak memory 202304 kb
Host smart-60a7b05f-98c4-4326-890d-dd91b079383c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852803250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3852803250
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.785067058
Short name T771
Test name
Test status
Simulation time 182373724589 ps
CPU time 198.5 seconds
Started Apr 25 01:13:37 PM PDT 24
Finished Apr 25 01:16:56 PM PDT 24
Peak memory 202328 kb
Host smart-44151d63-a76b-46d1-889d-c350683753bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785067058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.785067058
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3999085219
Short name T599
Test name
Test status
Simulation time 199772393875 ps
CPU time 245.65 seconds
Started Apr 25 01:13:36 PM PDT 24
Finished Apr 25 01:17:43 PM PDT 24
Peak memory 202284 kb
Host smart-009efbad-05d0-438b-a80f-b6461ca058a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999085219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3999085219
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1632350194
Short name T644
Test name
Test status
Simulation time 90921968043 ps
CPU time 370.7 seconds
Started Apr 25 01:13:38 PM PDT 24
Finished Apr 25 01:19:49 PM PDT 24
Peak memory 202644 kb
Host smart-f2e9b89e-8fe9-448a-8d80-b7cd3e0b0c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632350194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1632350194
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4175822197
Short name T485
Test name
Test status
Simulation time 24685235116 ps
CPU time 14.87 seconds
Started Apr 25 01:13:39 PM PDT 24
Finished Apr 25 01:13:54 PM PDT 24
Peak memory 202080 kb
Host smart-31436c3d-a9e3-40fd-b422-5a2142f4574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175822197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4175822197
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2901169354
Short name T499
Test name
Test status
Simulation time 4928012909 ps
CPU time 2.19 seconds
Started Apr 25 01:13:37 PM PDT 24
Finished Apr 25 01:13:40 PM PDT 24
Peak memory 202128 kb
Host smart-b4691dbd-58e7-4f21-aeb3-4e73d29cdd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901169354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2901169354
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.28881062
Short name T361
Test name
Test status
Simulation time 6034867338 ps
CPU time 16.09 seconds
Started Apr 25 01:13:38 PM PDT 24
Finished Apr 25 01:13:55 PM PDT 24
Peak memory 202136 kb
Host smart-65c61e44-f1c1-492c-a087-c0537ca01ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28881062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.28881062
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3082817830
Short name T498
Test name
Test status
Simulation time 362390553733 ps
CPU time 886.5 seconds
Started Apr 25 01:13:38 PM PDT 24
Finished Apr 25 01:28:26 PM PDT 24
Peak memory 202336 kb
Host smart-5513a5c4-5108-49ca-bd80-9a93e9776957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082817830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3082817830
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3399693464
Short name T762
Test name
Test status
Simulation time 350334342817 ps
CPU time 196.73 seconds
Started Apr 25 01:13:37 PM PDT 24
Finished Apr 25 01:16:54 PM PDT 24
Peak memory 202468 kb
Host smart-5bbede1d-e379-4e71-bbd8-1fc522362db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399693464 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3399693464
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2919365496
Short name T525
Test name
Test status
Simulation time 414643077 ps
CPU time 1.64 seconds
Started Apr 25 01:13:50 PM PDT 24
Finished Apr 25 01:13:52 PM PDT 24
Peak memory 201936 kb
Host smart-d36c9120-795c-48c2-a4b5-dab3927dd9d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919365496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2919365496
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1801439226
Short name T500
Test name
Test status
Simulation time 166615495650 ps
CPU time 358.16 seconds
Started Apr 25 01:13:46 PM PDT 24
Finished Apr 25 01:19:45 PM PDT 24
Peak memory 202272 kb
Host smart-3b47dfd2-03b2-41d7-a4be-59a8b3468c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801439226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1801439226
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1397825320
Short name T215
Test name
Test status
Simulation time 167953690436 ps
CPU time 356.08 seconds
Started Apr 25 01:13:45 PM PDT 24
Finished Apr 25 01:19:42 PM PDT 24
Peak memory 202312 kb
Host smart-a6ea3688-e0a8-4fa8-8224-13ce73679ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397825320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1397825320
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.231881490
Short name T759
Test name
Test status
Simulation time 329728709049 ps
CPU time 805.21 seconds
Started Apr 25 01:13:43 PM PDT 24
Finished Apr 25 01:27:09 PM PDT 24
Peak memory 202268 kb
Host smart-aa4f7237-e48b-4e73-a82a-5c39a0e203a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=231881490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.231881490
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.276562511
Short name T144
Test name
Test status
Simulation time 172116330953 ps
CPU time 97.65 seconds
Started Apr 25 01:13:41 PM PDT 24
Finished Apr 25 01:15:19 PM PDT 24
Peak memory 202284 kb
Host smart-ce14719e-14d9-41eb-9da8-28aa1779656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276562511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.276562511
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1186046371
Short name T670
Test name
Test status
Simulation time 169670255862 ps
CPU time 99.42 seconds
Started Apr 25 01:13:46 PM PDT 24
Finished Apr 25 01:15:26 PM PDT 24
Peak memory 202284 kb
Host smart-3eda389e-5a78-4101-ab1b-61d33a62bd71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186046371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1186046371
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.591394352
Short name T39
Test name
Test status
Simulation time 385315577067 ps
CPU time 699.5 seconds
Started Apr 25 01:13:42 PM PDT 24
Finished Apr 25 01:25:22 PM PDT 24
Peak memory 202268 kb
Host smart-dd7a0a62-fb82-4e43-a0c5-b4a23d6e8644
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591394352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.591394352
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2487689114
Short name T387
Test name
Test status
Simulation time 201713940225 ps
CPU time 31.55 seconds
Started Apr 25 01:13:43 PM PDT 24
Finished Apr 25 01:14:15 PM PDT 24
Peak memory 202292 kb
Host smart-d9689129-b847-495e-9b38-54b541bd52ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487689114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2487689114
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3755408932
Short name T547
Test name
Test status
Simulation time 98443874080 ps
CPU time 360.83 seconds
Started Apr 25 01:13:48 PM PDT 24
Finished Apr 25 01:19:50 PM PDT 24
Peak memory 202696 kb
Host smart-2745f3f9-10cf-42d9-89f5-d641635f3fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755408932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3755408932
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.40254316
Short name T528
Test name
Test status
Simulation time 24202484686 ps
CPU time 15.81 seconds
Started Apr 25 01:13:47 PM PDT 24
Finished Apr 25 01:14:03 PM PDT 24
Peak memory 202112 kb
Host smart-2f8777ca-3aeb-43bd-95cf-40733c2dff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40254316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.40254316
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1704395543
Short name T748
Test name
Test status
Simulation time 3917505052 ps
CPU time 8.35 seconds
Started Apr 25 01:13:44 PM PDT 24
Finished Apr 25 01:13:53 PM PDT 24
Peak memory 202136 kb
Host smart-e46c2707-f14c-45d8-bc10-8e4b18d834a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704395543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1704395543
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.338249634
Short name T171
Test name
Test status
Simulation time 5913509459 ps
CPU time 14.27 seconds
Started Apr 25 01:13:41 PM PDT 24
Finished Apr 25 01:13:56 PM PDT 24
Peak memory 202128 kb
Host smart-eace2647-810d-4d36-9f35-9aae95624a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338249634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.338249634
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3082319703
Short name T719
Test name
Test status
Simulation time 304334255088 ps
CPU time 479.72 seconds
Started Apr 25 01:13:50 PM PDT 24
Finished Apr 25 01:21:51 PM PDT 24
Peak memory 202376 kb
Host smart-aae95a63-58a6-44ef-b8c2-c841f2b96100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082319703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3082319703
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1815672665
Short name T13
Test name
Test status
Simulation time 15672862299 ps
CPU time 38.49 seconds
Started Apr 25 01:13:48 PM PDT 24
Finished Apr 25 01:14:27 PM PDT 24
Peak memory 210624 kb
Host smart-909a5075-713f-4b31-9bb0-5ff053d1f165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815672665 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1815672665
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1458574888
Short name T720
Test name
Test status
Simulation time 323450250 ps
CPU time 0.78 seconds
Started Apr 25 01:13:57 PM PDT 24
Finished Apr 25 01:13:58 PM PDT 24
Peak memory 202012 kb
Host smart-dbb28168-2034-4c55-b20a-53aa2c8cbdf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458574888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1458574888
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2212101930
Short name T320
Test name
Test status
Simulation time 501961513331 ps
CPU time 655.16 seconds
Started Apr 25 01:13:50 PM PDT 24
Finished Apr 25 01:24:46 PM PDT 24
Peak memory 202376 kb
Host smart-2b616839-6748-4a22-9637-e0c6eb562f74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212101930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2212101930
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2109067434
Short name T143
Test name
Test status
Simulation time 329422477210 ps
CPU time 186.39 seconds
Started Apr 25 01:13:55 PM PDT 24
Finished Apr 25 01:17:02 PM PDT 24
Peak memory 202296 kb
Host smart-455db4b2-9e07-4e97-87dc-c720fc7c8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109067434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2109067434
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4216447464
Short name T716
Test name
Test status
Simulation time 332969848840 ps
CPU time 759.06 seconds
Started Apr 25 01:13:50 PM PDT 24
Finished Apr 25 01:26:30 PM PDT 24
Peak memory 202308 kb
Host smart-0877141f-eb9c-466c-a9ce-b2bd44207fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216447464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.4216447464
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2871148562
Short name T516
Test name
Test status
Simulation time 331829766401 ps
CPU time 368.81 seconds
Started Apr 25 01:13:50 PM PDT 24
Finished Apr 25 01:19:59 PM PDT 24
Peak memory 202232 kb
Host smart-a49e56a2-632f-4db8-a2f7-6c42a15fefff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871148562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2871148562
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.436999540
Short name T677
Test name
Test status
Simulation time 484037361369 ps
CPU time 96.28 seconds
Started Apr 25 01:13:47 PM PDT 24
Finished Apr 25 01:15:24 PM PDT 24
Peak memory 202404 kb
Host smart-eae7551d-6ebe-4fd8-9836-aa57be36e20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436999540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.436999540
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.4278925957
Short name T584
Test name
Test status
Simulation time 327439964694 ps
CPU time 666.47 seconds
Started Apr 25 01:13:47 PM PDT 24
Finished Apr 25 01:24:55 PM PDT 24
Peak memory 202352 kb
Host smart-01ccc75f-c0f5-4a2d-bb5a-1d2462675802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278925957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.4278925957
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3299748749
Short name T701
Test name
Test status
Simulation time 598530152119 ps
CPU time 512.21 seconds
Started Apr 25 01:13:49 PM PDT 24
Finished Apr 25 01:22:22 PM PDT 24
Peak memory 202264 kb
Host smart-4b223449-58fd-4445-a7b9-a8900acc780e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299748749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3299748749
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1670895755
Short name T86
Test name
Test status
Simulation time 138264111721 ps
CPU time 467.51 seconds
Started Apr 25 01:13:49 PM PDT 24
Finished Apr 25 01:21:37 PM PDT 24
Peak memory 202656 kb
Host smart-1723d347-8954-4bb7-b377-c61fd2bb71cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670895755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1670895755
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4076945538
Short name T738
Test name
Test status
Simulation time 35672858473 ps
CPU time 12.66 seconds
Started Apr 25 01:13:48 PM PDT 24
Finished Apr 25 01:14:01 PM PDT 24
Peak memory 202132 kb
Host smart-9b6bd99d-7328-4c74-b87f-ff77a959ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076945538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4076945538
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3244878150
Short name T381
Test name
Test status
Simulation time 3783735495 ps
CPU time 6.73 seconds
Started Apr 25 01:13:47 PM PDT 24
Finished Apr 25 01:13:54 PM PDT 24
Peak memory 202132 kb
Host smart-c78c83aa-d423-4707-bfad-f07784ef5d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244878150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3244878150
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4257434806
Short name T448
Test name
Test status
Simulation time 6201048887 ps
CPU time 2.84 seconds
Started Apr 25 01:13:49 PM PDT 24
Finished Apr 25 01:13:52 PM PDT 24
Peak memory 202140 kb
Host smart-63fe35d0-79cf-4596-ad64-ef9f071405b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257434806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4257434806
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4069396418
Short name T332
Test name
Test status
Simulation time 248191687319 ps
CPU time 201.83 seconds
Started Apr 25 01:13:56 PM PDT 24
Finished Apr 25 01:17:19 PM PDT 24
Peak memory 210564 kb
Host smart-a25e0336-0b38-44eb-9d0e-c0e9a9767f52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069396418 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.4069396418
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1564141861
Short name T435
Test name
Test status
Simulation time 385309203 ps
CPU time 1.46 seconds
Started Apr 25 01:14:04 PM PDT 24
Finished Apr 25 01:14:06 PM PDT 24
Peak memory 202008 kb
Host smart-170c57db-436c-4ee4-99d7-b116cdeca6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564141861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1564141861
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2663344990
Short name T439
Test name
Test status
Simulation time 163023517618 ps
CPU time 51.16 seconds
Started Apr 25 01:13:53 PM PDT 24
Finished Apr 25 01:14:45 PM PDT 24
Peak memory 202232 kb
Host smart-1234522d-b645-4951-b353-dce326360281
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663344990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2663344990
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1408237257
Short name T750
Test name
Test status
Simulation time 481003795657 ps
CPU time 1045.93 seconds
Started Apr 25 01:13:53 PM PDT 24
Finished Apr 25 01:31:20 PM PDT 24
Peak memory 202384 kb
Host smart-cc6d7d33-d765-4b6b-b75a-0312550c9b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408237257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1408237257
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3587736001
Short name T429
Test name
Test status
Simulation time 322958271902 ps
CPU time 365.01 seconds
Started Apr 25 01:13:55 PM PDT 24
Finished Apr 25 01:20:01 PM PDT 24
Peak memory 202368 kb
Host smart-6cddcf56-d5d3-4ba2-ab62-c51d7f54a8c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587736001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3587736001
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2033563208
Short name T158
Test name
Test status
Simulation time 324610843698 ps
CPU time 41.98 seconds
Started Apr 25 01:13:56 PM PDT 24
Finished Apr 25 01:14:39 PM PDT 24
Peak memory 202372 kb
Host smart-3b98b68c-431c-4325-b1d5-50c436f7bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033563208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2033563208
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3618346535
Short name T509
Test name
Test status
Simulation time 166060772090 ps
CPU time 101.2 seconds
Started Apr 25 01:13:55 PM PDT 24
Finished Apr 25 01:15:37 PM PDT 24
Peak memory 202320 kb
Host smart-06667a89-685f-4b8a-ad5f-30092e9e4c12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618346535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3618346535
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3608936142
Short name T226
Test name
Test status
Simulation time 413890278301 ps
CPU time 528.09 seconds
Started Apr 25 01:13:54 PM PDT 24
Finished Apr 25 01:22:43 PM PDT 24
Peak memory 202320 kb
Host smart-12ba1f64-ec25-44d0-865e-0678e47b6efe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608936142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3608936142
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2871941964
Short name T345
Test name
Test status
Simulation time 604994574402 ps
CPU time 1444.22 seconds
Started Apr 25 01:13:52 PM PDT 24
Finished Apr 25 01:37:58 PM PDT 24
Peak memory 202312 kb
Host smart-e52cdd96-543e-464d-ac30-cf93c0b6fb1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871941964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2871941964
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3727601996
Short name T571
Test name
Test status
Simulation time 99285614182 ps
CPU time 411.88 seconds
Started Apr 25 01:14:03 PM PDT 24
Finished Apr 25 01:20:56 PM PDT 24
Peak memory 202660 kb
Host smart-994d594c-e741-4d30-b2ce-e7c86c42df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727601996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3727601996
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2630950625
Short name T455
Test name
Test status
Simulation time 44406177338 ps
CPU time 27.49 seconds
Started Apr 25 01:14:00 PM PDT 24
Finished Apr 25 01:14:28 PM PDT 24
Peak memory 202144 kb
Host smart-d0e2e56c-bf49-498b-8b81-3b05f0f933f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630950625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2630950625
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3142846060
Short name T683
Test name
Test status
Simulation time 2845533997 ps
CPU time 7.22 seconds
Started Apr 25 01:14:00 PM PDT 24
Finished Apr 25 01:14:08 PM PDT 24
Peak memory 202132 kb
Host smart-1ba84f28-7f9f-450a-bf9b-e64480a3ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142846060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3142846060
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2162355621
Short name T568
Test name
Test status
Simulation time 5789176915 ps
CPU time 1.89 seconds
Started Apr 25 01:14:01 PM PDT 24
Finished Apr 25 01:14:04 PM PDT 24
Peak memory 202140 kb
Host smart-3e7c106c-5b2c-407f-90b6-e4e8a749cdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162355621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2162355621
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2963822459
Short name T491
Test name
Test status
Simulation time 171663849167 ps
CPU time 107.16 seconds
Started Apr 25 01:14:00 PM PDT 24
Finished Apr 25 01:15:48 PM PDT 24
Peak memory 202320 kb
Host smart-2ae93517-b86b-4256-8a19-f0284a03d033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963822459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2963822459
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2784454718
Short name T753
Test name
Test status
Simulation time 418911550036 ps
CPU time 225.96 seconds
Started Apr 25 01:14:03 PM PDT 24
Finished Apr 25 01:17:51 PM PDT 24
Peak memory 210984 kb
Host smart-59a5c13a-5cc8-4808-ab25-92af85e05db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784454718 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2784454718
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3368577844
Short name T210
Test name
Test status
Simulation time 391875548754 ps
CPU time 119.52 seconds
Started Apr 25 01:14:03 PM PDT 24
Finished Apr 25 01:16:04 PM PDT 24
Peak memory 202232 kb
Host smart-92c90811-7da1-4793-bca2-011206180bdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368577844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3368577844
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3498678153
Short name T241
Test name
Test status
Simulation time 352107678863 ps
CPU time 421.33 seconds
Started Apr 25 01:14:05 PM PDT 24
Finished Apr 25 01:21:07 PM PDT 24
Peak memory 202196 kb
Host smart-d917128e-60f7-4edf-bed3-bcb27feca1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498678153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3498678153
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1867829474
Short name T126
Test name
Test status
Simulation time 331116421726 ps
CPU time 382.57 seconds
Started Apr 25 01:14:06 PM PDT 24
Finished Apr 25 01:20:29 PM PDT 24
Peak memory 202308 kb
Host smart-3212a51f-d454-418e-9efb-2a0d05f1b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867829474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1867829474
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1597400408
Short name T28
Test name
Test status
Simulation time 165498509532 ps
CPU time 358.48 seconds
Started Apr 25 01:14:04 PM PDT 24
Finished Apr 25 01:20:04 PM PDT 24
Peak memory 202256 kb
Host smart-9ebc5217-4782-4a9e-b92e-0910baa6f08b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597400408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1597400408
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3121901749
Short name T737
Test name
Test status
Simulation time 331913668916 ps
CPU time 72.91 seconds
Started Apr 25 01:14:04 PM PDT 24
Finished Apr 25 01:15:18 PM PDT 24
Peak memory 202356 kb
Host smart-9a876325-fc2a-4234-b680-0253edd5ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121901749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3121901749
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.294941117
Short name T409
Test name
Test status
Simulation time 482968874429 ps
CPU time 292.23 seconds
Started Apr 25 01:14:03 PM PDT 24
Finished Apr 25 01:18:57 PM PDT 24
Peak memory 202268 kb
Host smart-d40318df-2ceb-4f32-a830-dca2a1713c23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=294941117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.294941117
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3491853783
Short name T167
Test name
Test status
Simulation time 355427892360 ps
CPU time 196.62 seconds
Started Apr 25 01:14:04 PM PDT 24
Finished Apr 25 01:17:22 PM PDT 24
Peak memory 202200 kb
Host smart-729290fb-bc21-412a-a5b5-ca646cd9256d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491853783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3491853783
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1865730743
Short name T454
Test name
Test status
Simulation time 408094251695 ps
CPU time 894.38 seconds
Started Apr 25 01:14:03 PM PDT 24
Finished Apr 25 01:28:59 PM PDT 24
Peak memory 202324 kb
Host smart-a157f96d-c6eb-4ec9-92e3-8fdbe9ee51c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865730743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1865730743
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2072469021
Short name T203
Test name
Test status
Simulation time 133710232851 ps
CPU time 442.59 seconds
Started Apr 25 01:14:03 PM PDT 24
Finished Apr 25 01:21:27 PM PDT 24
Peak memory 202684 kb
Host smart-a0b55d60-84ed-4014-930e-96b7be594560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072469021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2072469021
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1587431522
Short name T141
Test name
Test status
Simulation time 24421774310 ps
CPU time 56.12 seconds
Started Apr 25 01:14:06 PM PDT 24
Finished Apr 25 01:15:03 PM PDT 24
Peak memory 202128 kb
Host smart-c37df320-3392-46c6-8b71-e147625a0d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587431522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1587431522
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.488977482
Short name T775
Test name
Test status
Simulation time 4903344640 ps
CPU time 3.38 seconds
Started Apr 25 01:14:04 PM PDT 24
Finished Apr 25 01:14:09 PM PDT 24
Peak memory 202116 kb
Host smart-3bf73fd9-391e-4b00-9eca-4580288cfb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488977482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.488977482
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2573840301
Short name T784
Test name
Test status
Simulation time 5879464711 ps
CPU time 15.44 seconds
Started Apr 25 01:14:01 PM PDT 24
Finished Apr 25 01:14:17 PM PDT 24
Peak memory 202136 kb
Host smart-1771fbdd-cb66-4052-9840-94159c31597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573840301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2573840301
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.360199009
Short name T48
Test name
Test status
Simulation time 534558962570 ps
CPU time 1519.75 seconds
Started Apr 25 01:14:09 PM PDT 24
Finished Apr 25 01:39:30 PM PDT 24
Peak memory 210868 kb
Host smart-188171fc-3f3a-4664-bee6-edbc80374ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360199009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
360199009
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3872766033
Short name T703
Test name
Test status
Simulation time 437418526 ps
CPU time 0.99 seconds
Started Apr 25 01:14:16 PM PDT 24
Finished Apr 25 01:14:18 PM PDT 24
Peak memory 202008 kb
Host smart-f381350d-3e91-41be-81c0-9a6d939f18b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872766033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3872766033
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1825524317
Short name T80
Test name
Test status
Simulation time 349452531767 ps
CPU time 812.22 seconds
Started Apr 25 01:14:10 PM PDT 24
Finished Apr 25 01:27:43 PM PDT 24
Peak memory 202384 kb
Host smart-a4fc2878-be8d-4253-a748-d0f8c4ba51c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825524317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1825524317
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2996445851
Short name T234
Test name
Test status
Simulation time 282667615437 ps
CPU time 179.86 seconds
Started Apr 25 01:14:11 PM PDT 24
Finished Apr 25 01:17:11 PM PDT 24
Peak memory 202252 kb
Host smart-57bc72ff-5e66-401b-934a-04567904c135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996445851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2996445851
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1590594411
Short name T231
Test name
Test status
Simulation time 329421156101 ps
CPU time 190.48 seconds
Started Apr 25 01:14:10 PM PDT 24
Finished Apr 25 01:17:21 PM PDT 24
Peak memory 202268 kb
Host smart-7c80d4ad-50db-4fee-8b48-f5ee37d9e032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590594411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1590594411
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3967548267
Short name T574
Test name
Test status
Simulation time 491593710380 ps
CPU time 155.25 seconds
Started Apr 25 01:14:10 PM PDT 24
Finished Apr 25 01:16:46 PM PDT 24
Peak memory 202284 kb
Host smart-2dc50b5d-6762-4718-952e-f346319fc1ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967548267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3967548267
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.644324372
Short name T422
Test name
Test status
Simulation time 323205888063 ps
CPU time 394.99 seconds
Started Apr 25 01:14:10 PM PDT 24
Finished Apr 25 01:20:46 PM PDT 24
Peak memory 202384 kb
Host smart-89c983aa-ad8c-441f-8270-fe77ca270bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644324372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.644324372
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3513897408
Short name T630
Test name
Test status
Simulation time 160378322572 ps
CPU time 234.86 seconds
Started Apr 25 01:14:13 PM PDT 24
Finished Apr 25 01:18:08 PM PDT 24
Peak memory 202288 kb
Host smart-abb1425d-ec6e-4cff-bd80-d5761464c8c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513897408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3513897408
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.379985007
Short name T427
Test name
Test status
Simulation time 395729405605 ps
CPU time 466.76 seconds
Started Apr 25 01:14:12 PM PDT 24
Finished Apr 25 01:21:59 PM PDT 24
Peak memory 202288 kb
Host smart-5537ab27-f3fe-4a9b-ad87-6d3933bb3e40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379985007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.379985007
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.386775666
Short name T450
Test name
Test status
Simulation time 137763348686 ps
CPU time 421.29 seconds
Started Apr 25 01:14:16 PM PDT 24
Finished Apr 25 01:21:18 PM PDT 24
Peak memory 202692 kb
Host smart-7921af9d-cb7c-415d-9f50-83b20664769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386775666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.386775666
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3361201853
Short name T749
Test name
Test status
Simulation time 31719579435 ps
CPU time 5.33 seconds
Started Apr 25 01:14:18 PM PDT 24
Finished Apr 25 01:14:24 PM PDT 24
Peak memory 202132 kb
Host smart-a7ab8f57-5a3b-42e4-a001-804310d84630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361201853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3361201853
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.753973529
Short name T434
Test name
Test status
Simulation time 5325294641 ps
CPU time 3.91 seconds
Started Apr 25 01:14:15 PM PDT 24
Finished Apr 25 01:14:19 PM PDT 24
Peak memory 202144 kb
Host smart-cf7887e9-9f32-405b-bbd7-07af30c5e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753973529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.753973529
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3067523949
Short name T356
Test name
Test status
Simulation time 5577586450 ps
CPU time 11.1 seconds
Started Apr 25 01:14:12 PM PDT 24
Finished Apr 25 01:14:23 PM PDT 24
Peak memory 202136 kb
Host smart-8017fe2a-7d8b-4e39-afef-70fe559044f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067523949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3067523949
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.863544183
Short name T30
Test name
Test status
Simulation time 197179528260 ps
CPU time 113.33 seconds
Started Apr 25 01:14:15 PM PDT 24
Finished Apr 25 01:16:09 PM PDT 24
Peak memory 202384 kb
Host smart-5de0116e-1ac4-4a30-b231-bd22035e4a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863544183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
863544183
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1013025717
Short name T370
Test name
Test status
Simulation time 383867598 ps
CPU time 0.83 seconds
Started Apr 25 01:14:27 PM PDT 24
Finished Apr 25 01:14:28 PM PDT 24
Peak memory 202000 kb
Host smart-634f21cb-8230-40e5-b86a-252e095572b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013025717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1013025717
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4066873853
Short name T692
Test name
Test status
Simulation time 160896172033 ps
CPU time 191.57 seconds
Started Apr 25 01:14:23 PM PDT 24
Finished Apr 25 01:17:35 PM PDT 24
Peak memory 202276 kb
Host smart-5d967c0a-8980-49b1-bd5a-f2d7127d8ce8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066873853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4066873853
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3595821538
Short name T229
Test name
Test status
Simulation time 165294632720 ps
CPU time 400.19 seconds
Started Apr 25 01:14:25 PM PDT 24
Finished Apr 25 01:21:06 PM PDT 24
Peak memory 202276 kb
Host smart-070d2d67-3547-444f-90c6-4973eb4c95ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595821538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3595821538
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2019757836
Short name T280
Test name
Test status
Simulation time 168963296327 ps
CPU time 190.61 seconds
Started Apr 25 01:14:15 PM PDT 24
Finished Apr 25 01:17:26 PM PDT 24
Peak memory 202364 kb
Host smart-a0c2c85c-3c55-4a5d-8e8a-578bece2404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019757836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2019757836
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1956103898
Short name T383
Test name
Test status
Simulation time 328691344541 ps
CPU time 92.49 seconds
Started Apr 25 01:14:23 PM PDT 24
Finished Apr 25 01:15:56 PM PDT 24
Peak memory 202308 kb
Host smart-daedd3ea-b405-4c10-816e-58e7b36cd035
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956103898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1956103898
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2503454168
Short name T731
Test name
Test status
Simulation time 156766410953 ps
CPU time 355.99 seconds
Started Apr 25 01:14:16 PM PDT 24
Finished Apr 25 01:20:12 PM PDT 24
Peak memory 202256 kb
Host smart-d2ec8e37-0a45-4464-a45d-8771daaffa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503454168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2503454168
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2127202199
Short name T639
Test name
Test status
Simulation time 164731300112 ps
CPU time 378.73 seconds
Started Apr 25 01:14:15 PM PDT 24
Finished Apr 25 01:20:35 PM PDT 24
Peak memory 202304 kb
Host smart-c5f8c2ac-a7c8-4f2f-9461-78ef0ade6c4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127202199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2127202199
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2430620743
Short name T600
Test name
Test status
Simulation time 570233346831 ps
CPU time 1360.27 seconds
Started Apr 25 01:14:21 PM PDT 24
Finished Apr 25 01:37:02 PM PDT 24
Peak memory 202372 kb
Host smart-e6da4cda-26b0-4a95-9ae2-db735ceb08fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430620743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2430620743
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1644408081
Short name T774
Test name
Test status
Simulation time 396724291225 ps
CPU time 465.37 seconds
Started Apr 25 01:14:22 PM PDT 24
Finished Apr 25 01:22:08 PM PDT 24
Peak memory 202212 kb
Host smart-0b988eba-b0bf-4212-9740-42b0512a4a7c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644408081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1644408081
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.934831423
Short name T8
Test name
Test status
Simulation time 98220958105 ps
CPU time 391.32 seconds
Started Apr 25 01:14:22 PM PDT 24
Finished Apr 25 01:20:54 PM PDT 24
Peak memory 202740 kb
Host smart-30c00adb-7c70-4b38-84f7-0f0398e07427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934831423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.934831423
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.502853610
Short name T85
Test name
Test status
Simulation time 21755424005 ps
CPU time 9.07 seconds
Started Apr 25 01:14:21 PM PDT 24
Finished Apr 25 01:14:30 PM PDT 24
Peak memory 202128 kb
Host smart-9f09cd78-1738-4b73-b45e-66ef1104eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502853610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.502853610
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2248060776
Short name T363
Test name
Test status
Simulation time 4749212824 ps
CPU time 11.13 seconds
Started Apr 25 01:14:23 PM PDT 24
Finished Apr 25 01:14:35 PM PDT 24
Peak memory 202128 kb
Host smart-d08fa6b8-0409-4c00-a658-af032715281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248060776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2248060776
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2910243810
Short name T695
Test name
Test status
Simulation time 5546072445 ps
CPU time 7.05 seconds
Started Apr 25 01:14:17 PM PDT 24
Finished Apr 25 01:14:24 PM PDT 24
Peak memory 202136 kb
Host smart-dbdccbd6-00a2-4b6a-9b97-cd769984403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910243810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2910243810
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3592129267
Short name T206
Test name
Test status
Simulation time 12412644544 ps
CPU time 29.99 seconds
Started Apr 25 01:14:27 PM PDT 24
Finished Apr 25 01:14:58 PM PDT 24
Peak memory 211048 kb
Host smart-9c7e7a22-c5aa-45f4-84ab-2290e72b5ef8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592129267 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3592129267
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1226146360
Short name T175
Test name
Test status
Simulation time 287350307 ps
CPU time 0.94 seconds
Started Apr 25 01:14:38 PM PDT 24
Finished Apr 25 01:14:40 PM PDT 24
Peak memory 201988 kb
Host smart-ba4fa5b2-6b36-4d8b-976f-26cde9a106c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226146360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1226146360
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.714702288
Short name T319
Test name
Test status
Simulation time 350377875868 ps
CPU time 855.12 seconds
Started Apr 25 01:14:34 PM PDT 24
Finished Apr 25 01:28:50 PM PDT 24
Peak memory 202316 kb
Host smart-e622e6f7-5bdf-4a3a-b9f8-87784b6d7bf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714702288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.714702288
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4291538688
Short name T521
Test name
Test status
Simulation time 169089113287 ps
CPU time 406.9 seconds
Started Apr 25 01:14:34 PM PDT 24
Finished Apr 25 01:21:22 PM PDT 24
Peak memory 202180 kb
Host smart-12b55763-d091-4544-898e-07c1d239e64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291538688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4291538688
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.134391493
Short name T326
Test name
Test status
Simulation time 491222198821 ps
CPU time 1070.32 seconds
Started Apr 25 01:14:26 PM PDT 24
Finished Apr 25 01:32:17 PM PDT 24
Peak memory 202244 kb
Host smart-474a294c-6f33-4d9d-8a88-f22f8206b25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134391493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.134391493
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3914915318
Short name T400
Test name
Test status
Simulation time 487511974220 ps
CPU time 123.49 seconds
Started Apr 25 01:14:27 PM PDT 24
Finished Apr 25 01:16:31 PM PDT 24
Peak memory 202276 kb
Host smart-2f4ffcd6-6112-483f-8acf-3c2adc97719d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914915318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3914915318
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.373750119
Short name T306
Test name
Test status
Simulation time 166731308944 ps
CPU time 373.01 seconds
Started Apr 25 01:14:30 PM PDT 24
Finished Apr 25 01:20:44 PM PDT 24
Peak memory 202276 kb
Host smart-4f362f08-1f20-47c3-9be5-0806fe3ff6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373750119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.373750119
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.702589674
Short name T495
Test name
Test status
Simulation time 487126734855 ps
CPU time 640 seconds
Started Apr 25 01:14:25 PM PDT 24
Finished Apr 25 01:25:06 PM PDT 24
Peak memory 202296 kb
Host smart-27535b6f-0a0b-4ed7-b08a-55df99036afd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=702589674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.702589674
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.564003276
Short name T671
Test name
Test status
Simulation time 386542417851 ps
CPU time 865.38 seconds
Started Apr 25 01:14:28 PM PDT 24
Finished Apr 25 01:28:54 PM PDT 24
Peak memory 202280 kb
Host smart-9ac8797c-df3d-4a22-a998-5b894fd8d40b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564003276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.564003276
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1959324613
Short name T472
Test name
Test status
Simulation time 403602359114 ps
CPU time 722.48 seconds
Started Apr 25 01:14:33 PM PDT 24
Finished Apr 25 01:26:36 PM PDT 24
Peak memory 202288 kb
Host smart-b46a0e12-92cb-4e06-bc54-eea673dd80ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959324613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1959324613
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3865172206
Short name T46
Test name
Test status
Simulation time 141267084734 ps
CPU time 439.28 seconds
Started Apr 25 01:14:32 PM PDT 24
Finished Apr 25 01:21:52 PM PDT 24
Peak memory 202672 kb
Host smart-ab299091-d40f-462a-99ed-68f721990076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865172206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3865172206
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1674867349
Short name T501
Test name
Test status
Simulation time 43385893356 ps
CPU time 101.41 seconds
Started Apr 25 01:14:34 PM PDT 24
Finished Apr 25 01:16:16 PM PDT 24
Peak memory 202108 kb
Host smart-713d530d-a272-42b4-95e5-e6db35444181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674867349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1674867349
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.510810745
Short name T745
Test name
Test status
Simulation time 3924260923 ps
CPU time 8.99 seconds
Started Apr 25 01:14:35 PM PDT 24
Finished Apr 25 01:14:45 PM PDT 24
Peak memory 202088 kb
Host smart-22002d65-e7d0-4bce-81cd-142c7516fe81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510810745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.510810745
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1954068065
Short name T488
Test name
Test status
Simulation time 5840429419 ps
CPU time 2.69 seconds
Started Apr 25 01:14:26 PM PDT 24
Finished Apr 25 01:14:29 PM PDT 24
Peak memory 202128 kb
Host smart-f74443c7-4ee4-4ea9-83ef-8309999aa5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954068065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1954068065
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3764124132
Short name T554
Test name
Test status
Simulation time 427210727 ps
CPU time 0.91 seconds
Started Apr 25 01:12:54 PM PDT 24
Finished Apr 25 01:12:55 PM PDT 24
Peak memory 201988 kb
Host smart-04d5a04b-3bb4-4254-94b1-bf306d1e8abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764124132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3764124132
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3217399867
Short name T135
Test name
Test status
Simulation time 489329938585 ps
CPU time 288.92 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:17:42 PM PDT 24
Peak memory 202324 kb
Host smart-932bc711-3a0a-49d6-8a9d-07e55f8b0d33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217399867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3217399867
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2760514888
Short name T729
Test name
Test status
Simulation time 162965387774 ps
CPU time 96.5 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:14:29 PM PDT 24
Peak memory 202388 kb
Host smart-ec3118d2-1480-4249-9780-77b370253a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760514888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2760514888
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3785523791
Short name T657
Test name
Test status
Simulation time 328495881902 ps
CPU time 809.52 seconds
Started Apr 25 01:12:50 PM PDT 24
Finished Apr 25 01:26:20 PM PDT 24
Peak memory 202296 kb
Host smart-cef8c792-9a18-4802-91a3-41d0897d05a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785523791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3785523791
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1926191807
Short name T624
Test name
Test status
Simulation time 498137088157 ps
CPU time 324.42 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:18:18 PM PDT 24
Peak memory 202288 kb
Host smart-2b584606-8945-49ff-ad94-86df1559117d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926191807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1926191807
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.801036203
Short name T305
Test name
Test status
Simulation time 164789228068 ps
CPU time 35.89 seconds
Started Apr 25 01:12:55 PM PDT 24
Finished Apr 25 01:13:32 PM PDT 24
Peak memory 202304 kb
Host smart-c01bc706-a362-434e-b631-4264b1871412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801036203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.801036203
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3564111470
Short name T513
Test name
Test status
Simulation time 494598327204 ps
CPU time 316.98 seconds
Started Apr 25 01:12:55 PM PDT 24
Finished Apr 25 01:18:13 PM PDT 24
Peak memory 202364 kb
Host smart-fc8322c8-1cc9-4d1a-8227-5f1482fae192
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564111470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3564111470
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.898545306
Short name T258
Test name
Test status
Simulation time 547009682414 ps
CPU time 593.88 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:22:46 PM PDT 24
Peak memory 202344 kb
Host smart-8ab6ad04-172d-44e4-9084-252950e5da27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898545306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.898545306
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1835122123
Short name T618
Test name
Test status
Simulation time 595533781575 ps
CPU time 1291.31 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:34:24 PM PDT 24
Peak memory 202300 kb
Host smart-635a3ab0-828f-4e07-95e1-2094c77ab14e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835122123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1835122123
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2516991769
Short name T615
Test name
Test status
Simulation time 99975217612 ps
CPU time 545.17 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:21:58 PM PDT 24
Peak memory 202604 kb
Host smart-daee5440-2712-4299-8572-e3c69a9b6e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516991769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2516991769
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.35097383
Short name T437
Test name
Test status
Simulation time 26395594265 ps
CPU time 59.9 seconds
Started Apr 25 01:12:52 PM PDT 24
Finished Apr 25 01:13:53 PM PDT 24
Peak memory 202016 kb
Host smart-271d9440-0d16-414b-94e3-38cf81cceec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35097383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.35097383
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.948827443
Short name T648
Test name
Test status
Simulation time 4521815082 ps
CPU time 3.31 seconds
Started Apr 25 01:12:51 PM PDT 24
Finished Apr 25 01:12:55 PM PDT 24
Peak memory 202140 kb
Host smart-db028f56-0987-4aca-b1d4-5b3e98e6cbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948827443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.948827443
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.313111119
Short name T72
Test name
Test status
Simulation time 4406947281 ps
CPU time 5.44 seconds
Started Apr 25 01:12:51 PM PDT 24
Finished Apr 25 01:12:57 PM PDT 24
Peak memory 217692 kb
Host smart-62cc062a-4b6d-4dba-9915-948fb7d142d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313111119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.313111119
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2743971242
Short name T505
Test name
Test status
Simulation time 5954678896 ps
CPU time 7.94 seconds
Started Apr 25 01:12:53 PM PDT 24
Finished Apr 25 01:13:02 PM PDT 24
Peak memory 202104 kb
Host smart-cc0c9097-2ae9-442b-927b-4c10cb40c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743971242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2743971242
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2636337073
Short name T572
Test name
Test status
Simulation time 1290971616 ps
CPU time 1.5 seconds
Started Apr 25 01:12:54 PM PDT 24
Finished Apr 25 01:12:56 PM PDT 24
Peak memory 202020 kb
Host smart-ef9bf76b-7531-4f71-bb92-7c66c49e4482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636337073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2636337073
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3986887746
Short name T37
Test name
Test status
Simulation time 131749600923 ps
CPU time 227.36 seconds
Started Apr 25 01:12:51 PM PDT 24
Finished Apr 25 01:16:40 PM PDT 24
Peak memory 211244 kb
Host smart-368de6ab-a903-466b-93a6-bfabff08f702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986887746 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3986887746
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3677162419
Short name T530
Test name
Test status
Simulation time 450753791 ps
CPU time 0.72 seconds
Started Apr 25 01:14:56 PM PDT 24
Finished Apr 25 01:14:58 PM PDT 24
Peak memory 202000 kb
Host smart-48f42cb0-6d94-4bf2-95d5-3e9ce21d3c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677162419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3677162419
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2893074182
Short name T184
Test name
Test status
Simulation time 529133737870 ps
CPU time 1210.19 seconds
Started Apr 25 01:14:57 PM PDT 24
Finished Apr 25 01:35:08 PM PDT 24
Peak memory 202312 kb
Host smart-1b4bfc66-ea1c-4342-ba84-880d8e7ba72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893074182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2893074182
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3151184557
Short name T276
Test name
Test status
Simulation time 508668531982 ps
CPU time 324.49 seconds
Started Apr 25 01:14:44 PM PDT 24
Finished Apr 25 01:20:09 PM PDT 24
Peak memory 202236 kb
Host smart-6e301e98-caf7-445a-b3d3-bd28f7cf7e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151184557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3151184557
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1404200908
Short name T617
Test name
Test status
Simulation time 328464058444 ps
CPU time 688.68 seconds
Started Apr 25 01:14:40 PM PDT 24
Finished Apr 25 01:26:10 PM PDT 24
Peak memory 202404 kb
Host smart-4ed002e0-d2d8-430e-99fc-59a67b7644ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404200908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1404200908
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1391780640
Short name T621
Test name
Test status
Simulation time 160196534833 ps
CPU time 358.08 seconds
Started Apr 25 01:14:42 PM PDT 24
Finished Apr 25 01:20:40 PM PDT 24
Peak memory 202276 kb
Host smart-18a00ece-9b61-42d5-b361-c47308e7ac7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391780640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1391780640
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.404612923
Short name T768
Test name
Test status
Simulation time 177857001972 ps
CPU time 405.33 seconds
Started Apr 25 01:14:51 PM PDT 24
Finished Apr 25 01:21:36 PM PDT 24
Peak memory 202352 kb
Host smart-f996880c-775b-4a00-a13f-01366e80d5c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404612923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.404612923
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.176494787
Short name T776
Test name
Test status
Simulation time 629553203691 ps
CPU time 725.98 seconds
Started Apr 25 01:14:52 PM PDT 24
Finished Apr 25 01:26:58 PM PDT 24
Peak memory 202372 kb
Host smart-dc8613d3-698f-4232-882b-c7d61bf01d1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176494787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.176494787
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3080639968
Short name T567
Test name
Test status
Simulation time 73533023553 ps
CPU time 243.59 seconds
Started Apr 25 01:14:58 PM PDT 24
Finished Apr 25 01:19:02 PM PDT 24
Peak memory 202736 kb
Host smart-0c3584c6-0610-435b-af94-5a789b97df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080639968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3080639968
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1117005676
Short name T693
Test name
Test status
Simulation time 46868669511 ps
CPU time 28.29 seconds
Started Apr 25 01:14:58 PM PDT 24
Finished Apr 25 01:15:27 PM PDT 24
Peak memory 202132 kb
Host smart-16df2ba9-efcd-45e1-b8cc-2f68fc812736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117005676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1117005676
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2898770468
Short name T534
Test name
Test status
Simulation time 4566739555 ps
CPU time 11.77 seconds
Started Apr 25 01:15:00 PM PDT 24
Finished Apr 25 01:15:12 PM PDT 24
Peak memory 202136 kb
Host smart-96d6a795-0edd-40f6-830c-d2cabaa33af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898770468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2898770468
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2290686560
Short name T373
Test name
Test status
Simulation time 5539500086 ps
CPU time 6.54 seconds
Started Apr 25 01:14:37 PM PDT 24
Finished Apr 25 01:14:45 PM PDT 24
Peak memory 202136 kb
Host smart-c67235b6-f005-461b-b6ba-e6bbaa59b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290686560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2290686560
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1430407662
Short name T301
Test name
Test status
Simulation time 60035245881 ps
CPU time 131.62 seconds
Started Apr 25 01:14:59 PM PDT 24
Finished Apr 25 01:17:11 PM PDT 24
Peak memory 219136 kb
Host smart-8716ec56-dd39-4740-a862-d76f399448e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430407662 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1430407662
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4273287625
Short name T362
Test name
Test status
Simulation time 534682922 ps
CPU time 0.83 seconds
Started Apr 25 01:15:06 PM PDT 24
Finished Apr 25 01:15:08 PM PDT 24
Peak memory 201992 kb
Host smart-b91d1c10-55e5-4e5a-a64c-0e0fa8d2bb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273287625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4273287625
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.379321569
Short name T188
Test name
Test status
Simulation time 518219927661 ps
CPU time 293.42 seconds
Started Apr 25 01:15:07 PM PDT 24
Finished Apr 25 01:20:01 PM PDT 24
Peak memory 202388 kb
Host smart-afffdebc-9b3c-4df4-876e-8bded1e8c6bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379321569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.379321569
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3803739553
Short name T765
Test name
Test status
Simulation time 492986760660 ps
CPU time 1171.44 seconds
Started Apr 25 01:15:05 PM PDT 24
Finished Apr 25 01:34:37 PM PDT 24
Peak memory 202316 kb
Host smart-cc8998a8-07da-4cab-99c0-d46bdb798699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803739553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3803739553
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2184574204
Short name T261
Test name
Test status
Simulation time 329681496514 ps
CPU time 799.3 seconds
Started Apr 25 01:15:01 PM PDT 24
Finished Apr 25 01:28:21 PM PDT 24
Peak memory 202380 kb
Host smart-23948097-3c47-42fb-b62a-ebd6bcc8d287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184574204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2184574204
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1333786502
Short name T425
Test name
Test status
Simulation time 336367172669 ps
CPU time 777.24 seconds
Started Apr 25 01:15:01 PM PDT 24
Finished Apr 25 01:27:59 PM PDT 24
Peak memory 202280 kb
Host smart-2ff55463-c500-4618-848d-08d05590e578
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333786502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1333786502
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.297424345
Short name T323
Test name
Test status
Simulation time 162245974308 ps
CPU time 175.62 seconds
Started Apr 25 01:14:58 PM PDT 24
Finished Apr 25 01:17:54 PM PDT 24
Peak memory 202304 kb
Host smart-cc2b7de7-85d1-4f7f-a4be-f9ad90d7b2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297424345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.297424345
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3547649199
Short name T673
Test name
Test status
Simulation time 491290582997 ps
CPU time 1107.44 seconds
Started Apr 25 01:14:57 PM PDT 24
Finished Apr 25 01:33:25 PM PDT 24
Peak memory 202356 kb
Host smart-9ec76b7b-b61e-4757-a271-f888e8296a7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547649199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3547649199
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.309717906
Short name T25
Test name
Test status
Simulation time 620325768955 ps
CPU time 265.74 seconds
Started Apr 25 01:15:05 PM PDT 24
Finished Apr 25 01:19:31 PM PDT 24
Peak memory 202324 kb
Host smart-cf1efcbb-6573-460e-a744-002bc72c7978
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309717906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.309717906
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3155925105
Short name T594
Test name
Test status
Simulation time 414389012977 ps
CPU time 1011.95 seconds
Started Apr 25 01:15:03 PM PDT 24
Finished Apr 25 01:31:55 PM PDT 24
Peak memory 202292 kb
Host smart-ace7ffc0-d6b5-4277-bd15-acba3b99ce00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155925105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3155925105
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1788225700
Short name T540
Test name
Test status
Simulation time 92140510083 ps
CPU time 504.44 seconds
Started Apr 25 01:15:10 PM PDT 24
Finished Apr 25 01:23:35 PM PDT 24
Peak memory 202636 kb
Host smart-183f3b6d-b996-4381-b83c-265967904832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788225700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1788225700
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3602841570
Short name T379
Test name
Test status
Simulation time 26593245628 ps
CPU time 17.12 seconds
Started Apr 25 01:15:05 PM PDT 24
Finished Apr 25 01:15:23 PM PDT 24
Peak memory 202076 kb
Host smart-602acb99-8edf-4ab1-8c84-167aa139068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602841570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3602841570
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4228556882
Short name T484
Test name
Test status
Simulation time 3457810732 ps
CPU time 9.67 seconds
Started Apr 25 01:15:04 PM PDT 24
Finished Apr 25 01:15:14 PM PDT 24
Peak memory 202148 kb
Host smart-f38368b5-f5ac-42ba-8bb0-cb913a2f61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228556882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4228556882
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.4171316258
Short name T116
Test name
Test status
Simulation time 5877683080 ps
CPU time 4.09 seconds
Started Apr 25 01:14:57 PM PDT 24
Finished Apr 25 01:15:02 PM PDT 24
Peak memory 202132 kb
Host smart-06263628-ee1f-4ca4-bb3a-1cb32fc01e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171316258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.4171316258
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3433366834
Short name T632
Test name
Test status
Simulation time 289091997618 ps
CPU time 449.79 seconds
Started Apr 25 01:15:08 PM PDT 24
Finished Apr 25 01:22:38 PM PDT 24
Peak memory 210880 kb
Host smart-9f119773-2442-4863-9ecc-3c9142693544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433366834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3433366834
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3377845606
Short name T217
Test name
Test status
Simulation time 887208477086 ps
CPU time 147.39 seconds
Started Apr 25 01:15:08 PM PDT 24
Finished Apr 25 01:17:36 PM PDT 24
Peak memory 202448 kb
Host smart-da4f8cd3-fd99-4920-9c35-137a21646c6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377845606 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3377845606
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1944154099
Short name T372
Test name
Test status
Simulation time 391934978 ps
CPU time 0.85 seconds
Started Apr 25 01:15:17 PM PDT 24
Finished Apr 25 01:15:19 PM PDT 24
Peak memory 201908 kb
Host smart-bfff5298-a821-4f55-a240-578110946a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944154099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1944154099
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1935356962
Short name T754
Test name
Test status
Simulation time 163217042775 ps
CPU time 62.97 seconds
Started Apr 25 01:15:24 PM PDT 24
Finished Apr 25 01:16:28 PM PDT 24
Peak memory 202252 kb
Host smart-faabfdaa-2b77-48ae-9c3a-015251eaeb6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935356962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1935356962
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1539530583
Short name T690
Test name
Test status
Simulation time 168051930259 ps
CPU time 354.93 seconds
Started Apr 25 01:15:14 PM PDT 24
Finished Apr 25 01:21:09 PM PDT 24
Peak memory 202364 kb
Host smart-f5a1bae7-2c62-4ca0-987a-de79053ee652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539530583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1539530583
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2397998155
Short name T83
Test name
Test status
Simulation time 491960158214 ps
CPU time 1065.53 seconds
Started Apr 25 01:15:12 PM PDT 24
Finished Apr 25 01:32:59 PM PDT 24
Peak memory 202312 kb
Host smart-4c763382-4bdc-41fc-8827-08cf6fb61788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397998155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2397998155
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2927996432
Short name T662
Test name
Test status
Simulation time 486822935876 ps
CPU time 144.91 seconds
Started Apr 25 01:15:13 PM PDT 24
Finished Apr 25 01:17:39 PM PDT 24
Peak memory 202320 kb
Host smart-61a762f7-8725-4ca3-89dc-dc3dff6c83ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927996432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2927996432
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3557663643
Short name T443
Test name
Test status
Simulation time 321017639135 ps
CPU time 172.85 seconds
Started Apr 25 01:15:13 PM PDT 24
Finished Apr 25 01:18:07 PM PDT 24
Peak memory 202288 kb
Host smart-0533ddb7-5125-4096-85ed-739959f48e14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557663643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3557663643
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1704663115
Short name T42
Test name
Test status
Simulation time 346021391376 ps
CPU time 792.7 seconds
Started Apr 25 01:15:14 PM PDT 24
Finished Apr 25 01:28:28 PM PDT 24
Peak memory 202312 kb
Host smart-bb25bb67-fd2c-43f7-8dba-598a32f1ecaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704663115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1704663115
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2928438779
Short name T402
Test name
Test status
Simulation time 396575863694 ps
CPU time 417.93 seconds
Started Apr 25 01:15:16 PM PDT 24
Finished Apr 25 01:22:15 PM PDT 24
Peak memory 202372 kb
Host smart-cf6979b0-291e-4c02-b0fa-7ee87f97a422
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928438779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2928438779
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1869820015
Short name T44
Test name
Test status
Simulation time 132212871075 ps
CPU time 418.57 seconds
Started Apr 25 01:15:19 PM PDT 24
Finished Apr 25 01:22:18 PM PDT 24
Peak memory 202660 kb
Host smart-a1124bb4-7fa0-4284-90ec-2019e2b9c510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869820015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1869820015
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2316637672
Short name T672
Test name
Test status
Simulation time 25149982550 ps
CPU time 31.88 seconds
Started Apr 25 01:15:18 PM PDT 24
Finished Apr 25 01:15:51 PM PDT 24
Peak memory 202116 kb
Host smart-9fa0efe4-2906-4ec5-9dd1-3a391c42fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316637672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2316637672
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2426895940
Short name T368
Test name
Test status
Simulation time 3509993008 ps
CPU time 8.95 seconds
Started Apr 25 01:15:20 PM PDT 24
Finished Apr 25 01:15:30 PM PDT 24
Peak memory 202124 kb
Host smart-2fabbf52-b8c2-4e39-a516-7c54784c2910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426895940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2426895940
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.501496759
Short name T352
Test name
Test status
Simulation time 5745686096 ps
CPU time 15.63 seconds
Started Apr 25 01:15:08 PM PDT 24
Finished Apr 25 01:15:25 PM PDT 24
Peak memory 202136 kb
Host smart-c22cc89c-0f5a-4070-9470-1e22ef37e570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501496759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.501496759
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1137995781
Short name T790
Test name
Test status
Simulation time 176596825243 ps
CPU time 684.08 seconds
Started Apr 25 01:15:21 PM PDT 24
Finished Apr 25 01:26:46 PM PDT 24
Peak memory 202676 kb
Host smart-79d89a60-3031-485a-b443-eeed27890a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137995781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1137995781
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1655399034
Short name T777
Test name
Test status
Simulation time 549820232790 ps
CPU time 444.19 seconds
Started Apr 25 01:15:18 PM PDT 24
Finished Apr 25 01:22:43 PM PDT 24
Peak memory 211100 kb
Host smart-1dfbeb2e-60ff-4cac-bc81-91e8f389ea19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655399034 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1655399034
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4118280460
Short name T660
Test name
Test status
Simulation time 518683824 ps
CPU time 0.92 seconds
Started Apr 25 01:15:48 PM PDT 24
Finished Apr 25 01:15:50 PM PDT 24
Peak memory 201968 kb
Host smart-dca3d197-ee02-4a7c-9e73-184db97b4f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118280460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4118280460
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2661027264
Short name T233
Test name
Test status
Simulation time 166721073973 ps
CPU time 282.56 seconds
Started Apr 25 01:15:37 PM PDT 24
Finished Apr 25 01:20:20 PM PDT 24
Peak memory 202324 kb
Host smart-98484e87-9d47-41dc-9a3f-d9aaaddbccfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661027264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2661027264
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3264066244
Short name T136
Test name
Test status
Simulation time 505768262176 ps
CPU time 703.03 seconds
Started Apr 25 01:15:43 PM PDT 24
Finished Apr 25 01:27:27 PM PDT 24
Peak memory 202272 kb
Host smart-5ca6db77-fcea-4ac7-abb5-5dd32d1197ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264066244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3264066244
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3516126115
Short name T159
Test name
Test status
Simulation time 488584619987 ps
CPU time 277.02 seconds
Started Apr 25 01:15:31 PM PDT 24
Finished Apr 25 01:20:08 PM PDT 24
Peak memory 202196 kb
Host smart-6c2aec97-a643-457f-af35-cf400624a7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516126115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3516126115
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1672447918
Short name T436
Test name
Test status
Simulation time 170342708855 ps
CPU time 366.93 seconds
Started Apr 25 01:15:28 PM PDT 24
Finished Apr 25 01:21:36 PM PDT 24
Peak memory 202284 kb
Host smart-75b7d679-9c03-41ee-876f-5c26ef473fab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672447918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1672447918
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3990398004
Short name T767
Test name
Test status
Simulation time 334263306102 ps
CPU time 205.22 seconds
Started Apr 25 01:15:25 PM PDT 24
Finished Apr 25 01:18:51 PM PDT 24
Peak memory 202308 kb
Host smart-85d9d537-2dba-4566-8569-1c6a38eb00cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990398004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3990398004
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3500397072
Short name T627
Test name
Test status
Simulation time 167844954238 ps
CPU time 204.37 seconds
Started Apr 25 01:15:29 PM PDT 24
Finished Apr 25 01:18:54 PM PDT 24
Peak memory 202220 kb
Host smart-37668c3b-337e-4764-b3d4-d9d7ae8dcad9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500397072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3500397072
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1997424889
Short name T145
Test name
Test status
Simulation time 217550473236 ps
CPU time 485.59 seconds
Started Apr 25 01:15:30 PM PDT 24
Finished Apr 25 01:23:36 PM PDT 24
Peak memory 202308 kb
Host smart-22dc03d0-3be5-4418-881b-0b0fc353fa32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997424889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1997424889
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1038771490
Short name T465
Test name
Test status
Simulation time 390244231726 ps
CPU time 931.94 seconds
Started Apr 25 01:15:30 PM PDT 24
Finished Apr 25 01:31:03 PM PDT 24
Peak memory 202168 kb
Host smart-11b9f671-f7d1-4909-8ebe-ba553985d48a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038771490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1038771490
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2393406183
Short name T603
Test name
Test status
Simulation time 134035709868 ps
CPU time 473.05 seconds
Started Apr 25 01:15:37 PM PDT 24
Finished Apr 25 01:23:31 PM PDT 24
Peak memory 202688 kb
Host smart-48cd0c01-5b79-48bb-a008-1debe4d37cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393406183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2393406183
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.4282698525
Short name T609
Test name
Test status
Simulation time 24602129990 ps
CPU time 22.02 seconds
Started Apr 25 01:15:44 PM PDT 24
Finished Apr 25 01:16:06 PM PDT 24
Peak memory 202084 kb
Host smart-979ea98e-dc05-4659-999c-19ea62c20662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282698525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.4282698525
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3197576160
Short name T43
Test name
Test status
Simulation time 4747980948 ps
CPU time 11.27 seconds
Started Apr 25 01:15:37 PM PDT 24
Finished Apr 25 01:15:48 PM PDT 24
Peak memory 202104 kb
Host smart-7620b139-d590-4986-8802-b8e400b9d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197576160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3197576160
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.907946934
Short name T464
Test name
Test status
Simulation time 5868206933 ps
CPU time 6.37 seconds
Started Apr 25 01:15:18 PM PDT 24
Finished Apr 25 01:15:26 PM PDT 24
Peak memory 202052 kb
Host smart-3bb0ac5a-0a7d-46dd-b483-56fee971a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907946934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.907946934
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3963717517
Short name T318
Test name
Test status
Simulation time 162549370936 ps
CPU time 193.5 seconds
Started Apr 25 01:15:42 PM PDT 24
Finished Apr 25 01:18:57 PM PDT 24
Peak memory 202380 kb
Host smart-49c3775e-26fa-4696-9463-931779414093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963717517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3963717517
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.749382026
Short name T633
Test name
Test status
Simulation time 235393260364 ps
CPU time 111.31 seconds
Started Apr 25 01:15:35 PM PDT 24
Finished Apr 25 01:17:27 PM PDT 24
Peak memory 213380 kb
Host smart-c24af8ce-92ed-48f7-a911-cb15945fc102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749382026 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.749382026
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.510582118
Short name T417
Test name
Test status
Simulation time 510420723 ps
CPU time 0.9 seconds
Started Apr 25 01:15:56 PM PDT 24
Finished Apr 25 01:15:57 PM PDT 24
Peak memory 201996 kb
Host smart-242402bd-0c64-4ae8-85b5-6ac11ecf543c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510582118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.510582118
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2798563109
Short name T691
Test name
Test status
Simulation time 158549957829 ps
CPU time 102.82 seconds
Started Apr 25 01:16:18 PM PDT 24
Finished Apr 25 01:18:01 PM PDT 24
Peak memory 202308 kb
Host smart-60111c54-71e5-49ff-a066-31837e8b084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798563109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2798563109
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3763154392
Short name T249
Test name
Test status
Simulation time 328516906494 ps
CPU time 179.69 seconds
Started Apr 25 01:15:46 PM PDT 24
Finished Apr 25 01:18:46 PM PDT 24
Peak memory 202388 kb
Host smart-b278bad8-b37d-4825-a413-9a1d927de6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763154392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3763154392
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.417813284
Short name T536
Test name
Test status
Simulation time 492038878902 ps
CPU time 1202.12 seconds
Started Apr 25 01:15:46 PM PDT 24
Finished Apr 25 01:35:48 PM PDT 24
Peak memory 202304 kb
Host smart-18b1fac2-d3bd-4793-885b-86e95e746b64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=417813284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.417813284
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.882170133
Short name T329
Test name
Test status
Simulation time 482241950292 ps
CPU time 599.82 seconds
Started Apr 25 01:15:46 PM PDT 24
Finished Apr 25 01:25:46 PM PDT 24
Peak memory 202308 kb
Host smart-32a0339a-0df5-4ab2-9776-4c137367661e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882170133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.882170133
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2884548963
Short name T727
Test name
Test status
Simulation time 170965035546 ps
CPU time 396.21 seconds
Started Apr 25 01:15:46 PM PDT 24
Finished Apr 25 01:22:22 PM PDT 24
Peak memory 202280 kb
Host smart-fbc3321f-a944-49fc-94dc-24fca3025d8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884548963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2884548963
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.716051925
Short name T271
Test name
Test status
Simulation time 358636960222 ps
CPU time 816.82 seconds
Started Apr 25 01:15:48 PM PDT 24
Finished Apr 25 01:29:26 PM PDT 24
Peak memory 202272 kb
Host smart-7a519970-5cb1-428a-a0e7-ac2d0a3a5875
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716051925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.716051925
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.417994963
Short name T420
Test name
Test status
Simulation time 384727918627 ps
CPU time 139.49 seconds
Started Apr 25 01:15:50 PM PDT 24
Finished Apr 25 01:18:10 PM PDT 24
Peak memory 202292 kb
Host smart-c6478cab-fddc-4be2-832e-4676bf8273c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417994963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.417994963
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1292316005
Short name T200
Test name
Test status
Simulation time 95477714961 ps
CPU time 511.21 seconds
Started Apr 25 01:15:56 PM PDT 24
Finished Apr 25 01:24:28 PM PDT 24
Peak memory 202664 kb
Host smart-b7c3beb4-9e1d-417a-a2fc-454dd5d8956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292316005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1292316005
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.352148132
Short name T591
Test name
Test status
Simulation time 33356899989 ps
CPU time 80.47 seconds
Started Apr 25 01:15:53 PM PDT 24
Finished Apr 25 01:17:14 PM PDT 24
Peak memory 202132 kb
Host smart-7e4f7051-0a16-49f1-9ea5-09e68443c9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352148132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.352148132
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.232438976
Short name T616
Test name
Test status
Simulation time 3654254657 ps
CPU time 8.66 seconds
Started Apr 25 01:15:51 PM PDT 24
Finished Apr 25 01:16:00 PM PDT 24
Peak memory 202156 kb
Host smart-65b68460-2176-4fe1-9183-f21aa5b52756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232438976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.232438976
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2995977524
Short name T350
Test name
Test status
Simulation time 5697510889 ps
CPU time 7.11 seconds
Started Apr 25 01:15:49 PM PDT 24
Finished Apr 25 01:15:57 PM PDT 24
Peak memory 202044 kb
Host smart-0ac59507-93fa-41a3-90e9-a9f5a456f790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995977524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2995977524
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.263077607
Short name T758
Test name
Test status
Simulation time 335723448224 ps
CPU time 165.08 seconds
Started Apr 25 01:15:56 PM PDT 24
Finished Apr 25 01:18:42 PM PDT 24
Peak memory 202304 kb
Host smart-cf09159e-9b81-40da-8227-9f73c5dff6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263077607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
263077607
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1885556976
Short name T309
Test name
Test status
Simulation time 250686307076 ps
CPU time 376.6 seconds
Started Apr 25 01:15:56 PM PDT 24
Finished Apr 25 01:22:13 PM PDT 24
Peak memory 211028 kb
Host smart-e1840b9d-9b75-4877-8ebf-eb2b01fd016a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885556976 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1885556976
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3392344824
Short name T508
Test name
Test status
Simulation time 327506731 ps
CPU time 1 seconds
Started Apr 25 01:16:07 PM PDT 24
Finished Apr 25 01:16:09 PM PDT 24
Peak memory 201944 kb
Host smart-22ea2947-8bfa-4974-a186-d173a797acdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392344824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3392344824
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2321087196
Short name T223
Test name
Test status
Simulation time 448854783441 ps
CPU time 503.91 seconds
Started Apr 25 01:16:06 PM PDT 24
Finished Apr 25 01:24:30 PM PDT 24
Peak memory 202328 kb
Host smart-9391aeb9-1395-4634-9f95-55392e30b8c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321087196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2321087196
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2133735775
Short name T302
Test name
Test status
Simulation time 322564142866 ps
CPU time 753.07 seconds
Started Apr 25 01:15:58 PM PDT 24
Finished Apr 25 01:28:31 PM PDT 24
Peak memory 202324 kb
Host smart-aa937733-2751-4787-87d4-5de7938b124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133735775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2133735775
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1906999646
Short name T582
Test name
Test status
Simulation time 162168496404 ps
CPU time 73.04 seconds
Started Apr 25 01:16:05 PM PDT 24
Finished Apr 25 01:17:18 PM PDT 24
Peak memory 202208 kb
Host smart-fe27698b-4c4e-4269-85e0-4dadae769721
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906999646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1906999646
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1372163237
Short name T180
Test name
Test status
Simulation time 168283476857 ps
CPU time 87.57 seconds
Started Apr 25 01:15:58 PM PDT 24
Finished Apr 25 01:17:26 PM PDT 24
Peak memory 202260 kb
Host smart-d7b85171-6c8b-4385-b1b9-3b24d4007d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372163237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1372163237
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1345723736
Short name T155
Test name
Test status
Simulation time 483380275881 ps
CPU time 309.23 seconds
Started Apr 25 01:15:57 PM PDT 24
Finished Apr 25 01:21:07 PM PDT 24
Peak memory 202252 kb
Host smart-15bd15b6-5fbf-445c-967f-174894acf5d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345723736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1345723736
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3191123622
Short name T268
Test name
Test status
Simulation time 273233424430 ps
CPU time 567.13 seconds
Started Apr 25 01:16:02 PM PDT 24
Finished Apr 25 01:25:30 PM PDT 24
Peak memory 202308 kb
Host smart-9b31b4ca-3085-4923-ab2f-73eaa2e95f10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191123622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3191123622
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2765875880
Short name T84
Test name
Test status
Simulation time 202152412115 ps
CPU time 478.07 seconds
Started Apr 25 01:16:11 PM PDT 24
Finished Apr 25 01:24:09 PM PDT 24
Peak memory 202356 kb
Host smart-d350651d-b717-452a-b8ce-22f05f6bd389
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765875880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2765875880
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2557553741
Short name T625
Test name
Test status
Simulation time 124432852039 ps
CPU time 492.63 seconds
Started Apr 25 01:16:01 PM PDT 24
Finished Apr 25 01:24:14 PM PDT 24
Peak memory 202660 kb
Host smart-8c3bba05-7395-4e1b-bb2d-eb3653bfe539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557553741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2557553741
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1666115220
Short name T449
Test name
Test status
Simulation time 47309311040 ps
CPU time 34.72 seconds
Started Apr 25 01:16:03 PM PDT 24
Finished Apr 25 01:16:38 PM PDT 24
Peak memory 202144 kb
Host smart-8d467ee3-9e8f-47a3-8b50-24392b8b47b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666115220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1666115220
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3442580839
Short name T589
Test name
Test status
Simulation time 5482775287 ps
CPU time 2.08 seconds
Started Apr 25 01:16:04 PM PDT 24
Finished Apr 25 01:16:06 PM PDT 24
Peak memory 202120 kb
Host smart-05022037-bb3f-4034-82e4-e2ad2994352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442580839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3442580839
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2630043744
Short name T658
Test name
Test status
Simulation time 6034236540 ps
CPU time 7.1 seconds
Started Apr 25 01:16:10 PM PDT 24
Finished Apr 25 01:16:18 PM PDT 24
Peak memory 202068 kb
Host smart-b1a20d3e-e69f-4f01-b74d-101c6d3f8cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630043744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2630043744
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3168691532
Short name T751
Test name
Test status
Simulation time 121168754678 ps
CPU time 321.41 seconds
Started Apr 25 01:16:03 PM PDT 24
Finished Apr 25 01:21:25 PM PDT 24
Peak memory 218336 kb
Host smart-c7b2bb9b-f396-4591-be9f-4fe4c786ba14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168691532 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3168691532
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.399172244
Short name T27
Test name
Test status
Simulation time 485683690 ps
CPU time 1.17 seconds
Started Apr 25 01:16:31 PM PDT 24
Finished Apr 25 01:16:32 PM PDT 24
Peak memory 202020 kb
Host smart-256c44ca-c6a5-45ba-be0e-6d763e74b310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399172244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.399172244
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1747204104
Short name T307
Test name
Test status
Simulation time 330269928220 ps
CPU time 351.81 seconds
Started Apr 25 01:16:18 PM PDT 24
Finished Apr 25 01:22:11 PM PDT 24
Peak memory 202384 kb
Host smart-ba6a6198-5f18-4435-9957-9c3a887cb486
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747204104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1747204104
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.331427676
Short name T230
Test name
Test status
Simulation time 170938682062 ps
CPU time 202.61 seconds
Started Apr 25 01:16:25 PM PDT 24
Finished Apr 25 01:19:48 PM PDT 24
Peak memory 202304 kb
Host smart-e463168f-045c-4093-913a-ab17c4e27a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331427676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.331427676
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3280197062
Short name T685
Test name
Test status
Simulation time 488003458577 ps
CPU time 1096.03 seconds
Started Apr 25 01:16:13 PM PDT 24
Finished Apr 25 01:34:29 PM PDT 24
Peak memory 202384 kb
Host smart-954d1d4e-c31f-41c6-b3e3-f9a064186c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280197062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3280197062
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1902217393
Short name T76
Test name
Test status
Simulation time 165526345951 ps
CPU time 376.25 seconds
Started Apr 25 01:16:12 PM PDT 24
Finished Apr 25 01:22:28 PM PDT 24
Peak memory 202296 kb
Host smart-01f050ea-7a49-4ea6-88bf-344340766de2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902217393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1902217393
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3036353578
Short name T715
Test name
Test status
Simulation time 161834250484 ps
CPU time 182.45 seconds
Started Apr 25 01:16:12 PM PDT 24
Finished Apr 25 01:19:15 PM PDT 24
Peak memory 202224 kb
Host smart-bc149cd2-437b-4fb4-b4b6-04a037c2447d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036353578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3036353578
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1936084149
Short name T225
Test name
Test status
Simulation time 370338238914 ps
CPU time 215.6 seconds
Started Apr 25 01:16:17 PM PDT 24
Finished Apr 25 01:19:53 PM PDT 24
Peak memory 202388 kb
Host smart-6ca07450-aad4-431a-9184-cc14e7f8609d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936084149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1936084149
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1056521903
Short name T476
Test name
Test status
Simulation time 402028536374 ps
CPU time 916.42 seconds
Started Apr 25 01:16:19 PM PDT 24
Finished Apr 25 01:31:36 PM PDT 24
Peak memory 202248 kb
Host smart-51d9b26c-1403-4a05-bf86-74998ce3cb9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056521903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1056521903
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.208838363
Short name T688
Test name
Test status
Simulation time 111997447347 ps
CPU time 618.13 seconds
Started Apr 25 01:16:25 PM PDT 24
Finished Apr 25 01:26:44 PM PDT 24
Peak memory 202680 kb
Host smart-11ea9194-8081-4173-ad84-f98c8d4ee024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208838363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.208838363
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1805321152
Short name T389
Test name
Test status
Simulation time 31441302481 ps
CPU time 36.52 seconds
Started Apr 25 01:16:22 PM PDT 24
Finished Apr 25 01:16:59 PM PDT 24
Peak memory 202144 kb
Host smart-7f7c733a-5444-46fa-aed8-5da63108e50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805321152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1805321152
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1221634214
Short name T717
Test name
Test status
Simulation time 5178541238 ps
CPU time 6.38 seconds
Started Apr 25 01:16:25 PM PDT 24
Finished Apr 25 01:16:32 PM PDT 24
Peak memory 202128 kb
Host smart-e36f438d-6ffe-40a4-957f-1253a6391450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221634214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1221634214
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3143023204
Short name T575
Test name
Test status
Simulation time 6010367285 ps
CPU time 5.3 seconds
Started Apr 25 01:16:15 PM PDT 24
Finished Apr 25 01:16:20 PM PDT 24
Peak memory 202124 kb
Host smart-4abbc299-de09-4042-b17b-7aaf87c7a313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143023204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3143023204
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2858245998
Short name T19
Test name
Test status
Simulation time 92120462621 ps
CPU time 367.64 seconds
Started Apr 25 01:16:23 PM PDT 24
Finished Apr 25 01:22:31 PM PDT 24
Peak memory 211184 kb
Host smart-80ad2027-9a6a-41b0-a81f-8274d53c19eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858245998 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2858245998
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1988251346
Short name T661
Test name
Test status
Simulation time 303809135 ps
CPU time 0.95 seconds
Started Apr 25 01:16:45 PM PDT 24
Finished Apr 25 01:16:47 PM PDT 24
Peak memory 201984 kb
Host smart-ae7e2f8e-06e8-4e52-b8c2-d2672d1d002f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988251346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1988251346
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2562421474
Short name T290
Test name
Test status
Simulation time 447806557632 ps
CPU time 468.56 seconds
Started Apr 25 01:17:17 PM PDT 24
Finished Apr 25 01:25:07 PM PDT 24
Peak memory 202240 kb
Host smart-8d8abf2f-83ec-4401-af60-c8f8c4968f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562421474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2562421474
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1186025472
Short name T240
Test name
Test status
Simulation time 162502595423 ps
CPU time 184.92 seconds
Started Apr 25 01:16:41 PM PDT 24
Finished Apr 25 01:19:46 PM PDT 24
Peak memory 202308 kb
Host smart-dec28ffd-395d-4d22-a80f-531fefeb8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186025472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1186025472
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3973621565
Short name T543
Test name
Test status
Simulation time 173697360332 ps
CPU time 435.07 seconds
Started Apr 25 01:16:38 PM PDT 24
Finished Apr 25 01:23:54 PM PDT 24
Peak memory 202368 kb
Host smart-b162e032-96be-4d10-9aa1-fabcf4a877a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973621565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3973621565
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3975328332
Short name T297
Test name
Test status
Simulation time 328357249603 ps
CPU time 76.34 seconds
Started Apr 25 01:16:35 PM PDT 24
Finished Apr 25 01:17:52 PM PDT 24
Peak memory 202336 kb
Host smart-1f560975-d939-4cb1-a0f1-21f7be08f6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975328332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3975328332
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2473325106
Short name T772
Test name
Test status
Simulation time 163586198625 ps
CPU time 93.88 seconds
Started Apr 25 01:16:35 PM PDT 24
Finished Apr 25 01:18:10 PM PDT 24
Peak memory 202216 kb
Host smart-dfa72852-9339-4e8c-8d4f-ff22dd4d9ed9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473325106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2473325106
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1042233868
Short name T228
Test name
Test status
Simulation time 374865821316 ps
CPU time 798.81 seconds
Started Apr 25 01:16:39 PM PDT 24
Finished Apr 25 01:29:59 PM PDT 24
Peak memory 202364 kb
Host smart-e7fd7996-6b68-4183-9ab3-f5cae5ec50f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042233868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1042233868
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4262412977
Short name T470
Test name
Test status
Simulation time 601955346890 ps
CPU time 353.05 seconds
Started Apr 25 01:16:40 PM PDT 24
Finished Apr 25 01:22:34 PM PDT 24
Peak memory 202196 kb
Host smart-c4de0728-7859-4c6a-b21e-fce44a2cdfea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262412977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4262412977
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.474673121
Short name T665
Test name
Test status
Simulation time 73078968715 ps
CPU time 397.11 seconds
Started Apr 25 01:16:44 PM PDT 24
Finished Apr 25 01:23:22 PM PDT 24
Peak memory 202652 kb
Host smart-dd158513-2f70-45e2-879c-d14389c19330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474673121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.474673121
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1140885508
Short name T613
Test name
Test status
Simulation time 38944471836 ps
CPU time 80.43 seconds
Started Apr 25 01:16:48 PM PDT 24
Finished Apr 25 01:18:09 PM PDT 24
Peak memory 202124 kb
Host smart-75a83b45-9a64-4126-a537-38233d8222c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140885508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1140885508
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3494685661
Short name T351
Test name
Test status
Simulation time 4183465060 ps
CPU time 3.61 seconds
Started Apr 25 01:16:46 PM PDT 24
Finished Apr 25 01:16:50 PM PDT 24
Peak memory 202116 kb
Host smart-edd8401e-3d29-47c8-a2ad-a59456c6d46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494685661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3494685661
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.741659190
Short name T377
Test name
Test status
Simulation time 6057325659 ps
CPU time 14.65 seconds
Started Apr 25 01:16:34 PM PDT 24
Finished Apr 25 01:16:49 PM PDT 24
Peak memory 202120 kb
Host smart-ff85ccfd-3dd5-45d7-848d-3344305d4188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741659190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.741659190
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2658095061
Short name T321
Test name
Test status
Simulation time 512976010418 ps
CPU time 1001.16 seconds
Started Apr 25 01:16:47 PM PDT 24
Finished Apr 25 01:33:29 PM PDT 24
Peak memory 202320 kb
Host smart-d14848ba-eaf6-45e0-a6da-e33fc45c0642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658095061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2658095061
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.466288818
Short name T371
Test name
Test status
Simulation time 408876094 ps
CPU time 0.81 seconds
Started Apr 25 01:17:04 PM PDT 24
Finished Apr 25 01:17:06 PM PDT 24
Peak memory 201936 kb
Host smart-1d20f563-0b98-4e8c-871a-1633557af4da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466288818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.466288818
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3485396692
Short name T162
Test name
Test status
Simulation time 330974586989 ps
CPU time 205.54 seconds
Started Apr 25 01:17:01 PM PDT 24
Finished Apr 25 01:20:27 PM PDT 24
Peak memory 202300 kb
Host smart-1e501056-1656-4b2a-a1a4-2684b55bdb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485396692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3485396692
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.489268043
Short name T92
Test name
Test status
Simulation time 327995382288 ps
CPU time 407.81 seconds
Started Apr 25 01:16:54 PM PDT 24
Finished Apr 25 01:23:43 PM PDT 24
Peak memory 202308 kb
Host smart-063b5cf7-c568-4f6a-9d51-f1c1a52d77b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=489268043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.489268043
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3766935190
Short name T522
Test name
Test status
Simulation time 489541051415 ps
CPU time 1103.23 seconds
Started Apr 25 01:16:53 PM PDT 24
Finished Apr 25 01:35:17 PM PDT 24
Peak memory 202308 kb
Host smart-defc6834-5595-4e33-ad71-064175256be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766935190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3766935190
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.589372069
Short name T510
Test name
Test status
Simulation time 323306034855 ps
CPU time 325.26 seconds
Started Apr 25 01:16:54 PM PDT 24
Finished Apr 25 01:22:20 PM PDT 24
Peak memory 202284 kb
Host smart-b41889f0-92cb-40e2-afbb-1bd130ccca31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=589372069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.589372069
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3947690292
Short name T322
Test name
Test status
Simulation time 566975780380 ps
CPU time 654.8 seconds
Started Apr 25 01:17:02 PM PDT 24
Finished Apr 25 01:27:57 PM PDT 24
Peak memory 202272 kb
Host smart-a4ac7c24-5cbc-4c64-9e74-aed20dfd04de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947690292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3947690292
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.715336472
Short name T629
Test name
Test status
Simulation time 597429440076 ps
CPU time 1361.88 seconds
Started Apr 25 01:17:09 PM PDT 24
Finished Apr 25 01:39:52 PM PDT 24
Peak memory 202348 kb
Host smart-5a10c3d3-12ef-42e3-9392-b028e84647d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715336472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.715336472
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.91313262
Short name T204
Test name
Test status
Simulation time 126344113533 ps
CPU time 444.19 seconds
Started Apr 25 01:17:04 PM PDT 24
Finished Apr 25 01:24:28 PM PDT 24
Peak memory 202648 kb
Host smart-d11c3293-57dc-4694-aae7-379dac1434da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91313262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.91313262
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.146525694
Short name T793
Test name
Test status
Simulation time 43319168823 ps
CPU time 75.86 seconds
Started Apr 25 01:17:07 PM PDT 24
Finished Apr 25 01:18:24 PM PDT 24
Peak memory 202072 kb
Host smart-e4075d48-a25b-4773-8020-20c5e381df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146525694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.146525694
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4285112624
Short name T722
Test name
Test status
Simulation time 3547504952 ps
CPU time 4.2 seconds
Started Apr 25 01:17:04 PM PDT 24
Finished Apr 25 01:17:09 PM PDT 24
Peak memory 202124 kb
Host smart-853009c2-c239-4168-a6ff-1ac58c58dc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285112624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4285112624
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4241981994
Short name T504
Test name
Test status
Simulation time 5730306297 ps
CPU time 13.55 seconds
Started Apr 25 01:16:45 PM PDT 24
Finished Apr 25 01:17:00 PM PDT 24
Peak memory 202040 kb
Host smart-3cd11805-7a76-4d57-9d49-58008c252d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241981994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4241981994
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.433929781
Short name T527
Test name
Test status
Simulation time 242546859000 ps
CPU time 98.16 seconds
Started Apr 25 01:17:06 PM PDT 24
Finished Apr 25 01:18:45 PM PDT 24
Peak memory 202304 kb
Host smart-9b8b1478-ffd9-4c86-86f9-0c522df0da44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433929781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
433929781
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3153999259
Short name T581
Test name
Test status
Simulation time 70053629115 ps
CPU time 69.7 seconds
Started Apr 25 01:17:05 PM PDT 24
Finished Apr 25 01:18:16 PM PDT 24
Peak memory 210944 kb
Host smart-f486d2d4-350d-446d-b272-a4a23b8ec797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153999259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3153999259
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4038766768
Short name T401
Test name
Test status
Simulation time 348584263 ps
CPU time 1.42 seconds
Started Apr 25 01:17:23 PM PDT 24
Finished Apr 25 01:17:25 PM PDT 24
Peak memory 201988 kb
Host smart-53372c37-171d-443d-97c0-35c9d7a4e0bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038766768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4038766768
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2399710577
Short name T398
Test name
Test status
Simulation time 255448194179 ps
CPU time 573.07 seconds
Started Apr 25 01:17:11 PM PDT 24
Finished Apr 25 01:26:45 PM PDT 24
Peak memory 202296 kb
Host smart-68da948c-e222-447e-97dd-c7c9d6ea4bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399710577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2399710577
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3925188320
Short name T583
Test name
Test status
Simulation time 157531759904 ps
CPU time 173.35 seconds
Started Apr 25 01:17:06 PM PDT 24
Finished Apr 25 01:20:00 PM PDT 24
Peak memory 202196 kb
Host smart-b8d46728-e672-4e9e-8c87-2ec38ffbe183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925188320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3925188320
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2076422896
Short name T418
Test name
Test status
Simulation time 330408833168 ps
CPU time 742.2 seconds
Started Apr 25 01:17:12 PM PDT 24
Finished Apr 25 01:29:35 PM PDT 24
Peak memory 202304 kb
Host smart-38724acc-3625-48eb-8652-e2f6b96723dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076422896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2076422896
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.434104173
Short name T168
Test name
Test status
Simulation time 483650584355 ps
CPU time 150.27 seconds
Started Apr 25 01:17:06 PM PDT 24
Finished Apr 25 01:19:37 PM PDT 24
Peak memory 202328 kb
Host smart-3462a22d-8971-4399-b3fc-339bf2349dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434104173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.434104173
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1275559428
Short name T520
Test name
Test status
Simulation time 164856324994 ps
CPU time 382.77 seconds
Started Apr 25 01:17:07 PM PDT 24
Finished Apr 25 01:23:30 PM PDT 24
Peak memory 202260 kb
Host smart-ffd46e93-83e3-44de-b9b6-1b0f8fee740a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275559428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1275559428
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2303943257
Short name T224
Test name
Test status
Simulation time 173911142224 ps
CPU time 94.56 seconds
Started Apr 25 01:17:10 PM PDT 24
Finished Apr 25 01:18:45 PM PDT 24
Peak memory 202364 kb
Host smart-915ef7a1-b4f0-4082-aea9-84b55d2f9adf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303943257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2303943257
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1658237398
Short name T780
Test name
Test status
Simulation time 590640602701 ps
CPU time 157.04 seconds
Started Apr 25 01:17:12 PM PDT 24
Finished Apr 25 01:19:49 PM PDT 24
Peak memory 202280 kb
Host smart-6ae60d54-5942-488d-911f-dc5186c3b9d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658237398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1658237398
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.62065647
Short name T614
Test name
Test status
Simulation time 72309550134 ps
CPU time 305.53 seconds
Started Apr 25 01:17:18 PM PDT 24
Finished Apr 25 01:22:24 PM PDT 24
Peak memory 202548 kb
Host smart-75d14270-236b-4765-8fa0-5cc9de7186ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62065647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.62065647
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.359298653
Short name T480
Test name
Test status
Simulation time 28538342032 ps
CPU time 4.79 seconds
Started Apr 25 01:17:16 PM PDT 24
Finished Apr 25 01:17:21 PM PDT 24
Peak memory 202124 kb
Host smart-4050e6a9-2240-4be8-8e08-3f1c14e0b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359298653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.359298653
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3038239096
Short name T385
Test name
Test status
Simulation time 4330686241 ps
CPU time 3.29 seconds
Started Apr 25 01:17:19 PM PDT 24
Finished Apr 25 01:17:23 PM PDT 24
Peak memory 202020 kb
Host smart-d7341f4c-50ae-436e-981d-34d7da9c388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038239096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3038239096
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3757250867
Short name T471
Test name
Test status
Simulation time 5853891197 ps
CPU time 15.77 seconds
Started Apr 25 01:17:06 PM PDT 24
Finished Apr 25 01:17:22 PM PDT 24
Peak memory 202116 kb
Host smart-0ab4613d-54cf-4f3f-ae48-a690bcd0d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757250867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3757250867
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.409378946
Short name T397
Test name
Test status
Simulation time 167283988895 ps
CPU time 394.16 seconds
Started Apr 25 01:17:15 PM PDT 24
Finished Apr 25 01:23:50 PM PDT 24
Peak memory 202304 kb
Host smart-87d30881-99cd-47d7-ac65-56c24a659a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409378946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
409378946
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.622866397
Short name T15
Test name
Test status
Simulation time 20504421375 ps
CPU time 107.95 seconds
Started Apr 25 01:17:16 PM PDT 24
Finished Apr 25 01:19:04 PM PDT 24
Peak memory 211100 kb
Host smart-96f4c031-67d0-4f08-adb5-a86a32eeff02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622866397 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.622866397
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2890119657
Short name T728
Test name
Test status
Simulation time 406864077 ps
CPU time 1.58 seconds
Started Apr 25 01:13:01 PM PDT 24
Finished Apr 25 01:13:03 PM PDT 24
Peak memory 202012 kb
Host smart-a081d87b-b32f-4f34-a058-d40ef3ee4064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890119657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2890119657
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2657711994
Short name T787
Test name
Test status
Simulation time 161367495098 ps
CPU time 62.95 seconds
Started Apr 25 01:12:56 PM PDT 24
Finished Apr 25 01:13:59 PM PDT 24
Peak memory 202388 kb
Host smart-c82cfd35-bfe0-4e57-90ab-5a571eb41e9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657711994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2657711994
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1900068975
Short name T736
Test name
Test status
Simulation time 164910869513 ps
CPU time 314.58 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:18:14 PM PDT 24
Peak memory 202188 kb
Host smart-5eedc836-0e84-41f8-bbd9-3fabb5f0fcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900068975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1900068975
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2973618420
Short name T636
Test name
Test status
Simulation time 164707340347 ps
CPU time 389.47 seconds
Started Apr 25 01:12:58 PM PDT 24
Finished Apr 25 01:19:28 PM PDT 24
Peak memory 202320 kb
Host smart-475dbfe8-76ac-4fb9-83a1-4ea5f5a72050
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973618420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2973618420
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.806215826
Short name T166
Test name
Test status
Simulation time 486978177778 ps
CPU time 223.08 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:16:43 PM PDT 24
Peak memory 202368 kb
Host smart-bc22b30c-7d6b-40e0-a753-06c993962e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806215826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.806215826
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.551136348
Short name T544
Test name
Test status
Simulation time 328542783717 ps
CPU time 685.08 seconds
Started Apr 25 01:12:57 PM PDT 24
Finished Apr 25 01:24:23 PM PDT 24
Peak memory 202384 kb
Host smart-f6402917-ba3a-4310-a8e0-1146ede3693c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=551136348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.551136348
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3210451592
Short name T295
Test name
Test status
Simulation time 640289651995 ps
CPU time 1405.17 seconds
Started Apr 25 01:12:58 PM PDT 24
Finished Apr 25 01:36:24 PM PDT 24
Peak memory 202300 kb
Host smart-a73d6347-2c19-4f60-a7d2-277553c09dcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210451592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3210451592
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1526412401
Short name T718
Test name
Test status
Simulation time 426947335630 ps
CPU time 1041.8 seconds
Started Apr 25 01:12:58 PM PDT 24
Finished Apr 25 01:30:21 PM PDT 24
Peak memory 202276 kb
Host smart-906283d6-f1bc-40b1-bc3a-606cd5a74898
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526412401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1526412401
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3045205898
Short name T202
Test name
Test status
Simulation time 111981192954 ps
CPU time 350.86 seconds
Started Apr 25 01:12:58 PM PDT 24
Finished Apr 25 01:18:50 PM PDT 24
Peak memory 202728 kb
Host smart-e3205c4a-48eb-44e9-9964-2161df92fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045205898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3045205898
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2938823122
Short name T601
Test name
Test status
Simulation time 40299334244 ps
CPU time 43.91 seconds
Started Apr 25 01:12:58 PM PDT 24
Finished Apr 25 01:13:43 PM PDT 24
Peak memory 202108 kb
Host smart-34d0c124-019d-4d5e-81b3-37f1519400a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938823122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2938823122
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3042839498
Short name T743
Test name
Test status
Simulation time 4075136271 ps
CPU time 5.03 seconds
Started Apr 25 01:13:00 PM PDT 24
Finished Apr 25 01:13:05 PM PDT 24
Peak memory 202128 kb
Host smart-dd929853-98ae-4a20-8213-602a34fea007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042839498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3042839498
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2581356525
Short name T73
Test name
Test status
Simulation time 8417838055 ps
CPU time 8.91 seconds
Started Apr 25 01:13:01 PM PDT 24
Finished Apr 25 01:13:11 PM PDT 24
Peak memory 217860 kb
Host smart-62e0bb4a-0016-400f-a98a-ac9d6410b79c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581356525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2581356525
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2404046778
Short name T578
Test name
Test status
Simulation time 5837789934 ps
CPU time 7.32 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:13:07 PM PDT 24
Peak memory 202036 kb
Host smart-5a9077df-aa87-4ff7-9643-886665957225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404046778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2404046778
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1481857967
Short name T786
Test name
Test status
Simulation time 713620763255 ps
CPU time 641.22 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:23:41 PM PDT 24
Peak memory 211024 kb
Host smart-72ab61ff-420a-4487-864d-6676e53c1a95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481857967 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1481857967
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3686159104
Short name T68
Test name
Test status
Simulation time 352551853 ps
CPU time 1.37 seconds
Started Apr 25 01:17:45 PM PDT 24
Finished Apr 25 01:17:47 PM PDT 24
Peak memory 201984 kb
Host smart-4701f9c9-4078-4659-997d-3f159a6b6f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686159104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3686159104
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.281407263
Short name T2
Test name
Test status
Simulation time 499534040974 ps
CPU time 1099.23 seconds
Started Apr 25 01:17:27 PM PDT 24
Finished Apr 25 01:35:47 PM PDT 24
Peak memory 202384 kb
Host smart-baa1ed08-4b72-423c-b385-f1bbc56d17bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281407263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.281407263
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2231658305
Short name T87
Test name
Test status
Simulation time 162188459206 ps
CPU time 148.27 seconds
Started Apr 25 01:17:28 PM PDT 24
Finished Apr 25 01:19:57 PM PDT 24
Peak memory 202268 kb
Host smart-760e88b7-aca0-4df8-a710-c194eb6cecde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231658305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2231658305
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2986798613
Short name T148
Test name
Test status
Simulation time 488354755307 ps
CPU time 266.12 seconds
Started Apr 25 01:17:22 PM PDT 24
Finished Apr 25 01:21:49 PM PDT 24
Peak memory 202256 kb
Host smart-0fa9a8f7-ad55-46be-ba16-104221abfb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986798613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2986798613
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2990349018
Short name T492
Test name
Test status
Simulation time 331498283318 ps
CPU time 197.92 seconds
Started Apr 25 01:17:29 PM PDT 24
Finished Apr 25 01:20:47 PM PDT 24
Peak memory 202284 kb
Host smart-33bbae5a-b004-465c-99d1-208c7a403530
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990349018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2990349018
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1681207296
Short name T696
Test name
Test status
Simulation time 392735225264 ps
CPU time 229.85 seconds
Started Apr 25 01:17:28 PM PDT 24
Finished Apr 25 01:21:19 PM PDT 24
Peak memory 202288 kb
Host smart-725255d3-29db-4b19-83e6-3c9472edfda6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681207296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1681207296
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1758221780
Short name T452
Test name
Test status
Simulation time 581262921443 ps
CPU time 685.36 seconds
Started Apr 25 01:17:26 PM PDT 24
Finished Apr 25 01:28:52 PM PDT 24
Peak memory 202336 kb
Host smart-02144c97-50b0-434b-8f01-93c83729cc82
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758221780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1758221780
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3774220357
Short name T724
Test name
Test status
Simulation time 116608418662 ps
CPU time 447.4 seconds
Started Apr 25 01:17:32 PM PDT 24
Finished Apr 25 01:25:00 PM PDT 24
Peak memory 202660 kb
Host smart-1b30f409-73f0-4442-9e67-054d048d9c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774220357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3774220357
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3485581084
Short name T348
Test name
Test status
Simulation time 34730220856 ps
CPU time 19.6 seconds
Started Apr 25 01:17:32 PM PDT 24
Finished Apr 25 01:17:52 PM PDT 24
Peak memory 202124 kb
Host smart-b47e7847-3fb9-4980-a623-b72963a1e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485581084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3485581084
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.971021408
Short name T405
Test name
Test status
Simulation time 5111931449 ps
CPU time 13.24 seconds
Started Apr 25 01:17:34 PM PDT 24
Finished Apr 25 01:17:48 PM PDT 24
Peak memory 201988 kb
Host smart-cfba414e-2f2f-424d-aee1-8d17a77432a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971021408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.971021408
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3191809878
Short name T430
Test name
Test status
Simulation time 5990947638 ps
CPU time 13.89 seconds
Started Apr 25 01:17:35 PM PDT 24
Finished Apr 25 01:17:49 PM PDT 24
Peak memory 202124 kb
Host smart-8fbcef53-7c33-4183-997b-f5beab9b4a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191809878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3191809878
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1985329793
Short name T310
Test name
Test status
Simulation time 188875065603 ps
CPU time 170.91 seconds
Started Apr 25 01:17:34 PM PDT 24
Finished Apr 25 01:20:25 PM PDT 24
Peak memory 219244 kb
Host smart-019a61d2-65de-4c4d-8bff-c6cbe2582dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985329793 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1985329793
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2078480481
Short name T386
Test name
Test status
Simulation time 507780448 ps
CPU time 1.73 seconds
Started Apr 25 01:17:58 PM PDT 24
Finished Apr 25 01:18:00 PM PDT 24
Peak memory 202008 kb
Host smart-9a2fa67c-8ae9-449a-95dd-c177263cf858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078480481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2078480481
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3072722912
Short name T746
Test name
Test status
Simulation time 170448782458 ps
CPU time 10.49 seconds
Started Apr 25 01:17:45 PM PDT 24
Finished Apr 25 01:17:56 PM PDT 24
Peak memory 202188 kb
Host smart-54642516-e574-4b2f-a09a-7269aecf7a3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072722912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3072722912
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1911771745
Short name T281
Test name
Test status
Simulation time 194245661555 ps
CPU time 418.88 seconds
Started Apr 25 01:17:44 PM PDT 24
Finished Apr 25 01:24:44 PM PDT 24
Peak memory 202296 kb
Host smart-d41fb92a-336f-486e-b3a6-5cf07fca2d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911771745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1911771745
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.263524301
Short name T647
Test name
Test status
Simulation time 166376282969 ps
CPU time 402.38 seconds
Started Apr 25 01:17:44 PM PDT 24
Finished Apr 25 01:24:27 PM PDT 24
Peak memory 202308 kb
Host smart-f9da682f-0669-4613-aa16-10d2bf8d9ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263524301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.263524301
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3737467866
Short name T365
Test name
Test status
Simulation time 160578755639 ps
CPU time 102.39 seconds
Started Apr 25 01:17:45 PM PDT 24
Finished Apr 25 01:19:28 PM PDT 24
Peak memory 202272 kb
Host smart-4a397a23-ba2f-48bb-bed2-9bf3e77e54cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737467866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3737467866
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.292097653
Short name T169
Test name
Test status
Simulation time 331302878962 ps
CPU time 165.82 seconds
Started Apr 25 01:17:38 PM PDT 24
Finished Apr 25 01:20:25 PM PDT 24
Peak memory 202296 kb
Host smart-24b080f0-c3ea-4e15-b387-8b568a92dec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292097653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.292097653
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4156449988
Short name T396
Test name
Test status
Simulation time 492604327581 ps
CPU time 787.06 seconds
Started Apr 25 01:17:38 PM PDT 24
Finished Apr 25 01:30:45 PM PDT 24
Peak memory 202280 kb
Host smart-5532d529-23c8-436a-a8de-3ed1ab710a22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156449988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4156449988
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.138305697
Short name T653
Test name
Test status
Simulation time 187057582225 ps
CPU time 109.09 seconds
Started Apr 25 01:17:52 PM PDT 24
Finished Apr 25 01:19:42 PM PDT 24
Peak memory 202328 kb
Host smart-bc5c54f9-7c6d-42da-bb57-68ae0d57dc75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138305697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.138305697
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3732133892
Short name T441
Test name
Test status
Simulation time 203206780320 ps
CPU time 124.28 seconds
Started Apr 25 01:17:45 PM PDT 24
Finished Apr 25 01:19:50 PM PDT 24
Peak memory 202308 kb
Host smart-58d70a31-0889-4865-9e74-ec4a551f12da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732133892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3732133892
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.927789518
Short name T459
Test name
Test status
Simulation time 85071901057 ps
CPU time 438.57 seconds
Started Apr 25 01:17:54 PM PDT 24
Finished Apr 25 01:25:13 PM PDT 24
Peak memory 202656 kb
Host smart-fa18c54e-5839-4d03-872b-753c618e46b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927789518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.927789518
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4005307640
Short name T481
Test name
Test status
Simulation time 39812281137 ps
CPU time 88.37 seconds
Started Apr 25 01:17:57 PM PDT 24
Finished Apr 25 01:19:26 PM PDT 24
Peak memory 202140 kb
Host smart-b5d42fcd-869c-445a-8f73-0113ebdb8f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005307640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4005307640
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4263932695
Short name T375
Test name
Test status
Simulation time 3711910360 ps
CPU time 2.12 seconds
Started Apr 25 01:17:49 PM PDT 24
Finished Apr 25 01:17:52 PM PDT 24
Peak memory 202132 kb
Host smart-bfb80e46-d429-4ebf-8fb2-2787e5447c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263932695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4263932695
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3536995462
Short name T88
Test name
Test status
Simulation time 5922451934 ps
CPU time 2.74 seconds
Started Apr 25 01:17:38 PM PDT 24
Finished Apr 25 01:17:42 PM PDT 24
Peak memory 202076 kb
Host smart-af2100bf-fa75-430d-86b8-8259d3e6dcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536995462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3536995462
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2996884378
Short name T453
Test name
Test status
Simulation time 413946294909 ps
CPU time 268.92 seconds
Started Apr 25 01:17:53 PM PDT 24
Finished Apr 25 01:22:23 PM PDT 24
Peak memory 202236 kb
Host smart-8341f1c6-1f04-4e93-8ac7-d5b2e4d43f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996884378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2996884378
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.650525028
Short name T23
Test name
Test status
Simulation time 190110462281 ps
CPU time 348.55 seconds
Started Apr 25 01:17:59 PM PDT 24
Finished Apr 25 01:23:48 PM PDT 24
Peak memory 211000 kb
Host smart-00315bc6-95f9-4ccd-8743-d30019c6d8ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650525028 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.650525028
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2688667009
Short name T563
Test name
Test status
Simulation time 530950500 ps
CPU time 0.71 seconds
Started Apr 25 01:18:11 PM PDT 24
Finished Apr 25 01:18:12 PM PDT 24
Peak memory 201988 kb
Host smart-a1e19ddf-8ef6-4753-8b3f-415240fc2ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688667009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2688667009
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3731801026
Short name T266
Test name
Test status
Simulation time 512637559434 ps
CPU time 570.14 seconds
Started Apr 25 01:18:02 PM PDT 24
Finished Apr 25 01:27:33 PM PDT 24
Peak memory 202304 kb
Host smart-d4fc0094-94ee-46af-9d16-b0a365d3cb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731801026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3731801026
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4127400362
Short name T757
Test name
Test status
Simulation time 167706366921 ps
CPU time 203.42 seconds
Started Apr 25 01:17:55 PM PDT 24
Finished Apr 25 01:21:18 PM PDT 24
Peak memory 202328 kb
Host smart-3e4e1a27-e0a0-484a-ba95-2aaae4666548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127400362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4127400362
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4047657266
Short name T553
Test name
Test status
Simulation time 492279828977 ps
CPU time 313.47 seconds
Started Apr 25 01:18:01 PM PDT 24
Finished Apr 25 01:23:15 PM PDT 24
Peak memory 202304 kb
Host smart-8cbe3ead-53b0-49b1-ad4f-e7ff4d233782
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047657266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4047657266
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2433502660
Short name T313
Test name
Test status
Simulation time 496731311248 ps
CPU time 1049.13 seconds
Started Apr 25 01:17:56 PM PDT 24
Finished Apr 25 01:35:25 PM PDT 24
Peak memory 202232 kb
Host smart-7f5d2d23-b270-4397-906d-b626f38ff5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433502660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2433502660
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2690279853
Short name T468
Test name
Test status
Simulation time 333997343401 ps
CPU time 715.37 seconds
Started Apr 25 01:17:54 PM PDT 24
Finished Apr 25 01:29:50 PM PDT 24
Peak memory 202308 kb
Host smart-69c3cb06-7cb0-4982-8279-0970c0410780
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690279853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2690279853
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3554860560
Short name T714
Test name
Test status
Simulation time 551724773425 ps
CPU time 1306.52 seconds
Started Apr 25 01:18:02 PM PDT 24
Finished Apr 25 01:39:49 PM PDT 24
Peak memory 202372 kb
Host smart-4bde1e80-1d64-4f5c-851e-20ee813dcdda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554860560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3554860560
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1412645712
Short name T637
Test name
Test status
Simulation time 397825629669 ps
CPU time 969.33 seconds
Started Apr 25 01:18:01 PM PDT 24
Finished Apr 25 01:34:11 PM PDT 24
Peak memory 202248 kb
Host smart-6d890702-6fee-4dfb-ad6f-0824d944dd57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412645712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1412645712
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.134443397
Short name T191
Test name
Test status
Simulation time 134824148862 ps
CPU time 556.7 seconds
Started Apr 25 01:18:01 PM PDT 24
Finished Apr 25 01:27:18 PM PDT 24
Peak memory 202720 kb
Host smart-12efe571-4864-4518-acdd-eb17678af2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134443397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.134443397
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2991750004
Short name T461
Test name
Test status
Simulation time 25265185081 ps
CPU time 16.35 seconds
Started Apr 25 01:18:00 PM PDT 24
Finished Apr 25 01:18:16 PM PDT 24
Peak memory 202068 kb
Host smart-e54a8713-1ba5-43a5-9140-476dd880816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991750004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2991750004
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1642835347
Short name T79
Test name
Test status
Simulation time 4537800227 ps
CPU time 6.08 seconds
Started Apr 25 01:18:01 PM PDT 24
Finished Apr 25 01:18:08 PM PDT 24
Peak memory 202116 kb
Host smart-15375a65-e21a-45d4-8fc7-a71e79c39076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642835347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1642835347
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3459000983
Short name T442
Test name
Test status
Simulation time 5992785117 ps
CPU time 4.63 seconds
Started Apr 25 01:17:55 PM PDT 24
Finished Apr 25 01:18:00 PM PDT 24
Peak memory 202084 kb
Host smart-afd0bb78-9e59-4595-93cb-9855d19860d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459000983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3459000983
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3701491918
Short name T192
Test name
Test status
Simulation time 245826062138 ps
CPU time 841.07 seconds
Started Apr 25 01:18:11 PM PDT 24
Finished Apr 25 01:32:13 PM PDT 24
Peak memory 210848 kb
Host smart-06a6a988-2394-4122-a01f-be432be5b340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701491918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3701491918
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3733457321
Short name T35
Test name
Test status
Simulation time 66972594019 ps
CPU time 86.3 seconds
Started Apr 25 01:18:07 PM PDT 24
Finished Apr 25 01:19:34 PM PDT 24
Peak memory 218332 kb
Host smart-da386424-23c1-44e5-a4c2-0d6f8601b52a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733457321 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3733457321
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2280028166
Short name T597
Test name
Test status
Simulation time 456193066 ps
CPU time 1.76 seconds
Started Apr 25 01:18:23 PM PDT 24
Finished Apr 25 01:18:25 PM PDT 24
Peak memory 201896 kb
Host smart-9a49a327-4579-4571-a014-73061a957550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280028166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2280028166
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.4286966152
Short name T269
Test name
Test status
Simulation time 166465035356 ps
CPU time 97.44 seconds
Started Apr 25 01:18:18 PM PDT 24
Finished Apr 25 01:19:56 PM PDT 24
Peak memory 202276 kb
Host smart-e4d525a1-7c2d-473c-9340-e731c6e013a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286966152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4286966152
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.205632924
Short name T156
Test name
Test status
Simulation time 326543800771 ps
CPU time 184.23 seconds
Started Apr 25 01:18:16 PM PDT 24
Finished Apr 25 01:21:21 PM PDT 24
Peak memory 202300 kb
Host smart-8d03eb58-7a46-4a4d-9ba2-4bc5cdffc583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205632924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.205632924
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3640093374
Short name T176
Test name
Test status
Simulation time 493353482281 ps
CPU time 254.68 seconds
Started Apr 25 01:18:18 PM PDT 24
Finished Apr 25 01:22:34 PM PDT 24
Peak memory 202188 kb
Host smart-738c7cec-8bf4-4acd-a94d-bda9ae132a9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640093374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3640093374
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1515762950
Short name T75
Test name
Test status
Simulation time 505092884697 ps
CPU time 1068.32 seconds
Started Apr 25 01:18:12 PM PDT 24
Finished Apr 25 01:36:02 PM PDT 24
Peak memory 202360 kb
Host smart-a04d885d-a3be-4281-887a-c0a408d94cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515762950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1515762950
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2499191758
Short name T503
Test name
Test status
Simulation time 491510522376 ps
CPU time 1125.34 seconds
Started Apr 25 01:18:13 PM PDT 24
Finished Apr 25 01:36:59 PM PDT 24
Peak memory 202244 kb
Host smart-1a93c3fe-fe58-4829-bc55-622bb9776da7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499191758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2499191758
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4264604037
Short name T41
Test name
Test status
Simulation time 546876971285 ps
CPU time 1208.83 seconds
Started Apr 25 01:18:17 PM PDT 24
Finished Apr 25 01:38:26 PM PDT 24
Peak memory 202448 kb
Host smart-26f049d0-1394-4fed-94bb-ce4853381afc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264604037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4264604037
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1089953555
Short name T40
Test name
Test status
Simulation time 593766292594 ps
CPU time 668.8 seconds
Started Apr 25 01:18:17 PM PDT 24
Finished Apr 25 01:29:26 PM PDT 24
Peak memory 202296 kb
Host smart-828e2395-bd63-4a67-a839-37ee5e6f2b8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089953555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1089953555
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2288603321
Short name T595
Test name
Test status
Simulation time 136540312005 ps
CPU time 667.83 seconds
Started Apr 25 01:18:24 PM PDT 24
Finished Apr 25 01:29:32 PM PDT 24
Peak memory 202592 kb
Host smart-4fde4ae6-bea1-4f12-a4f3-3228731d6d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288603321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2288603321
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.74930244
Short name T667
Test name
Test status
Simulation time 37479747049 ps
CPU time 22.6 seconds
Started Apr 25 01:18:18 PM PDT 24
Finished Apr 25 01:18:41 PM PDT 24
Peak memory 202060 kb
Host smart-2f1e5561-9f14-48e8-92fb-a33ed78bc4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74930244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.74930244
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1182142614
Short name T631
Test name
Test status
Simulation time 4777207595 ps
CPU time 11.27 seconds
Started Apr 25 01:18:18 PM PDT 24
Finished Apr 25 01:18:31 PM PDT 24
Peak memory 202072 kb
Host smart-a586c93d-80c6-4c6f-920a-9848ca9d242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182142614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1182142614
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2793964815
Short name T359
Test name
Test status
Simulation time 5913089348 ps
CPU time 7.23 seconds
Started Apr 25 01:18:11 PM PDT 24
Finished Apr 25 01:18:19 PM PDT 24
Peak memory 202068 kb
Host smart-185f13a9-e065-489d-976f-66b7907d5071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793964815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2793964815
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3968103994
Short name T147
Test name
Test status
Simulation time 722359761994 ps
CPU time 1606.97 seconds
Started Apr 25 01:18:24 PM PDT 24
Finished Apr 25 01:45:11 PM PDT 24
Peak memory 202388 kb
Host smart-cb7723a5-1341-4462-92d8-d22ae4619223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968103994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3968103994
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3433213479
Short name T680
Test name
Test status
Simulation time 18353419106 ps
CPU time 66.42 seconds
Started Apr 25 01:18:23 PM PDT 24
Finished Apr 25 01:19:30 PM PDT 24
Peak memory 210996 kb
Host smart-ae07c06d-95b5-4da2-a9a5-c0da180b1b29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433213479 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3433213479
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3985754294
Short name T512
Test name
Test status
Simulation time 364313321 ps
CPU time 0.82 seconds
Started Apr 25 01:18:36 PM PDT 24
Finished Apr 25 01:18:38 PM PDT 24
Peak memory 201896 kb
Host smart-7ee1f88b-9a84-44b6-a086-578f820bd7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985754294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3985754294
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.4060986139
Short name T208
Test name
Test status
Simulation time 351007746664 ps
CPU time 403.24 seconds
Started Apr 25 01:18:30 PM PDT 24
Finished Apr 25 01:25:14 PM PDT 24
Peak memory 202380 kb
Host smart-8bbf4d12-4f34-4056-9ad3-115137366d04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060986139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.4060986139
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2173426178
Short name T214
Test name
Test status
Simulation time 509831189545 ps
CPU time 1182.1 seconds
Started Apr 25 01:18:29 PM PDT 24
Finished Apr 25 01:38:12 PM PDT 24
Peak memory 202332 kb
Host smart-75d2df56-83c5-4b34-b2be-87a8e61e39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173426178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2173426178
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2964718652
Short name T560
Test name
Test status
Simulation time 495765490535 ps
CPU time 1215.84 seconds
Started Apr 25 01:18:32 PM PDT 24
Finished Apr 25 01:38:48 PM PDT 24
Peak memory 202280 kb
Host smart-59aaa9df-2882-4b72-83f4-05501306abca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964718652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2964718652
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4241254827
Short name T170
Test name
Test status
Simulation time 483236186798 ps
CPU time 165.92 seconds
Started Apr 25 01:18:22 PM PDT 24
Finished Apr 25 01:21:08 PM PDT 24
Peak memory 202348 kb
Host smart-9b2fc2c7-9cd1-4547-965b-b608ead1cb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241254827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4241254827
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.191397291
Short name T479
Test name
Test status
Simulation time 491205737732 ps
CPU time 160.65 seconds
Started Apr 25 01:18:33 PM PDT 24
Finished Apr 25 01:21:14 PM PDT 24
Peak memory 202364 kb
Host smart-80814e39-b7d0-4641-bf4a-082e010dcf08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=191397291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.191397291
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1837992730
Short name T741
Test name
Test status
Simulation time 200482777973 ps
CPU time 128.54 seconds
Started Apr 25 01:18:29 PM PDT 24
Finished Apr 25 01:20:39 PM PDT 24
Peak memory 202264 kb
Host smart-855c28df-97e2-45ce-a002-844db6ab603f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837992730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1837992730
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.856380987
Short name T687
Test name
Test status
Simulation time 75585983703 ps
CPU time 341.71 seconds
Started Apr 25 01:18:35 PM PDT 24
Finished Apr 25 01:24:17 PM PDT 24
Peak memory 202656 kb
Host smart-31cd3e8b-9563-47fa-a1c7-73aec778c370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856380987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.856380987
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3163998328
Short name T382
Test name
Test status
Simulation time 45509583109 ps
CPU time 99.9 seconds
Started Apr 25 01:18:28 PM PDT 24
Finished Apr 25 01:20:10 PM PDT 24
Peak memory 202096 kb
Host smart-a60f1a02-c837-42aa-aed9-64e122b2ed4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163998328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3163998328
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2186825022
Short name T642
Test name
Test status
Simulation time 5381752362 ps
CPU time 13.74 seconds
Started Apr 25 01:18:28 PM PDT 24
Finished Apr 25 01:18:42 PM PDT 24
Peak memory 202128 kb
Host smart-0fc6ce7f-b8ca-4eea-91fa-70198f895eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186825022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2186825022
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4132326797
Short name T364
Test name
Test status
Simulation time 5900366743 ps
CPU time 4.29 seconds
Started Apr 25 01:18:24 PM PDT 24
Finished Apr 25 01:18:29 PM PDT 24
Peak memory 202016 kb
Host smart-67bb56bc-e9f9-4bdd-857d-234b849fe563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132326797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4132326797
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.758581087
Short name T74
Test name
Test status
Simulation time 1655274638994 ps
CPU time 902.43 seconds
Started Apr 25 01:18:35 PM PDT 24
Finished Apr 25 01:33:38 PM PDT 24
Peak memory 210864 kb
Host smart-20a10dbe-8684-45d3-9d49-2bfcd8bf2c53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758581087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
758581087
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2794962158
Short name T17
Test name
Test status
Simulation time 131437016101 ps
CPU time 149.38 seconds
Started Apr 25 01:18:34 PM PDT 24
Finished Apr 25 01:21:04 PM PDT 24
Peak memory 202472 kb
Host smart-d1f70948-b6bd-452e-b3e7-f4146caf4a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794962158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2794962158
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2961784734
Short name T623
Test name
Test status
Simulation time 426827874 ps
CPU time 1.62 seconds
Started Apr 25 01:18:51 PM PDT 24
Finished Apr 25 01:18:53 PM PDT 24
Peak memory 201928 kb
Host smart-40f6ecf2-ce79-45ca-bc92-2d7afb7f5cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961784734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2961784734
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.372456377
Short name T245
Test name
Test status
Simulation time 350705411115 ps
CPU time 248.53 seconds
Started Apr 25 01:18:44 PM PDT 24
Finished Apr 25 01:22:53 PM PDT 24
Peak memory 202316 kb
Host smart-6b3f4481-089b-4e8e-bfdb-bdbad10f5d6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372456377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.372456377
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1588762852
Short name T733
Test name
Test status
Simulation time 162898520381 ps
CPU time 96.18 seconds
Started Apr 25 01:18:41 PM PDT 24
Finished Apr 25 01:20:18 PM PDT 24
Peak memory 202388 kb
Host smart-19c520f9-9a2c-4fa4-8ad9-0991acab31ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588762852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1588762852
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3957988831
Short name T577
Test name
Test status
Simulation time 332668028504 ps
CPU time 364.94 seconds
Started Apr 25 01:18:41 PM PDT 24
Finished Apr 25 01:24:46 PM PDT 24
Peak memory 202324 kb
Host smart-032ac150-c3c2-4412-bda3-1e15b5a6deba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957988831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3957988831
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1950608507
Short name T447
Test name
Test status
Simulation time 168044812142 ps
CPU time 100.89 seconds
Started Apr 25 01:18:40 PM PDT 24
Finished Apr 25 01:20:22 PM PDT 24
Peak memory 202320 kb
Host smart-f88c4c8a-6bf2-4f46-ade2-c4c367cc348d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950608507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1950608507
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1404137258
Short name T477
Test name
Test status
Simulation time 487911575795 ps
CPU time 159.54 seconds
Started Apr 25 01:18:42 PM PDT 24
Finished Apr 25 01:21:22 PM PDT 24
Peak memory 202296 kb
Host smart-1406ed2c-89b2-4fd4-9071-f4d8fc36564f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404137258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1404137258
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2066651028
Short name T334
Test name
Test status
Simulation time 555083056825 ps
CPU time 661.04 seconds
Started Apr 25 01:18:46 PM PDT 24
Finished Apr 25 01:29:48 PM PDT 24
Peak memory 202312 kb
Host smart-0c475b13-72bf-4892-924c-0fb7cecedfc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066651028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2066651028
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3098241632
Short name T154
Test name
Test status
Simulation time 197909818631 ps
CPU time 65.86 seconds
Started Apr 25 01:18:46 PM PDT 24
Finished Apr 25 01:19:52 PM PDT 24
Peak memory 202288 kb
Host smart-f0020505-9ffd-4428-9ac8-9e7c6607ccdc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098241632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3098241632
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3439679899
Short name T49
Test name
Test status
Simulation time 78071985580 ps
CPU time 245.89 seconds
Started Apr 25 01:18:44 PM PDT 24
Finished Apr 25 01:22:51 PM PDT 24
Peak memory 202748 kb
Host smart-f11b95ad-5fe8-46ec-b072-ef6226565e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439679899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3439679899
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.236775440
Short name T390
Test name
Test status
Simulation time 23352410141 ps
CPU time 5.13 seconds
Started Apr 25 01:18:44 PM PDT 24
Finished Apr 25 01:18:50 PM PDT 24
Peak memory 202136 kb
Host smart-1d3595a9-8258-4cdf-b6ce-1e0ee49e5d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236775440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.236775440
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.882224176
Short name T789
Test name
Test status
Simulation time 2729359815 ps
CPU time 7.22 seconds
Started Apr 25 01:18:47 PM PDT 24
Finished Apr 25 01:18:55 PM PDT 24
Peak memory 202076 kb
Host smart-0ec86d57-491a-47c2-bc25-e446334b1d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882224176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.882224176
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4048828302
Short name T562
Test name
Test status
Simulation time 5772039007 ps
CPU time 8.16 seconds
Started Apr 25 01:18:36 PM PDT 24
Finished Apr 25 01:18:44 PM PDT 24
Peak memory 202076 kb
Host smart-82197dd6-9093-46f5-a48f-dd5840dd1184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048828302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4048828302
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.64160622
Short name T541
Test name
Test status
Simulation time 174271405171 ps
CPU time 94.34 seconds
Started Apr 25 01:18:46 PM PDT 24
Finished Apr 25 01:20:21 PM PDT 24
Peak memory 202264 kb
Host smart-4f7f28ca-685c-4c6e-95c4-77190fa02f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64160622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.64160622
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.671144251
Short name T20
Test name
Test status
Simulation time 217912710434 ps
CPU time 148.51 seconds
Started Apr 25 01:18:46 PM PDT 24
Finished Apr 25 01:21:15 PM PDT 24
Peak memory 210972 kb
Host smart-d302a5ae-b36b-430e-9ef9-b65922ebf2d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671144251 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.671144251
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2864385129
Short name T463
Test name
Test status
Simulation time 496813247 ps
CPU time 1.07 seconds
Started Apr 25 01:19:12 PM PDT 24
Finished Apr 25 01:19:22 PM PDT 24
Peak memory 202004 kb
Host smart-4e0a8875-93ab-466a-aa9b-d00240130379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864385129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2864385129
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.254400753
Short name T286
Test name
Test status
Simulation time 327072002372 ps
CPU time 82.11 seconds
Started Apr 25 01:18:57 PM PDT 24
Finished Apr 25 01:20:22 PM PDT 24
Peak memory 202332 kb
Host smart-91193d23-430b-4f23-b157-fb533138a78e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254400753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.254400753
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2403071756
Short name T227
Test name
Test status
Simulation time 328446937197 ps
CPU time 145.13 seconds
Started Apr 25 01:19:06 PM PDT 24
Finished Apr 25 01:21:41 PM PDT 24
Peak memory 202260 kb
Host smart-39bd31d2-bddd-4a35-8680-d82abf2c71f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403071756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2403071756
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4076366913
Short name T128
Test name
Test status
Simulation time 166514071324 ps
CPU time 52.07 seconds
Started Apr 25 01:18:51 PM PDT 24
Finished Apr 25 01:19:44 PM PDT 24
Peak memory 202192 kb
Host smart-e33465a4-a7f1-4ccb-b4d9-acf159c67b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076366913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4076366913
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2907185931
Short name T649
Test name
Test status
Simulation time 165724106475 ps
CPU time 100.81 seconds
Started Apr 25 01:18:50 PM PDT 24
Finished Apr 25 01:20:32 PM PDT 24
Peak memory 202292 kb
Host smart-dab8b5b0-1069-4ac7-b089-64b28c10142c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907185931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2907185931
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3895269177
Short name T428
Test name
Test status
Simulation time 167970449435 ps
CPU time 404.68 seconds
Started Apr 25 01:18:52 PM PDT 24
Finished Apr 25 01:25:38 PM PDT 24
Peak memory 202324 kb
Host smart-d3485ab3-8c1d-4ee8-8c51-edd0f18d0624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895269177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3895269177
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2257157144
Short name T445
Test name
Test status
Simulation time 492157466660 ps
CPU time 1140.72 seconds
Started Apr 25 01:18:50 PM PDT 24
Finished Apr 25 01:37:52 PM PDT 24
Peak memory 202344 kb
Host smart-90fa8a00-8944-4c72-80bf-c35c74ba5080
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257157144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2257157144
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2470102984
Short name T254
Test name
Test status
Simulation time 356389817086 ps
CPU time 792.44 seconds
Started Apr 25 01:18:57 PM PDT 24
Finished Apr 25 01:32:13 PM PDT 24
Peak memory 202260 kb
Host smart-53f41653-4409-47df-b241-da27a38daf04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470102984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2470102984
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1627513878
Short name T752
Test name
Test status
Simulation time 609451461555 ps
CPU time 330.08 seconds
Started Apr 25 01:18:57 PM PDT 24
Finished Apr 25 01:24:32 PM PDT 24
Peak memory 202296 kb
Host smart-a1a32aba-98fe-4e0d-9f36-0a3839413dec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627513878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1627513878
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.727883195
Short name T340
Test name
Test status
Simulation time 93465547423 ps
CPU time 390.86 seconds
Started Apr 25 01:19:07 PM PDT 24
Finished Apr 25 01:25:49 PM PDT 24
Peak memory 202592 kb
Host smart-6cd81705-bdfc-4603-b7e1-4359f3d3a9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727883195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.727883195
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2612128001
Short name T598
Test name
Test status
Simulation time 28566304187 ps
CPU time 11.83 seconds
Started Apr 25 01:19:05 PM PDT 24
Finished Apr 25 01:19:26 PM PDT 24
Peak memory 202120 kb
Host smart-962b5881-c7e0-45b2-ad6d-2418732aa9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612128001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2612128001
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2408780965
Short name T394
Test name
Test status
Simulation time 3288819664 ps
CPU time 4.32 seconds
Started Apr 25 01:19:07 PM PDT 24
Finished Apr 25 01:19:21 PM PDT 24
Peak memory 202076 kb
Host smart-9c760f1f-8461-4494-89a2-2e441ced42fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408780965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2408780965
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.351499837
Short name T117
Test name
Test status
Simulation time 5682593043 ps
CPU time 7.58 seconds
Started Apr 25 01:18:52 PM PDT 24
Finished Apr 25 01:19:01 PM PDT 24
Peak memory 202140 kb
Host smart-2218fabc-2661-46d6-b036-a4375339c2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351499837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.351499837
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2864370670
Short name T552
Test name
Test status
Simulation time 453409487233 ps
CPU time 437.44 seconds
Started Apr 25 01:19:12 PM PDT 24
Finished Apr 25 01:26:39 PM PDT 24
Peak memory 210868 kb
Host smart-bf6f9e64-71bf-4d12-9b36-af827defe5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864370670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2864370670
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1684465779
Short name T239
Test name
Test status
Simulation time 166718975811 ps
CPU time 86.43 seconds
Started Apr 25 01:19:06 PM PDT 24
Finished Apr 25 01:20:42 PM PDT 24
Peak memory 211000 kb
Host smart-d7bdb9d3-68ea-4f3b-9985-6b8729ea0e71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684465779 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1684465779
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4283131070
Short name T548
Test name
Test status
Simulation time 537084371 ps
CPU time 0.8 seconds
Started Apr 25 01:19:24 PM PDT 24
Finished Apr 25 01:19:28 PM PDT 24
Peak memory 202008 kb
Host smart-614d4302-d2c7-47b6-b0cb-41030e1e1dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283131070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4283131070
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2763955313
Short name T726
Test name
Test status
Simulation time 164175843812 ps
CPU time 187.35 seconds
Started Apr 25 01:19:17 PM PDT 24
Finished Apr 25 01:22:31 PM PDT 24
Peak memory 202268 kb
Host smart-c7e18548-281b-48fe-888a-09cef3e5b75a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763955313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2763955313
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.689462514
Short name T730
Test name
Test status
Simulation time 440597743462 ps
CPU time 296.46 seconds
Started Apr 25 01:19:17 PM PDT 24
Finished Apr 25 01:24:20 PM PDT 24
Peak memory 202304 kb
Host smart-7bce3fad-37fd-40e8-84bc-64fdf57845a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689462514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.689462514
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2959938683
Short name T213
Test name
Test status
Simulation time 162951704596 ps
CPU time 191.34 seconds
Started Apr 25 01:19:14 PM PDT 24
Finished Apr 25 01:22:34 PM PDT 24
Peak memory 202304 kb
Host smart-6f5fb6b5-1fa7-4a02-8632-d6d5145eae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959938683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2959938683
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1271213102
Short name T380
Test name
Test status
Simulation time 318046193990 ps
CPU time 688.83 seconds
Started Apr 25 01:19:16 PM PDT 24
Finished Apr 25 01:30:52 PM PDT 24
Peak memory 202200 kb
Host smart-2417f79e-20da-407c-be60-2074c1bd8837
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271213102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1271213102
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2094828827
Short name T129
Test name
Test status
Simulation time 336683537586 ps
CPU time 727.78 seconds
Started Apr 25 01:19:11 PM PDT 24
Finished Apr 25 01:31:29 PM PDT 24
Peak memory 202296 kb
Host smart-9bb27ba9-7c87-4449-aa5d-6634e784bd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094828827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2094828827
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.953059347
Short name T518
Test name
Test status
Simulation time 167771428043 ps
CPU time 380.55 seconds
Started Apr 25 01:19:11 PM PDT 24
Finished Apr 25 01:25:41 PM PDT 24
Peak memory 202180 kb
Host smart-8377fb22-8931-4911-aaa5-f37a81f26788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=953059347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.953059347
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4285728555
Short name T706
Test name
Test status
Simulation time 193093827069 ps
CPU time 420.23 seconds
Started Apr 25 01:19:18 PM PDT 24
Finished Apr 25 01:26:24 PM PDT 24
Peak memory 202240 kb
Host smart-3aa8f724-1567-4b31-a3b4-ecba1870cf29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285728555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4285728555
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.236105973
Short name T426
Test name
Test status
Simulation time 412497157567 ps
CPU time 232.74 seconds
Started Apr 25 01:19:17 PM PDT 24
Finished Apr 25 01:23:16 PM PDT 24
Peak memory 202296 kb
Host smart-63e51d3e-454e-4cec-ab96-3e51957be49d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236105973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.236105973
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.27635691
Short name T29
Test name
Test status
Simulation time 102207669883 ps
CPU time 362.22 seconds
Started Apr 25 01:19:21 PM PDT 24
Finished Apr 25 01:25:27 PM PDT 24
Peak memory 202660 kb
Host smart-0fb79f73-9f0a-4bed-bef4-226795422c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27635691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.27635691
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2888087360
Short name T681
Test name
Test status
Simulation time 45281323457 ps
CPU time 51.69 seconds
Started Apr 25 01:19:23 PM PDT 24
Finished Apr 25 01:20:17 PM PDT 24
Peak memory 202068 kb
Host smart-adb101c1-177c-465c-8793-4b2dab0406fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888087360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2888087360
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3448810287
Short name T781
Test name
Test status
Simulation time 2937649476 ps
CPU time 2.39 seconds
Started Apr 25 01:19:22 PM PDT 24
Finished Apr 25 01:19:28 PM PDT 24
Peak memory 202060 kb
Host smart-119445d0-0e35-4b6b-ad23-cd92ed7b546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448810287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3448810287
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3020423006
Short name T635
Test name
Test status
Simulation time 6053857068 ps
CPU time 7.46 seconds
Started Apr 25 01:19:12 PM PDT 24
Finished Apr 25 01:19:29 PM PDT 24
Peak memory 202136 kb
Host smart-c1c12f92-b5af-4b63-b0bc-6c2397c07220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020423006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3020423006
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3765173519
Short name T705
Test name
Test status
Simulation time 429261208292 ps
CPU time 576.48 seconds
Started Apr 25 01:19:24 PM PDT 24
Finished Apr 25 01:29:03 PM PDT 24
Peak memory 213608 kb
Host smart-ef16e8df-d460-4630-969b-51a26eff2065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765173519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3765173519
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3670139491
Short name T756
Test name
Test status
Simulation time 316616955 ps
CPU time 1.32 seconds
Started Apr 25 01:19:34 PM PDT 24
Finished Apr 25 01:19:36 PM PDT 24
Peak memory 202004 kb
Host smart-108201db-9ded-4e55-b71c-e523c6632de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670139491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3670139491
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1828322122
Short name T460
Test name
Test status
Simulation time 162307681750 ps
CPU time 34.19 seconds
Started Apr 25 01:19:28 PM PDT 24
Finished Apr 25 01:20:04 PM PDT 24
Peak memory 202332 kb
Host smart-6e09d09d-8bbc-404b-b902-91c4c3b9b7fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828322122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1828322122
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3363331799
Short name T34
Test name
Test status
Simulation time 344656674265 ps
CPU time 418.32 seconds
Started Apr 25 01:19:27 PM PDT 24
Finished Apr 25 01:26:28 PM PDT 24
Peak memory 202284 kb
Host smart-83dc50c0-312f-4390-969e-60d1cfd914a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363331799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3363331799
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2221223438
Short name T317
Test name
Test status
Simulation time 320454471501 ps
CPU time 761.08 seconds
Started Apr 25 01:19:26 PM PDT 24
Finished Apr 25 01:32:10 PM PDT 24
Peak memory 202304 kb
Host smart-f60be354-00f8-4d74-90f2-34e3a6cad6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221223438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2221223438
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2559276455
Short name T761
Test name
Test status
Simulation time 490867030551 ps
CPU time 1183.66 seconds
Started Apr 25 01:19:30 PM PDT 24
Finished Apr 25 01:39:15 PM PDT 24
Peak memory 202272 kb
Host smart-19acb7de-8dcb-4ec7-b799-59496de535f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559276455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2559276455
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.368024583
Short name T4
Test name
Test status
Simulation time 495190618737 ps
CPU time 256.68 seconds
Started Apr 25 01:19:22 PM PDT 24
Finished Apr 25 01:23:42 PM PDT 24
Peak memory 202308 kb
Host smart-804863ae-64fd-4876-96ba-6c483f449707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368024583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.368024583
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3206676768
Short name T81
Test name
Test status
Simulation time 162951377654 ps
CPU time 78.66 seconds
Started Apr 25 01:19:30 PM PDT 24
Finished Apr 25 01:20:50 PM PDT 24
Peak memory 202368 kb
Host smart-12083cf1-1383-4f67-891b-c1a257698046
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206676768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3206676768
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.894293896
Short name T333
Test name
Test status
Simulation time 187524716037 ps
CPU time 403.48 seconds
Started Apr 25 01:19:30 PM PDT 24
Finished Apr 25 01:26:14 PM PDT 24
Peak memory 202356 kb
Host smart-64005880-ea64-4385-925a-cf439ef8ba19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894293896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.894293896
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.4019832301
Short name T755
Test name
Test status
Simulation time 391890825747 ps
CPU time 878.49 seconds
Started Apr 25 01:19:28 PM PDT 24
Finished Apr 25 01:34:08 PM PDT 24
Peak memory 202280 kb
Host smart-387b36f6-2b22-4de2-b0ce-d3f6f76f83b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019832301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.4019832301
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2629870818
Short name T564
Test name
Test status
Simulation time 83916718669 ps
CPU time 427.74 seconds
Started Apr 25 01:19:28 PM PDT 24
Finished Apr 25 01:26:38 PM PDT 24
Peak memory 202736 kb
Host smart-185bca51-5fa0-4793-a50f-272fa7593094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629870818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2629870818
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.362778532
Short name T707
Test name
Test status
Simulation time 34366604139 ps
CPU time 20.37 seconds
Started Apr 25 01:19:28 PM PDT 24
Finished Apr 25 01:19:50 PM PDT 24
Peak memory 202152 kb
Host smart-5318444f-dee6-4733-bd30-66d0fde729e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362778532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.362778532
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2337255005
Short name T120
Test name
Test status
Simulation time 3211584975 ps
CPU time 4.45 seconds
Started Apr 25 01:19:30 PM PDT 24
Finished Apr 25 01:19:35 PM PDT 24
Peak memory 202068 kb
Host smart-aa47d767-819b-46ca-a1bc-ccffc80f08f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337255005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2337255005
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1391420078
Short name T378
Test name
Test status
Simulation time 5601158897 ps
CPU time 16.33 seconds
Started Apr 25 01:19:22 PM PDT 24
Finished Apr 25 01:19:42 PM PDT 24
Peak memory 202136 kb
Host smart-9326c904-27f1-4a95-bb7e-5bf86c24224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391420078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1391420078
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2307475576
Short name T238
Test name
Test status
Simulation time 333256161499 ps
CPU time 176.72 seconds
Started Apr 25 01:19:32 PM PDT 24
Finished Apr 25 01:22:30 PM PDT 24
Peak memory 202288 kb
Host smart-40ed32f2-2dc5-4966-95ea-6317f11fe518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307475576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2307475576
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.173268020
Short name T237
Test name
Test status
Simulation time 138211966671 ps
CPU time 87.44 seconds
Started Apr 25 01:19:29 PM PDT 24
Finished Apr 25 01:20:58 PM PDT 24
Peak memory 210552 kb
Host smart-c4faea57-6f41-4109-b7bc-6a4fed4495ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173268020 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.173268020
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2575046568
Short name T411
Test name
Test status
Simulation time 399756961 ps
CPU time 0.87 seconds
Started Apr 25 01:20:03 PM PDT 24
Finished Apr 25 01:20:05 PM PDT 24
Peak memory 202012 kb
Host smart-73cbdb59-321f-471e-9bad-7101ef22ab19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575046568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2575046568
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1449868204
Short name T606
Test name
Test status
Simulation time 255308376890 ps
CPU time 314.76 seconds
Started Apr 25 01:19:51 PM PDT 24
Finished Apr 25 01:25:06 PM PDT 24
Peak memory 202308 kb
Host smart-5d64dbc3-9b1c-4ea6-9ff0-f8850accbd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449868204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1449868204
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4120322722
Short name T640
Test name
Test status
Simulation time 159562308479 ps
CPU time 360.13 seconds
Started Apr 25 01:19:43 PM PDT 24
Finished Apr 25 01:25:44 PM PDT 24
Peak memory 202176 kb
Host smart-f6cf8119-aaa1-468a-a136-e9de896b7486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120322722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4120322722
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1027118618
Short name T557
Test name
Test status
Simulation time 494809421465 ps
CPU time 1199.74 seconds
Started Apr 25 01:19:40 PM PDT 24
Finished Apr 25 01:39:42 PM PDT 24
Peak memory 202320 kb
Host smart-2347ed45-f409-4e19-ae00-dc3c237e83de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027118618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1027118618
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2655180241
Short name T311
Test name
Test status
Simulation time 164324942762 ps
CPU time 101.49 seconds
Started Apr 25 01:19:41 PM PDT 24
Finished Apr 25 01:21:24 PM PDT 24
Peak memory 202268 kb
Host smart-4cf23759-a218-41a4-804e-a9133b3eb302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655180241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2655180241
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.220167873
Short name T10
Test name
Test status
Simulation time 160263931365 ps
CPU time 390.76 seconds
Started Apr 25 01:19:37 PM PDT 24
Finished Apr 25 01:26:08 PM PDT 24
Peak memory 202344 kb
Host smart-8805fb0d-4d66-4ed1-9ce7-c6554b642ba2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=220167873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.220167873
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.272147276
Short name T596
Test name
Test status
Simulation time 353204512899 ps
CPU time 440.27 seconds
Started Apr 25 01:19:45 PM PDT 24
Finished Apr 25 01:27:06 PM PDT 24
Peak memory 202340 kb
Host smart-594b5874-5000-489a-a437-c563346020c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272147276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.272147276
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1437323410
Short name T723
Test name
Test status
Simulation time 202153615002 ps
CPU time 323.26 seconds
Started Apr 25 01:19:54 PM PDT 24
Finished Apr 25 01:25:18 PM PDT 24
Peak memory 202332 kb
Host smart-1e2716c1-0c39-4094-aaee-fb5acae85544
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437323410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1437323410
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2249132496
Short name T494
Test name
Test status
Simulation time 86742100611 ps
CPU time 317.26 seconds
Started Apr 25 01:19:56 PM PDT 24
Finished Apr 25 01:25:14 PM PDT 24
Peak memory 202612 kb
Host smart-57b8866c-2d84-4dd7-98b5-0038fbd95007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249132496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2249132496
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.700432177
Short name T346
Test name
Test status
Simulation time 46255860649 ps
CPU time 111.32 seconds
Started Apr 25 01:19:58 PM PDT 24
Finished Apr 25 01:21:50 PM PDT 24
Peak memory 202124 kb
Host smart-3a9df73a-b112-4784-bd7c-a7d89d27fe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700432177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.700432177
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.901004107
Short name T769
Test name
Test status
Simulation time 3724840904 ps
CPU time 1.24 seconds
Started Apr 25 01:19:50 PM PDT 24
Finished Apr 25 01:19:52 PM PDT 24
Peak memory 202200 kb
Host smart-79ac01e4-4f8a-45e2-844b-0a9a2310294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901004107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.901004107
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3012837858
Short name T366
Test name
Test status
Simulation time 5963408181 ps
CPU time 4.02 seconds
Started Apr 25 01:19:41 PM PDT 24
Finished Apr 25 01:19:46 PM PDT 24
Peak memory 202020 kb
Host smart-a19eb930-6232-410d-8185-326c5a7319e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012837858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3012837858
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.265623994
Short name T82
Test name
Test status
Simulation time 115221662746 ps
CPU time 337.2 seconds
Started Apr 25 01:19:57 PM PDT 24
Finished Apr 25 01:25:35 PM PDT 24
Peak memory 211080 kb
Host smart-beb0fb55-c942-49ef-890a-d2b57851fd95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265623994 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.265623994
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.4274403750
Short name T604
Test name
Test status
Simulation time 391882221 ps
CPU time 1.5 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:13:05 PM PDT 24
Peak memory 201988 kb
Host smart-cfd34032-0f16-4ce4-bc3d-9449f14b8003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274403750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.4274403750
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1035494619
Short name T708
Test name
Test status
Simulation time 162776477908 ps
CPU time 12.62 seconds
Started Apr 25 01:12:58 PM PDT 24
Finished Apr 25 01:13:11 PM PDT 24
Peak memory 202236 kb
Host smart-694c1df9-ba97-4d9c-99e8-130e965cbcdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035494619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1035494619
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2742405730
Short name T235
Test name
Test status
Simulation time 332708935509 ps
CPU time 428.86 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:20:09 PM PDT 24
Peak memory 202216 kb
Host smart-4a548fbf-7d96-4c6c-83bb-f3fb26b13aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742405730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2742405730
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.930052958
Short name T747
Test name
Test status
Simulation time 481654485355 ps
CPU time 1194.67 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:32:59 PM PDT 24
Peak memory 202280 kb
Host smart-51222aab-bec1-4c94-bc76-8a8a06f475b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930052958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.930052958
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.367403003
Short name T404
Test name
Test status
Simulation time 160400623758 ps
CPU time 385.52 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:19:25 PM PDT 24
Peak memory 202396 kb
Host smart-a7ecc49b-4a3a-4d17-bd0a-dda6ebf5dfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367403003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.367403003
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2209953612
Short name T651
Test name
Test status
Simulation time 168311381956 ps
CPU time 205.39 seconds
Started Apr 25 01:13:00 PM PDT 24
Finished Apr 25 01:16:26 PM PDT 24
Peak memory 202288 kb
Host smart-2e4766c5-091d-43cf-859d-4360119ec92d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209953612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2209953612
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1456228491
Short name T537
Test name
Test status
Simulation time 174640195472 ps
CPU time 209.64 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:16:30 PM PDT 24
Peak memory 202324 kb
Host smart-f7dc6418-c897-42f8-ab65-dc7f38159809
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456228491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1456228491
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.816858975
Short name T556
Test name
Test status
Simulation time 399454545586 ps
CPU time 471.08 seconds
Started Apr 25 01:13:01 PM PDT 24
Finished Apr 25 01:20:52 PM PDT 24
Peak memory 202304 kb
Host smart-c23f92f1-c623-486b-896a-8e37275b76c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816858975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.816858975
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1563014675
Short name T590
Test name
Test status
Simulation time 91917440980 ps
CPU time 361.97 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:19:13 PM PDT 24
Peak memory 202804 kb
Host smart-5fe9be22-e83a-4f33-b012-f50b3da00df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563014675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1563014675
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3168181240
Short name T457
Test name
Test status
Simulation time 39762069919 ps
CPU time 10.91 seconds
Started Apr 25 01:13:06 PM PDT 24
Finished Apr 25 01:13:17 PM PDT 24
Peak memory 202160 kb
Host smart-aa0177d0-ca9f-4972-88ff-7a957a60ce5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168181240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3168181240
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2781085370
Short name T650
Test name
Test status
Simulation time 5423884631 ps
CPU time 14.73 seconds
Started Apr 25 01:13:02 PM PDT 24
Finished Apr 25 01:13:17 PM PDT 24
Peak memory 202048 kb
Host smart-896607b0-7a47-4942-b931-5ceba4da4324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781085370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2781085370
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2499647919
Short name T59
Test name
Test status
Simulation time 8520010283 ps
CPU time 6.11 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:13:10 PM PDT 24
Peak memory 218868 kb
Host smart-a2102261-7307-4088-b546-eb23e28d65d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499647919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2499647919
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1635606269
Short name T675
Test name
Test status
Simulation time 6100650752 ps
CPU time 1.76 seconds
Started Apr 25 01:12:59 PM PDT 24
Finished Apr 25 01:13:01 PM PDT 24
Peak memory 202008 kb
Host smart-0f866fe4-ae44-4f1c-85fd-340223e4db30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635606269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1635606269
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.210068148
Short name T212
Test name
Test status
Simulation time 167384620562 ps
CPU time 204.46 seconds
Started Apr 25 01:13:05 PM PDT 24
Finished Apr 25 01:16:30 PM PDT 24
Peak memory 202364 kb
Host smart-f629708b-1129-41ef-bddf-032a4dd732a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210068148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.210068148
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1061838487
Short name T18
Test name
Test status
Simulation time 42109702985 ps
CPU time 180.74 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:16:05 PM PDT 24
Peak memory 211052 kb
Host smart-710e1671-c3cf-40fe-991b-39fe0131f7cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061838487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1061838487
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2460813684
Short name T523
Test name
Test status
Simulation time 439459247 ps
CPU time 1.59 seconds
Started Apr 25 01:20:14 PM PDT 24
Finished Apr 25 01:20:17 PM PDT 24
Peak memory 202000 kb
Host smart-981d70fb-182f-4c36-9517-3a6d2aba46ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460813684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2460813684
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2760168241
Short name T538
Test name
Test status
Simulation time 167422001264 ps
CPU time 413.77 seconds
Started Apr 25 01:20:06 PM PDT 24
Finished Apr 25 01:27:01 PM PDT 24
Peak memory 202336 kb
Host smart-868c8f6f-f630-46ba-a7d6-491b4fb19c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760168241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2760168241
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2082917963
Short name T421
Test name
Test status
Simulation time 169879949112 ps
CPU time 395.39 seconds
Started Apr 25 01:20:01 PM PDT 24
Finished Apr 25 01:26:38 PM PDT 24
Peak memory 202304 kb
Host smart-e9a4be56-8138-4287-ad23-374d55e66ba9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082917963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2082917963
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.92213008
Short name T328
Test name
Test status
Simulation time 163540170024 ps
CPU time 346.28 seconds
Started Apr 25 01:20:03 PM PDT 24
Finished Apr 25 01:25:50 PM PDT 24
Peak memory 202308 kb
Host smart-2cc467f8-b07e-4d31-bc53-8df790534c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92213008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.92213008
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1010912675
Short name T770
Test name
Test status
Simulation time 495112475775 ps
CPU time 307.61 seconds
Started Apr 25 01:20:03 PM PDT 24
Finished Apr 25 01:25:12 PM PDT 24
Peak memory 202280 kb
Host smart-633dc65a-625a-419b-ab40-ba03719b6b35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010912675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1010912675
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1182706306
Short name T267
Test name
Test status
Simulation time 542907629407 ps
CPU time 312.44 seconds
Started Apr 25 01:20:00 PM PDT 24
Finished Apr 25 01:25:14 PM PDT 24
Peak memory 202292 kb
Host smart-0aac74e7-f402-41e6-87f7-3ef82b092e5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182706306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1182706306
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3069595494
Short name T423
Test name
Test status
Simulation time 587883195972 ps
CPU time 324.53 seconds
Started Apr 25 01:20:02 PM PDT 24
Finished Apr 25 01:25:27 PM PDT 24
Peak memory 202336 kb
Host smart-e8264799-34b9-4dbc-8f33-954873cdb245
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069595494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3069595494
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1366176685
Short name T193
Test name
Test status
Simulation time 129474435239 ps
CPU time 406.01 seconds
Started Apr 25 01:20:08 PM PDT 24
Finished Apr 25 01:26:55 PM PDT 24
Peak memory 202652 kb
Host smart-55ffd9f3-eea0-4be3-900c-f396b2d082f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366176685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1366176685
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2497652535
Short name T487
Test name
Test status
Simulation time 44033366891 ps
CPU time 52.03 seconds
Started Apr 25 01:20:07 PM PDT 24
Finished Apr 25 01:21:00 PM PDT 24
Peak memory 202132 kb
Host smart-7a3c7ebc-3b9f-4e94-a6f0-b575cc52b144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497652535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2497652535
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.987908898
Short name T353
Test name
Test status
Simulation time 3152592330 ps
CPU time 4.82 seconds
Started Apr 25 01:20:08 PM PDT 24
Finished Apr 25 01:20:14 PM PDT 24
Peak memory 202132 kb
Host smart-d2f37265-4227-431f-a51f-ac881f02f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987908898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.987908898
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3728340809
Short name T570
Test name
Test status
Simulation time 5699885637 ps
CPU time 14.65 seconds
Started Apr 25 01:20:04 PM PDT 24
Finished Apr 25 01:20:20 PM PDT 24
Peak memory 202132 kb
Host smart-1416e3ab-d497-4512-a2d3-d6d7d4ae33e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728340809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3728340809
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.920390722
Short name T682
Test name
Test status
Simulation time 15879980064 ps
CPU time 35.66 seconds
Started Apr 25 01:20:12 PM PDT 24
Finished Apr 25 01:20:50 PM PDT 24
Peak memory 202528 kb
Host smart-0ad873cf-27a1-4e49-9141-caab84eda0db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920390722 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.920390722
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1013503040
Short name T475
Test name
Test status
Simulation time 319881063 ps
CPU time 1.29 seconds
Started Apr 25 01:20:24 PM PDT 24
Finished Apr 25 01:20:28 PM PDT 24
Peak memory 201960 kb
Host smart-a1f019c7-ec29-4261-a023-07aa33dcdfd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013503040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1013503040
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3923754562
Short name T664
Test name
Test status
Simulation time 169958958217 ps
CPU time 65.35 seconds
Started Apr 25 01:20:23 PM PDT 24
Finished Apr 25 01:21:29 PM PDT 24
Peak memory 202300 kb
Host smart-4ade4e55-dd46-48e6-9403-2e7ae6f2df4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923754562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3923754562
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2249098187
Short name T125
Test name
Test status
Simulation time 323115114827 ps
CPU time 127.26 seconds
Started Apr 25 01:20:12 PM PDT 24
Finished Apr 25 01:22:21 PM PDT 24
Peak memory 202248 kb
Host smart-6edb7edf-e322-4036-95d4-63b6b3b3bb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249098187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2249098187
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1614981641
Short name T376
Test name
Test status
Simulation time 164233069505 ps
CPU time 323.44 seconds
Started Apr 25 01:20:26 PM PDT 24
Finished Apr 25 01:25:51 PM PDT 24
Peak memory 202292 kb
Host smart-23114a8c-52e7-4116-86e7-be2c390907b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614981641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1614981641
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3218347752
Short name T142
Test name
Test status
Simulation time 163454321437 ps
CPU time 87.12 seconds
Started Apr 25 01:20:14 PM PDT 24
Finished Apr 25 01:21:42 PM PDT 24
Peak memory 202240 kb
Host smart-e2029dc7-723f-4afb-b14e-d8c0263aa048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218347752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3218347752
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2471698646
Short name T712
Test name
Test status
Simulation time 323060067351 ps
CPU time 180.45 seconds
Started Apr 25 01:20:13 PM PDT 24
Finished Apr 25 01:23:15 PM PDT 24
Peak memory 202296 kb
Host smart-b9f7e47b-9a47-4e71-8bce-0f258a18fd5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471698646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2471698646
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1162179088
Short name T519
Test name
Test status
Simulation time 385894914373 ps
CPU time 86.91 seconds
Started Apr 25 01:20:22 PM PDT 24
Finished Apr 25 01:21:50 PM PDT 24
Peak memory 202276 kb
Host smart-7aba135a-f179-419c-a9a2-2937983d8fc3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162179088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1162179088
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3752295225
Short name T338
Test name
Test status
Simulation time 103508148961 ps
CPU time 505.26 seconds
Started Apr 25 01:20:20 PM PDT 24
Finished Apr 25 01:28:47 PM PDT 24
Peak memory 202676 kb
Host smart-0958229c-dcdc-46b7-a0c2-97f6f3029703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752295225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3752295225
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1586287463
Short name T369
Test name
Test status
Simulation time 36685818435 ps
CPU time 19.06 seconds
Started Apr 25 01:20:25 PM PDT 24
Finished Apr 25 01:20:47 PM PDT 24
Peak memory 202144 kb
Host smart-d8cd9384-6565-45f4-8b99-dd15f0d7dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586287463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1586287463
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2743964707
Short name T622
Test name
Test status
Simulation time 4424417449 ps
CPU time 3.03 seconds
Started Apr 25 01:20:24 PM PDT 24
Finished Apr 25 01:20:30 PM PDT 24
Peak memory 202040 kb
Host smart-96731256-e051-46b8-9077-b20e11271aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743964707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2743964707
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1372587823
Short name T710
Test name
Test status
Simulation time 6260260011 ps
CPU time 1.5 seconds
Started Apr 25 01:20:13 PM PDT 24
Finished Apr 25 01:20:16 PM PDT 24
Peak memory 202092 kb
Host smart-4d73e89e-36bc-43b1-bc05-d96ec9ddd513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372587823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1372587823
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.164802402
Short name T678
Test name
Test status
Simulation time 408199987482 ps
CPU time 1137.82 seconds
Started Apr 25 01:20:26 PM PDT 24
Finished Apr 25 01:39:26 PM PDT 24
Peak memory 202672 kb
Host smart-6f3a876e-fc4e-4b3f-a852-e6430a3d23b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164802402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
164802402
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2157100945
Short name T686
Test name
Test status
Simulation time 23536276869 ps
CPU time 57.9 seconds
Started Apr 25 01:20:24 PM PDT 24
Finished Apr 25 01:21:25 PM PDT 24
Peak memory 210628 kb
Host smart-572b04e7-eb6d-4097-a223-d7605b676480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157100945 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2157100945
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3036336661
Short name T569
Test name
Test status
Simulation time 322193612 ps
CPU time 1.39 seconds
Started Apr 25 01:20:30 PM PDT 24
Finished Apr 25 01:20:33 PM PDT 24
Peak memory 201980 kb
Host smart-efad6f6e-fe04-4753-a051-7ff0fe448584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036336661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3036336661
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.597291448
Short name T483
Test name
Test status
Simulation time 167118993683 ps
CPU time 103.43 seconds
Started Apr 25 01:20:26 PM PDT 24
Finished Apr 25 01:22:12 PM PDT 24
Peak memory 202384 kb
Host smart-05230c97-d3e6-4bd0-947a-464aa29ed4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597291448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.597291448
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.588412914
Short name T388
Test name
Test status
Simulation time 319073935817 ps
CPU time 67.1 seconds
Started Apr 25 01:20:25 PM PDT 24
Finished Apr 25 01:21:34 PM PDT 24
Peak memory 202292 kb
Host smart-bd72c2b1-6049-48b7-a7fd-5eec7fc12ca2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=588412914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.588412914
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2061929314
Short name T160
Test name
Test status
Simulation time 480877219086 ps
CPU time 148.25 seconds
Started Apr 25 01:20:25 PM PDT 24
Finished Apr 25 01:22:56 PM PDT 24
Peak memory 202364 kb
Host smart-65ff0b91-6027-4734-8858-9e68d0f8373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061929314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2061929314
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2040282332
Short name T517
Test name
Test status
Simulation time 162085855568 ps
CPU time 358.98 seconds
Started Apr 25 01:20:27 PM PDT 24
Finished Apr 25 01:26:28 PM PDT 24
Peak memory 202288 kb
Host smart-f8db4c1e-e34a-4dfa-8c28-ed2629673334
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040282332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2040282332
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3850954388
Short name T656
Test name
Test status
Simulation time 620681213273 ps
CPU time 1381.19 seconds
Started Apr 25 01:20:24 PM PDT 24
Finished Apr 25 01:43:28 PM PDT 24
Peak memory 202364 kb
Host smart-6e0f9d81-8e20-483b-93ed-6a958c6fc560
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850954388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3850954388
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3901785083
Short name T21
Test name
Test status
Simulation time 198455324278 ps
CPU time 70.51 seconds
Started Apr 25 01:20:26 PM PDT 24
Finished Apr 25 01:21:39 PM PDT 24
Peak memory 202296 kb
Host smart-7eb03a11-1f42-4749-8364-41be28fa9657
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901785083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3901785083
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1836957630
Short name T539
Test name
Test status
Simulation time 126792083865 ps
CPU time 689.4 seconds
Started Apr 25 01:20:30 PM PDT 24
Finished Apr 25 01:32:01 PM PDT 24
Peak memory 202740 kb
Host smart-76c3b9a4-d088-428a-bc8a-069238ee95ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836957630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1836957630
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2616278640
Short name T626
Test name
Test status
Simulation time 23350951450 ps
CPU time 55.28 seconds
Started Apr 25 01:20:32 PM PDT 24
Finished Apr 25 01:21:30 PM PDT 24
Peak memory 202160 kb
Host smart-25a84dde-6704-47ef-a1bb-e63712ee2c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616278640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2616278640
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1570840912
Short name T779
Test name
Test status
Simulation time 3352547140 ps
CPU time 5.7 seconds
Started Apr 25 01:20:29 PM PDT 24
Finished Apr 25 01:20:36 PM PDT 24
Peak memory 202076 kb
Host smart-b429f820-1e60-4ff2-bfa8-4fab680169f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570840912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1570840912
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.6734193
Short name T763
Test name
Test status
Simulation time 5509444017 ps
CPU time 7.28 seconds
Started Apr 25 01:20:23 PM PDT 24
Finished Apr 25 01:20:33 PM PDT 24
Peak memory 202092 kb
Host smart-ea5d20d9-250b-43a0-9194-697111620d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6734193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.6734193
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.460188236
Short name T638
Test name
Test status
Simulation time 359719087886 ps
CPU time 208.09 seconds
Started Apr 25 01:20:29 PM PDT 24
Finished Apr 25 01:23:58 PM PDT 24
Peak memory 202332 kb
Host smart-03fe7ec8-b456-4e88-99f5-cde3433e306f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460188236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
460188236
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2255112797
Short name T36
Test name
Test status
Simulation time 58338506766 ps
CPU time 161.6 seconds
Started Apr 25 01:20:29 PM PDT 24
Finished Apr 25 01:23:12 PM PDT 24
Peak memory 211580 kb
Host smart-2921c88e-e45b-4bc7-8685-a48ca56eb11b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255112797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2255112797
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2426086341
Short name T415
Test name
Test status
Simulation time 438257056 ps
CPU time 1.6 seconds
Started Apr 25 01:20:43 PM PDT 24
Finished Apr 25 01:20:50 PM PDT 24
Peak memory 201896 kb
Host smart-85bf3b80-951f-485e-adb3-a12c532949ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426086341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2426086341
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2887429145
Short name T255
Test name
Test status
Simulation time 165496042497 ps
CPU time 124.8 seconds
Started Apr 25 01:20:43 PM PDT 24
Finished Apr 25 01:22:53 PM PDT 24
Peak memory 202272 kb
Host smart-7eee0752-e84c-4132-a254-0911bce75014
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887429145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2887429145
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.594576473
Short name T265
Test name
Test status
Simulation time 511334357952 ps
CPU time 101.97 seconds
Started Apr 25 01:20:43 PM PDT 24
Finished Apr 25 01:22:31 PM PDT 24
Peak memory 202292 kb
Host smart-d4874b73-59d1-442b-b4d1-dffb158356c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594576473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.594576473
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1624453101
Short name T293
Test name
Test status
Simulation time 163900736062 ps
CPU time 346.67 seconds
Started Apr 25 01:20:36 PM PDT 24
Finished Apr 25 01:26:28 PM PDT 24
Peak memory 202248 kb
Host smart-f1603e43-3daa-4ac9-944d-8cb51d2d50a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624453101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1624453101
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.462436390
Short name T502
Test name
Test status
Simulation time 493258749031 ps
CPU time 1123.36 seconds
Started Apr 25 01:20:35 PM PDT 24
Finished Apr 25 01:39:25 PM PDT 24
Peak memory 202260 kb
Host smart-73a87956-d807-4b82-8b3e-440d5f175f36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=462436390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.462436390
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.190150445
Short name T493
Test name
Test status
Simulation time 161897361890 ps
CPU time 82.04 seconds
Started Apr 25 01:20:38 PM PDT 24
Finished Apr 25 01:22:06 PM PDT 24
Peak memory 202188 kb
Host smart-54731369-11dd-4bda-b860-c0a869d7ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190150445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.190150445
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2799216095
Short name T466
Test name
Test status
Simulation time 496350803915 ps
CPU time 361.87 seconds
Started Apr 25 01:20:36 PM PDT 24
Finished Apr 25 01:26:44 PM PDT 24
Peak memory 202296 kb
Host smart-c24610dc-b306-415f-b47c-fc0dfe80879a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799216095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2799216095
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1591410541
Short name T565
Test name
Test status
Simulation time 196629214042 ps
CPU time 430.99 seconds
Started Apr 25 01:20:43 PM PDT 24
Finished Apr 25 01:27:59 PM PDT 24
Peak memory 202264 kb
Host smart-824e37dc-3cef-483f-beb0-31f3af8e6463
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591410541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1591410541
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.4239753523
Short name T486
Test name
Test status
Simulation time 78894701180 ps
CPU time 337.88 seconds
Started Apr 25 01:20:41 PM PDT 24
Finished Apr 25 01:26:25 PM PDT 24
Peak memory 202640 kb
Host smart-05c698b2-74e0-4f78-8fd4-e826f1196008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239753523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4239753523
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3933997627
Short name T645
Test name
Test status
Simulation time 33427153416 ps
CPU time 19 seconds
Started Apr 25 01:20:42 PM PDT 24
Finished Apr 25 01:21:07 PM PDT 24
Peak memory 202152 kb
Host smart-28bce6c9-1b1e-44d2-b8d0-a391b7852b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933997627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3933997627
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3551093019
Short name T580
Test name
Test status
Simulation time 3369583399 ps
CPU time 8.07 seconds
Started Apr 25 01:20:43 PM PDT 24
Finished Apr 25 01:20:57 PM PDT 24
Peak memory 202012 kb
Host smart-84d5263f-5be0-4234-8061-ec2f6619b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551093019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3551093019
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3843678882
Short name T354
Test name
Test status
Simulation time 6021380709 ps
CPU time 4.36 seconds
Started Apr 25 01:20:39 PM PDT 24
Finished Apr 25 01:20:49 PM PDT 24
Peak memory 202128 kb
Host smart-0120664f-5aa3-4307-82c5-1d4d3851acda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843678882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3843678882
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1546415412
Short name T291
Test name
Test status
Simulation time 501542909248 ps
CPU time 1614.33 seconds
Started Apr 25 01:20:44 PM PDT 24
Finished Apr 25 01:47:44 PM PDT 24
Peak memory 210892 kb
Host smart-a000ae03-87b6-46eb-9c02-1a0d8f58cebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546415412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1546415412
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1349936933
Short name T550
Test name
Test status
Simulation time 130963258370 ps
CPU time 48.13 seconds
Started Apr 25 01:20:42 PM PDT 24
Finished Apr 25 01:21:35 PM PDT 24
Peak memory 210720 kb
Host smart-4bc4e150-482d-45ce-b36f-15f1f9ffbd42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349936933 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1349936933
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1337694558
Short name T482
Test name
Test status
Simulation time 435483027 ps
CPU time 0.76 seconds
Started Apr 25 01:20:58 PM PDT 24
Finished Apr 25 01:21:00 PM PDT 24
Peak memory 202004 kb
Host smart-e7fc7cf8-3cbd-4064-9e52-fef1fd485f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337694558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1337694558
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3817818126
Short name T490
Test name
Test status
Simulation time 178632333909 ps
CPU time 412.32 seconds
Started Apr 25 01:20:55 PM PDT 24
Finished Apr 25 01:27:48 PM PDT 24
Peak memory 202384 kb
Host smart-4e83b679-184b-4f9c-bd04-5b73c8c99b33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817818126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3817818126
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.79058309
Short name T139
Test name
Test status
Simulation time 166809690783 ps
CPU time 42.26 seconds
Started Apr 25 01:20:53 PM PDT 24
Finished Apr 25 01:21:36 PM PDT 24
Peak memory 202292 kb
Host smart-049e97ea-9c32-4df5-a4b2-946aa82d7c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79058309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.79058309
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1116712285
Short name T549
Test name
Test status
Simulation time 330636012142 ps
CPU time 104.13 seconds
Started Apr 25 01:20:47 PM PDT 24
Finished Apr 25 01:22:36 PM PDT 24
Peak memory 202408 kb
Host smart-5baf949d-35e3-4988-97a0-1e61a1219914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116712285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1116712285
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1701715695
Short name T446
Test name
Test status
Simulation time 163039227381 ps
CPU time 104.18 seconds
Started Apr 25 01:20:47 PM PDT 24
Finished Apr 25 01:22:35 PM PDT 24
Peak memory 202292 kb
Host smart-7279d170-62b7-470b-b053-c63394b85bee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701715695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1701715695
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.760829655
Short name T791
Test name
Test status
Simulation time 493551967832 ps
CPU time 1082.91 seconds
Started Apr 25 01:20:45 PM PDT 24
Finished Apr 25 01:38:53 PM PDT 24
Peak memory 202356 kb
Host smart-cad78486-ff80-44cb-a269-69799420d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760829655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.760829655
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.432440860
Short name T343
Test name
Test status
Simulation time 485315004560 ps
CPU time 1195.08 seconds
Started Apr 25 01:20:47 PM PDT 24
Finished Apr 25 01:40:47 PM PDT 24
Peak memory 202224 kb
Host smart-65f2c42a-de46-4917-92cc-f70454fd6ce9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=432440860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.432440860
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1544079511
Short name T185
Test name
Test status
Simulation time 342818252058 ps
CPU time 219.46 seconds
Started Apr 25 01:20:53 PM PDT 24
Finished Apr 25 01:24:34 PM PDT 24
Peak memory 202272 kb
Host smart-0a0079d4-db5d-4f79-af5f-54fe43f1b33c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544079511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1544079511
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4239997705
Short name T588
Test name
Test status
Simulation time 192589021709 ps
CPU time 482 seconds
Started Apr 25 01:20:54 PM PDT 24
Finished Apr 25 01:28:57 PM PDT 24
Peak memory 202296 kb
Host smart-69f7778a-870d-4318-b5ab-176f9b440c87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239997705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4239997705
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1408986720
Short name T194
Test name
Test status
Simulation time 113541756542 ps
CPU time 374.6 seconds
Started Apr 25 01:20:57 PM PDT 24
Finished Apr 25 01:27:12 PM PDT 24
Peak memory 202716 kb
Host smart-b50b9719-2d70-40ee-b812-ba5094614675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408986720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1408986720
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1787979977
Short name T358
Test name
Test status
Simulation time 40279319468 ps
CPU time 25.18 seconds
Started Apr 25 01:20:51 PM PDT 24
Finished Apr 25 01:21:18 PM PDT 24
Peak memory 202084 kb
Host smart-94ac5c1f-b1f4-4e2e-a61c-621305c0fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787979977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1787979977
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.693173070
Short name T579
Test name
Test status
Simulation time 4852094437 ps
CPU time 13.41 seconds
Started Apr 25 01:20:52 PM PDT 24
Finished Apr 25 01:21:06 PM PDT 24
Peak memory 202072 kb
Host smart-3789dfcd-5e11-4ab7-bd4f-aed08e593367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693173070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.693173070
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1370355733
Short name T773
Test name
Test status
Simulation time 5994422866 ps
CPU time 13.39 seconds
Started Apr 25 01:20:42 PM PDT 24
Finished Apr 25 01:21:01 PM PDT 24
Peak memory 202132 kb
Host smart-8d6b1a55-9615-4e4e-96a8-684b596ae9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370355733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1370355733
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3500728347
Short name T216
Test name
Test status
Simulation time 377923281248 ps
CPU time 935.64 seconds
Started Apr 25 01:20:57 PM PDT 24
Finished Apr 25 01:36:33 PM PDT 24
Peak memory 202304 kb
Host smart-e7416a9d-4e26-4510-87ab-c09225a2f074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500728347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3500728347
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2477916640
Short name T33
Test name
Test status
Simulation time 86292153504 ps
CPU time 241.32 seconds
Started Apr 25 01:20:58 PM PDT 24
Finished Apr 25 01:25:00 PM PDT 24
Peak memory 211036 kb
Host smart-1695115a-af2c-444d-b0e6-8a778f462549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477916640 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2477916640
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1020842979
Short name T698
Test name
Test status
Simulation time 419345332 ps
CPU time 0.84 seconds
Started Apr 25 01:21:10 PM PDT 24
Finished Apr 25 01:21:11 PM PDT 24
Peak memory 202008 kb
Host smart-623587cd-8435-4edd-8648-d786d5711ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020842979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1020842979
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1898481237
Short name T218
Test name
Test status
Simulation time 490749312565 ps
CPU time 1032.47 seconds
Started Apr 25 01:20:58 PM PDT 24
Finished Apr 25 01:38:12 PM PDT 24
Peak memory 202304 kb
Host smart-4e9ffb51-54f7-4906-82c1-c0905d2e7938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898481237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1898481237
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.338467698
Short name T740
Test name
Test status
Simulation time 160360795657 ps
CPU time 103.96 seconds
Started Apr 25 01:21:23 PM PDT 24
Finished Apr 25 01:23:09 PM PDT 24
Peak memory 202324 kb
Host smart-27564a33-dfe3-4de5-bd1b-3a1e13d5930a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=338467698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.338467698
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2315584318
Short name T605
Test name
Test status
Simulation time 163850493445 ps
CPU time 41.43 seconds
Started Apr 25 01:20:58 PM PDT 24
Finished Apr 25 01:21:41 PM PDT 24
Peak memory 202332 kb
Host smart-45208738-bf66-4ba0-b0e4-e53b6a933b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315584318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2315584318
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3174201182
Short name T611
Test name
Test status
Simulation time 162494308302 ps
CPU time 395.49 seconds
Started Apr 25 01:20:58 PM PDT 24
Finished Apr 25 01:27:35 PM PDT 24
Peak memory 202292 kb
Host smart-f3d996fd-d133-4ac0-b780-6cd7c3d0d1a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174201182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3174201182
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1586244506
Short name T122
Test name
Test status
Simulation time 569405190075 ps
CPU time 708.28 seconds
Started Apr 25 01:21:04 PM PDT 24
Finished Apr 25 01:32:53 PM PDT 24
Peak memory 202264 kb
Host smart-8d88f780-3219-4161-bc5f-b6de879e1664
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586244506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1586244506
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1864097304
Short name T587
Test name
Test status
Simulation time 385859013823 ps
CPU time 850.7 seconds
Started Apr 25 01:21:02 PM PDT 24
Finished Apr 25 01:35:14 PM PDT 24
Peak memory 202292 kb
Host smart-0cad8dd0-11c5-414f-8295-61ea0744a02c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864097304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1864097304
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.566291532
Short name T533
Test name
Test status
Simulation time 135337975331 ps
CPU time 707.61 seconds
Started Apr 25 01:21:11 PM PDT 24
Finished Apr 25 01:32:59 PM PDT 24
Peak memory 202728 kb
Host smart-ac825c50-2f81-4143-8acb-7f9032deb4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566291532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.566291532
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3516739090
Short name T47
Test name
Test status
Simulation time 42107399625 ps
CPU time 25.61 seconds
Started Apr 25 01:21:09 PM PDT 24
Finished Apr 25 01:21:35 PM PDT 24
Peak memory 202088 kb
Host smart-61d4e0a1-be81-42cb-a7d5-38120457f618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516739090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3516739090
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.675176452
Short name T456
Test name
Test status
Simulation time 3177700352 ps
CPU time 2.39 seconds
Started Apr 25 01:21:10 PM PDT 24
Finished Apr 25 01:21:13 PM PDT 24
Peak memory 202136 kb
Host smart-3ef8df9d-fd84-406b-ba02-5b212b3404cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675176452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.675176452
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1788000486
Short name T403
Test name
Test status
Simulation time 5947117886 ps
CPU time 14.74 seconds
Started Apr 25 01:20:59 PM PDT 24
Finished Apr 25 01:21:15 PM PDT 24
Peak memory 202140 kb
Host smart-a075e550-da1f-474f-acd6-72790e20351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788000486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1788000486
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4071329854
Short name T303
Test name
Test status
Simulation time 399459418688 ps
CPU time 179.09 seconds
Started Apr 25 01:21:10 PM PDT 24
Finished Apr 25 01:24:10 PM PDT 24
Peak memory 202284 kb
Host smart-56a3e7a3-c93b-4af1-a7ac-38b255079025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071329854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4071329854
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1564987166
Short name T300
Test name
Test status
Simulation time 51814390622 ps
CPU time 113.27 seconds
Started Apr 25 01:21:09 PM PDT 24
Finished Apr 25 01:23:03 PM PDT 24
Peak memory 217472 kb
Host smart-b1023828-bb31-4dac-8531-69bba27ae873
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564987166 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1564987166
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2791428560
Short name T458
Test name
Test status
Simulation time 547978141 ps
CPU time 0.94 seconds
Started Apr 25 01:21:28 PM PDT 24
Finished Apr 25 01:21:30 PM PDT 24
Peak memory 201968 kb
Host smart-f80e69e6-1f55-4d00-a237-a2de8c4cd72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791428560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2791428560
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1347821987
Short name T138
Test name
Test status
Simulation time 536887982503 ps
CPU time 670.69 seconds
Started Apr 25 01:21:23 PM PDT 24
Finished Apr 25 01:32:36 PM PDT 24
Peak memory 202380 kb
Host smart-3a07e333-041b-40aa-a3e5-5f1acabf4ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347821987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1347821987
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.507238184
Short name T619
Test name
Test status
Simulation time 336348799203 ps
CPU time 203.77 seconds
Started Apr 25 01:21:24 PM PDT 24
Finished Apr 25 01:24:49 PM PDT 24
Peak memory 202288 kb
Host smart-510539da-fcf6-4913-bbf7-f58b491d0e57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=507238184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.507238184
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2740036990
Short name T274
Test name
Test status
Simulation time 501940479303 ps
CPU time 1046.21 seconds
Started Apr 25 01:21:19 PM PDT 24
Finished Apr 25 01:38:46 PM PDT 24
Peak memory 202276 kb
Host smart-9f2236bb-130c-4264-a9f9-50f807ac130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740036990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2740036990
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.169690627
Short name T535
Test name
Test status
Simulation time 488109072827 ps
CPU time 588.85 seconds
Started Apr 25 01:21:15 PM PDT 24
Finished Apr 25 01:31:04 PM PDT 24
Peak memory 202264 kb
Host smart-5b8b085f-d30c-49ea-b262-4d87e5da6900
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=169690627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.169690627
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1976474527
Short name T134
Test name
Test status
Simulation time 605613067357 ps
CPU time 1344.61 seconds
Started Apr 25 01:21:20 PM PDT 24
Finished Apr 25 01:43:46 PM PDT 24
Peak memory 202364 kb
Host smart-6179f65a-84bd-4440-8e41-7f0f87e5e71c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976474527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1976474527
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2836172532
Short name T151
Test name
Test status
Simulation time 424139851715 ps
CPU time 522.48 seconds
Started Apr 25 01:21:24 PM PDT 24
Finished Apr 25 01:30:07 PM PDT 24
Peak memory 202368 kb
Host smart-b8d4e196-00dc-42cd-bf72-2acb3126dae0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836172532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2836172532
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1499701992
Short name T679
Test name
Test status
Simulation time 123649597249 ps
CPU time 605.47 seconds
Started Apr 25 01:21:31 PM PDT 24
Finished Apr 25 01:31:37 PM PDT 24
Peak memory 202732 kb
Host smart-ad3c2344-6783-4825-841e-6861c367e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499701992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1499701992
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1051539866
Short name T558
Test name
Test status
Simulation time 29645450169 ps
CPU time 67.41 seconds
Started Apr 25 01:21:23 PM PDT 24
Finished Apr 25 01:22:32 PM PDT 24
Peak memory 202052 kb
Host smart-60642ff1-46b1-465c-a93a-d2390a634263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051539866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1051539866
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1422118634
Short name T119
Test name
Test status
Simulation time 3567706446 ps
CPU time 1.51 seconds
Started Apr 25 01:21:22 PM PDT 24
Finished Apr 25 01:21:25 PM PDT 24
Peak memory 202136 kb
Host smart-483e75e7-be5f-45b8-ad71-404ac1b2eba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422118634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1422118634
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3673619450
Short name T711
Test name
Test status
Simulation time 5572496192 ps
CPU time 12.33 seconds
Started Apr 25 01:21:16 PM PDT 24
Finished Apr 25 01:21:29 PM PDT 24
Peak memory 202068 kb
Host smart-a31795c8-fda7-4701-9732-9b5de2d49872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673619450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3673619450
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2287069115
Short name T66
Test name
Test status
Simulation time 26710517906 ps
CPU time 61.29 seconds
Started Apr 25 01:21:30 PM PDT 24
Finished Apr 25 01:22:32 PM PDT 24
Peak memory 202024 kb
Host smart-25bcd237-e0ce-4122-9ff6-345baab1a834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287069115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2287069115
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3084971311
Short name T251
Test name
Test status
Simulation time 125063535606 ps
CPU time 188.35 seconds
Started Apr 25 01:21:29 PM PDT 24
Finished Apr 25 01:24:38 PM PDT 24
Peak memory 211328 kb
Host smart-42761ccb-1c1b-447c-af88-87c8cdff5b73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084971311 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3084971311
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3056126941
Short name T559
Test name
Test status
Simulation time 453235827 ps
CPU time 1.74 seconds
Started Apr 25 01:21:38 PM PDT 24
Finished Apr 25 01:21:41 PM PDT 24
Peak memory 201988 kb
Host smart-e6447a23-a2fb-4148-aa33-ecb88162822d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056126941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3056126941
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3975415884
Short name T209
Test name
Test status
Simulation time 172276005169 ps
CPU time 217.7 seconds
Started Apr 25 01:21:34 PM PDT 24
Finished Apr 25 01:25:13 PM PDT 24
Peak memory 202192 kb
Host smart-7e497619-6982-4a67-9b5a-e5db17ca28d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975415884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3975415884
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.100250328
Short name T783
Test name
Test status
Simulation time 160695169805 ps
CPU time 97.71 seconds
Started Apr 25 01:21:34 PM PDT 24
Finished Apr 25 01:23:13 PM PDT 24
Peak memory 202308 kb
Host smart-24199fd5-7799-4818-9330-440e5fe48ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100250328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.100250328
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.422735422
Short name T384
Test name
Test status
Simulation time 495550429439 ps
CPU time 121.66 seconds
Started Apr 25 01:21:34 PM PDT 24
Finished Apr 25 01:23:36 PM PDT 24
Peak memory 202288 kb
Host smart-3a7d62b3-7579-4691-8892-2da2f0b62de4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=422735422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.422735422
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3465875477
Short name T325
Test name
Test status
Simulation time 163760625601 ps
CPU time 58.96 seconds
Started Apr 25 01:21:29 PM PDT 24
Finished Apr 25 01:22:28 PM PDT 24
Peak memory 202404 kb
Host smart-f284634d-c124-4f89-bea5-88ba6de2a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465875477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3465875477
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.927039168
Short name T444
Test name
Test status
Simulation time 335017252681 ps
CPU time 88.44 seconds
Started Apr 25 01:21:33 PM PDT 24
Finished Apr 25 01:23:03 PM PDT 24
Peak memory 202292 kb
Host smart-7471b50a-643d-4074-bdc8-ea0bd0fd4798
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=927039168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.927039168
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1068022187
Short name T242
Test name
Test status
Simulation time 408608620726 ps
CPU time 904.64 seconds
Started Apr 25 01:21:34 PM PDT 24
Finished Apr 25 01:36:40 PM PDT 24
Peak memory 202288 kb
Host smart-e0a5343f-ccc1-4c96-91d9-64a4e287eabb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068022187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1068022187
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2931407060
Short name T628
Test name
Test status
Simulation time 607253866004 ps
CPU time 744.29 seconds
Started Apr 25 01:21:33 PM PDT 24
Finished Apr 25 01:33:58 PM PDT 24
Peak memory 202260 kb
Host smart-0c8907da-5dc7-44d0-948a-13ae57845996
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931407060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2931407060
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1848996058
Short name T190
Test name
Test status
Simulation time 78892365360 ps
CPU time 236.16 seconds
Started Apr 25 01:21:40 PM PDT 24
Finished Apr 25 01:25:38 PM PDT 24
Peak memory 202660 kb
Host smart-2d9960c0-0e2a-482d-ae70-ff08790554ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848996058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1848996058
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.993069977
Short name T608
Test name
Test status
Simulation time 31436516729 ps
CPU time 47.52 seconds
Started Apr 25 01:21:38 PM PDT 24
Finished Apr 25 01:22:27 PM PDT 24
Peak memory 202076 kb
Host smart-5f43fb0b-f05c-441e-a09a-093a9ca6c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993069977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.993069977
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2754759814
Short name T473
Test name
Test status
Simulation time 4100320668 ps
CPU time 10.86 seconds
Started Apr 25 01:21:39 PM PDT 24
Finished Apr 25 01:21:52 PM PDT 24
Peak memory 202072 kb
Host smart-442d693c-25bb-4907-9ccf-85a809a52468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754759814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2754759814
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1471728936
Short name T676
Test name
Test status
Simulation time 6075284433 ps
CPU time 4.17 seconds
Started Apr 25 01:21:28 PM PDT 24
Finished Apr 25 01:21:33 PM PDT 24
Peak memory 202140 kb
Host smart-ac42e732-a4d3-475f-a4e2-768da9541d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471728936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1471728936
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2738976021
Short name T545
Test name
Test status
Simulation time 93835501819 ps
CPU time 262.6 seconds
Started Apr 25 01:21:40 PM PDT 24
Finished Apr 25 01:26:04 PM PDT 24
Peak memory 218948 kb
Host smart-2bbb4bc0-5af4-43c4-9f9f-79219f48957c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738976021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2738976021
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2757451304
Short name T198
Test name
Test status
Simulation time 341772344415 ps
CPU time 228.96 seconds
Started Apr 25 01:21:41 PM PDT 24
Finished Apr 25 01:25:31 PM PDT 24
Peak memory 217348 kb
Host smart-9e0b045a-1d0c-4e53-9be6-a2637c1e1f55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757451304 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2757451304
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2301970001
Short name T542
Test name
Test status
Simulation time 323810479 ps
CPU time 1.37 seconds
Started Apr 25 01:21:50 PM PDT 24
Finished Apr 25 01:21:52 PM PDT 24
Peak memory 202012 kb
Host smart-356ee3f6-bedb-428a-bedd-0820ee6eb7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301970001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2301970001
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1015756444
Short name T284
Test name
Test status
Simulation time 167955198469 ps
CPU time 409.42 seconds
Started Apr 25 01:21:47 PM PDT 24
Finished Apr 25 01:28:37 PM PDT 24
Peak memory 202308 kb
Host smart-eed36279-f4aa-497b-8336-473f52ce7110
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015756444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1015756444
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2064871915
Short name T331
Test name
Test status
Simulation time 161902392550 ps
CPU time 27.57 seconds
Started Apr 25 01:21:43 PM PDT 24
Finished Apr 25 01:22:12 PM PDT 24
Peak memory 202272 kb
Host smart-43fecdcc-b371-47b4-9ecb-52ec57d37851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064871915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2064871915
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2169196000
Short name T395
Test name
Test status
Simulation time 323198889720 ps
CPU time 68.97 seconds
Started Apr 25 01:21:46 PM PDT 24
Finished Apr 25 01:22:55 PM PDT 24
Peak memory 202228 kb
Host smart-fc0ae430-dbae-4e0b-be6c-ee634b095fbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169196000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2169196000
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1069211135
Short name T140
Test name
Test status
Simulation time 166981619401 ps
CPU time 102.6 seconds
Started Apr 25 01:21:40 PM PDT 24
Finished Apr 25 01:23:24 PM PDT 24
Peak memory 202368 kb
Host smart-b326e573-5603-4883-ba6e-d0d03d0a7892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069211135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1069211135
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.257543706
Short name T721
Test name
Test status
Simulation time 482999235790 ps
CPU time 296 seconds
Started Apr 25 01:21:45 PM PDT 24
Finished Apr 25 01:26:42 PM PDT 24
Peak memory 202252 kb
Host smart-0d29a440-454e-4cb7-b994-d183585357ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=257543706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.257543706
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2368045973
Short name T257
Test name
Test status
Simulation time 377707614677 ps
CPU time 965.39 seconds
Started Apr 25 01:21:43 PM PDT 24
Finished Apr 25 01:37:50 PM PDT 24
Peak memory 202276 kb
Host smart-23f17f4f-1d3d-4c2e-b4d0-e615e5bc619d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368045973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2368045973
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4153242199
Short name T467
Test name
Test status
Simulation time 588579196995 ps
CPU time 714.01 seconds
Started Apr 25 01:21:46 PM PDT 24
Finished Apr 25 01:33:41 PM PDT 24
Peak memory 202300 kb
Host smart-63ea5dee-d6e6-46ef-8c1d-a3954c0e5b9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153242199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4153242199
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2664605124
Short name T666
Test name
Test status
Simulation time 106820274818 ps
CPU time 431.81 seconds
Started Apr 25 01:21:52 PM PDT 24
Finished Apr 25 01:29:04 PM PDT 24
Peak memory 202728 kb
Host smart-6b0215d5-abe0-431e-b4c8-fa12811ca344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664605124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2664605124
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2902770029
Short name T152
Test name
Test status
Simulation time 42223400807 ps
CPU time 17.9 seconds
Started Apr 25 01:21:51 PM PDT 24
Finished Apr 25 01:22:10 PM PDT 24
Peak memory 202132 kb
Host smart-eb96fa4b-7c16-4e4c-ab35-8a33d6d4308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902770029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2902770029
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.344756153
Short name T700
Test name
Test status
Simulation time 2934039148 ps
CPU time 2.33 seconds
Started Apr 25 01:21:45 PM PDT 24
Finished Apr 25 01:21:48 PM PDT 24
Peak memory 202144 kb
Host smart-c5778345-f843-4140-a7b8-503bff3acaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344756153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.344756153
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1496650998
Short name T438
Test name
Test status
Simulation time 6097043568 ps
CPU time 4.42 seconds
Started Apr 25 01:21:39 PM PDT 24
Finished Apr 25 01:21:45 PM PDT 24
Peak memory 202132 kb
Host smart-ab7d0152-06d2-48fd-b8e1-e8b7140bbe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496650998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1496650998
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3602268122
Short name T659
Test name
Test status
Simulation time 335323341896 ps
CPU time 764.37 seconds
Started Apr 25 01:21:51 PM PDT 24
Finished Apr 25 01:34:36 PM PDT 24
Peak memory 202264 kb
Host smart-9ecbd02f-c361-4427-bf64-e29c98bba48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602268122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3602268122
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3729058856
Short name T16
Test name
Test status
Simulation time 298954272389 ps
CPU time 169.93 seconds
Started Apr 25 01:21:51 PM PDT 24
Finished Apr 25 01:24:42 PM PDT 24
Peak memory 218304 kb
Host smart-f871aa97-e347-4221-bafd-87cfe450937c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729058856 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3729058856
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.989196656
Short name T699
Test name
Test status
Simulation time 395649351 ps
CPU time 1.03 seconds
Started Apr 25 01:22:05 PM PDT 24
Finished Apr 25 01:22:07 PM PDT 24
Peak memory 202012 kb
Host smart-21cae52c-831b-4e45-8ecf-3811cb2ca525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989196656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.989196656
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3625216766
Short name T566
Test name
Test status
Simulation time 171203651644 ps
CPU time 61.48 seconds
Started Apr 25 01:22:01 PM PDT 24
Finished Apr 25 01:23:05 PM PDT 24
Peak memory 202332 kb
Host smart-4e3f98cd-3335-411a-932b-c2b82eeb1096
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625216766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3625216766
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2573563279
Short name T652
Test name
Test status
Simulation time 326312199790 ps
CPU time 743.17 seconds
Started Apr 25 01:21:57 PM PDT 24
Finished Apr 25 01:34:21 PM PDT 24
Peak memory 202252 kb
Host smart-2015e99e-ad69-4de0-89de-0fa39d942d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573563279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2573563279
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.61919723
Short name T529
Test name
Test status
Simulation time 320867610992 ps
CPU time 190.96 seconds
Started Apr 25 01:21:55 PM PDT 24
Finished Apr 25 01:25:08 PM PDT 24
Peak memory 202308 kb
Host smart-f131c314-c032-4f04-8980-47d90f515a0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=61919723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt
_fixed.61919723
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.626804186
Short name T506
Test name
Test status
Simulation time 159071780779 ps
CPU time 101.85 seconds
Started Apr 25 01:21:52 PM PDT 24
Finished Apr 25 01:23:34 PM PDT 24
Peak memory 202284 kb
Host smart-edcfc5a8-75d8-474b-a7da-da43339799d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626804186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.626804186
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.639695986
Short name T406
Test name
Test status
Simulation time 159831454956 ps
CPU time 379.75 seconds
Started Apr 25 01:21:56 PM PDT 24
Finished Apr 25 01:28:17 PM PDT 24
Peak memory 202236 kb
Host smart-0062dcc5-2ede-4d0c-b0e9-c1558b9fab4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=639695986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.639695986
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1750292428
Short name T164
Test name
Test status
Simulation time 553591950486 ps
CPU time 690.57 seconds
Started Apr 25 01:22:03 PM PDT 24
Finished Apr 25 01:33:36 PM PDT 24
Peak memory 202284 kb
Host smart-025531e7-9bef-43a6-9658-366769ab05af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750292428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1750292428
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3025044816
Short name T178
Test name
Test status
Simulation time 198490314625 ps
CPU time 431.25 seconds
Started Apr 25 01:21:56 PM PDT 24
Finished Apr 25 01:29:09 PM PDT 24
Peak memory 202360 kb
Host smart-7634105c-b50a-402b-9986-e15c3bf08921
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025044816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3025044816
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3731548458
Short name T646
Test name
Test status
Simulation time 131586473044 ps
CPU time 454.6 seconds
Started Apr 25 01:22:03 PM PDT 24
Finished Apr 25 01:29:39 PM PDT 24
Peak memory 202632 kb
Host smart-6c941877-187c-40f1-b828-dc09662ab03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731548458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3731548458
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1090579873
Short name T357
Test name
Test status
Simulation time 28493730243 ps
CPU time 61.36 seconds
Started Apr 25 01:22:02 PM PDT 24
Finished Apr 25 01:23:06 PM PDT 24
Peak memory 202160 kb
Host smart-22a1a983-ca60-47ad-921e-286d593315ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090579873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1090579873
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.4242674290
Short name T118
Test name
Test status
Simulation time 4791016101 ps
CPU time 3.77 seconds
Started Apr 25 01:22:03 PM PDT 24
Finished Apr 25 01:22:09 PM PDT 24
Peak memory 202128 kb
Host smart-317dbfce-6e22-4c07-8d07-c6ba2a18b8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242674290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.4242674290
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4108658815
Short name T634
Test name
Test status
Simulation time 5725593515 ps
CPU time 14.46 seconds
Started Apr 25 01:21:53 PM PDT 24
Finished Apr 25 01:22:08 PM PDT 24
Peak memory 202136 kb
Host smart-f8e234c7-79e8-448b-946b-c55e3e250fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108658815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4108658815
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4294092595
Short name T201
Test name
Test status
Simulation time 317642178454 ps
CPU time 1459.18 seconds
Started Apr 25 01:22:02 PM PDT 24
Finished Apr 25 01:46:24 PM PDT 24
Peak memory 211956 kb
Host smart-92a73199-b000-40c5-90c1-45da72ea1d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294092595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4294092595
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1344870799
Short name T655
Test name
Test status
Simulation time 524556682 ps
CPU time 1.72 seconds
Started Apr 25 01:13:08 PM PDT 24
Finished Apr 25 01:13:10 PM PDT 24
Peak memory 201972 kb
Host smart-d66c0a1b-3289-4340-be2d-7be3408f88fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344870799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1344870799
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1552662956
Short name T157
Test name
Test status
Simulation time 504629557203 ps
CPU time 262.38 seconds
Started Apr 25 01:13:05 PM PDT 24
Finished Apr 25 01:17:28 PM PDT 24
Peak memory 202312 kb
Host smart-72e97e90-fcdb-4b75-a7c2-d9f6583cc086
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552662956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1552662956
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1081236491
Short name T704
Test name
Test status
Simulation time 326264039880 ps
CPU time 204.76 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:16:29 PM PDT 24
Peak memory 202312 kb
Host smart-182a0d6b-8bde-4738-ad5b-5930b6903db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081236491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1081236491
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2775747492
Short name T287
Test name
Test status
Simulation time 167316687823 ps
CPU time 125.5 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:15:09 PM PDT 24
Peak memory 202388 kb
Host smart-4fb02464-b436-4fb1-9020-509b075e0e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775747492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2775747492
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2621199153
Short name T440
Test name
Test status
Simulation time 485195096584 ps
CPU time 757.9 seconds
Started Apr 25 01:13:04 PM PDT 24
Finished Apr 25 01:25:42 PM PDT 24
Peak memory 202320 kb
Host smart-ef206d99-366b-472e-98e4-b5a15c830978
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621199153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2621199153
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3724556620
Short name T489
Test name
Test status
Simulation time 327027781818 ps
CPU time 789.45 seconds
Started Apr 25 01:13:02 PM PDT 24
Finished Apr 25 01:26:12 PM PDT 24
Peak memory 202380 kb
Host smart-317e12a1-d810-4630-8683-ad26cf687e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724556620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3724556620
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.4197352710
Short name T419
Test name
Test status
Simulation time 323725375124 ps
CPU time 54.77 seconds
Started Apr 25 01:13:03 PM PDT 24
Finished Apr 25 01:13:58 PM PDT 24
Peak memory 202252 kb
Host smart-193a8ff8-93db-42f0-be6d-6ef81b36c1cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197352710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.4197352710
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2905778263
Short name T593
Test name
Test status
Simulation time 361491059583 ps
CPU time 736.21 seconds
Started Apr 25 01:13:04 PM PDT 24
Finished Apr 25 01:25:21 PM PDT 24
Peak memory 202308 kb
Host smart-5bc834b0-617a-4ee9-92c2-d684a1967cfe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905778263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2905778263
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1581868012
Short name T573
Test name
Test status
Simulation time 200784061536 ps
CPU time 478.56 seconds
Started Apr 25 01:13:05 PM PDT 24
Finished Apr 25 01:21:04 PM PDT 24
Peak memory 202372 kb
Host smart-9e3adb63-1ccf-4af4-b883-6f17143663e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581868012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1581868012
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1364228332
Short name T474
Test name
Test status
Simulation time 129187447843 ps
CPU time 667.66 seconds
Started Apr 25 01:13:09 PM PDT 24
Finished Apr 25 01:24:17 PM PDT 24
Peak memory 202680 kb
Host smart-8de1d39c-68a5-40e4-b0e7-b12be82c4d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364228332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1364228332
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.63667064
Short name T641
Test name
Test status
Simulation time 32525506679 ps
CPU time 32.77 seconds
Started Apr 25 01:13:04 PM PDT 24
Finished Apr 25 01:13:38 PM PDT 24
Peak memory 202156 kb
Host smart-825f9f54-093b-4776-8c71-ba9da4ff8f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63667064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.63667064
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3691257273
Short name T24
Test name
Test status
Simulation time 3129159400 ps
CPU time 7.85 seconds
Started Apr 25 01:13:02 PM PDT 24
Finished Apr 25 01:13:11 PM PDT 24
Peak memory 202124 kb
Host smart-c1f1e7d6-db42-4e8a-b376-689df600f25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691257273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3691257273
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1191242100
Short name T478
Test name
Test status
Simulation time 5799746713 ps
CPU time 13.28 seconds
Started Apr 25 01:13:02 PM PDT 24
Finished Apr 25 01:13:16 PM PDT 24
Peak memory 202148 kb
Host smart-6b05c34a-2d2e-4e60-bd0d-a3222ca709ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191242100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1191242100
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.117566054
Short name T555
Test name
Test status
Simulation time 273854045116 ps
CPU time 467.01 seconds
Started Apr 25 01:13:11 PM PDT 24
Finished Apr 25 01:20:59 PM PDT 24
Peak memory 202668 kb
Host smart-013eba5d-aa8b-4101-9701-a8ed607381e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117566054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.117566054
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2270951655
Short name T742
Test name
Test status
Simulation time 472083538 ps
CPU time 1.8 seconds
Started Apr 25 01:13:12 PM PDT 24
Finished Apr 25 01:13:14 PM PDT 24
Peak memory 201932 kb
Host smart-3b76afd4-e552-473e-abbf-90bc4b6caa38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270951655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2270951655
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3814087570
Short name T709
Test name
Test status
Simulation time 432470824191 ps
CPU time 389.14 seconds
Started Apr 25 01:13:11 PM PDT 24
Finished Apr 25 01:19:42 PM PDT 24
Peak memory 202260 kb
Host smart-7240aa37-2368-41d1-aa4e-2929f207533d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814087570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3814087570
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1473537330
Short name T674
Test name
Test status
Simulation time 376134917820 ps
CPU time 223.38 seconds
Started Apr 25 01:13:12 PM PDT 24
Finished Apr 25 01:16:56 PM PDT 24
Peak memory 202272 kb
Host smart-bb84e098-4880-44d0-a6b8-95c78a00685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473537330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1473537330
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2050309660
Short name T324
Test name
Test status
Simulation time 160226569490 ps
CPU time 140.71 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:15:31 PM PDT 24
Peak memory 202300 kb
Host smart-f5fb6f54-11ff-4fca-92e5-3b7903a6a7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050309660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2050309660
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3276513313
Short name T532
Test name
Test status
Simulation time 325964543533 ps
CPU time 821.89 seconds
Started Apr 25 01:13:08 PM PDT 24
Finished Apr 25 01:26:51 PM PDT 24
Peak memory 202284 kb
Host smart-4d5a29f1-ba06-4bd3-8ebc-982a16ea07df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276513313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3276513313
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3405084720
Short name T416
Test name
Test status
Simulation time 162418009120 ps
CPU time 95.82 seconds
Started Apr 25 01:13:12 PM PDT 24
Finished Apr 25 01:14:49 PM PDT 24
Peak memory 202316 kb
Host smart-194ec78c-d36a-404b-9871-cead5d59eb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405084720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3405084720
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3547297062
Short name T9
Test name
Test status
Simulation time 167553475409 ps
CPU time 403.3 seconds
Started Apr 25 01:13:11 PM PDT 24
Finished Apr 25 01:19:55 PM PDT 24
Peak memory 202356 kb
Host smart-8b95cf1c-0be7-4d60-95ae-8965dd5c86fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547297062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3547297062
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.789969970
Short name T431
Test name
Test status
Simulation time 187226647333 ps
CPU time 198.48 seconds
Started Apr 25 01:13:09 PM PDT 24
Finished Apr 25 01:16:28 PM PDT 24
Peak memory 202396 kb
Host smart-f07902e6-1907-4e7e-8160-53f2935d07bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789969970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.789969970
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.605798214
Short name T725
Test name
Test status
Simulation time 408108836462 ps
CPU time 226.42 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:16:58 PM PDT 24
Peak memory 202316 kb
Host smart-cc8e8ab5-5660-4c3f-b4ca-d4a487384d1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605798214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.605798214
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.75483171
Short name T586
Test name
Test status
Simulation time 95244513227 ps
CPU time 309.07 seconds
Started Apr 25 01:13:09 PM PDT 24
Finished Apr 25 01:18:18 PM PDT 24
Peak memory 202664 kb
Host smart-b26f57c8-9741-4d27-9bab-03909b453b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75483171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.75483171
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1265045904
Short name T393
Test name
Test status
Simulation time 45960637595 ps
CPU time 27.32 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:13:38 PM PDT 24
Peak memory 202128 kb
Host smart-8af79190-f36c-48df-8290-19cb33b753fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265045904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1265045904
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3042912245
Short name T172
Test name
Test status
Simulation time 5202238541 ps
CPU time 7.52 seconds
Started Apr 25 01:13:12 PM PDT 24
Finished Apr 25 01:13:21 PM PDT 24
Peak memory 202136 kb
Host smart-89862283-4b70-4ab6-9734-6a6006742600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042912245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3042912245
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.345706663
Short name T412
Test name
Test status
Simulation time 5772357245 ps
CPU time 4.22 seconds
Started Apr 25 01:13:39 PM PDT 24
Finished Apr 25 01:13:44 PM PDT 24
Peak memory 202076 kb
Host smart-e4c94617-3065-448f-bec2-b27a714b26c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345706663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.345706663
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3124546952
Short name T31
Test name
Test status
Simulation time 691721971350 ps
CPU time 902.23 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:28:13 PM PDT 24
Peak memory 202728 kb
Host smart-f7cc29ff-7c6e-406f-948e-5f9df359c905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124546952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3124546952
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4092710738
Short name T760
Test name
Test status
Simulation time 62827607004 ps
CPU time 37.55 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:13:49 PM PDT 24
Peak memory 202420 kb
Host smart-385bcad7-2504-40dd-8df9-ace15113a6b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092710738 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4092710738
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.211248009
Short name T702
Test name
Test status
Simulation time 592952995 ps
CPU time 0.67 seconds
Started Apr 25 01:13:15 PM PDT 24
Finished Apr 25 01:13:16 PM PDT 24
Peak memory 201944 kb
Host smart-7694840a-1414-4957-8ad5-016321014109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211248009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.211248009
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3939535106
Short name T207
Test name
Test status
Simulation time 324598294582 ps
CPU time 386.74 seconds
Started Apr 25 01:13:17 PM PDT 24
Finished Apr 25 01:19:44 PM PDT 24
Peak memory 202328 kb
Host smart-6561adcf-6052-4a05-92d1-0d20ac2913b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939535106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3939535106
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2952687635
Short name T132
Test name
Test status
Simulation time 327766364625 ps
CPU time 806.26 seconds
Started Apr 25 01:13:16 PM PDT 24
Finished Apr 25 01:26:43 PM PDT 24
Peak memory 202308 kb
Host smart-85e973d4-6f27-4dc9-9b9a-d2081ef2780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952687635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2952687635
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.515398278
Short name T182
Test name
Test status
Simulation time 497202871616 ps
CPU time 286.76 seconds
Started Apr 25 01:13:11 PM PDT 24
Finished Apr 25 01:17:58 PM PDT 24
Peak memory 202312 kb
Host smart-0133c339-b434-4b6c-9eac-e5ce0a5bf139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515398278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.515398278
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1158990298
Short name T511
Test name
Test status
Simulation time 163632573439 ps
CPU time 269.88 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:17:41 PM PDT 24
Peak memory 202372 kb
Host smart-520e1308-3bd8-4602-aa2d-147fdbef56ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158990298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1158990298
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3875379737
Short name T283
Test name
Test status
Simulation time 161184591119 ps
CPU time 131 seconds
Started Apr 25 01:13:10 PM PDT 24
Finished Apr 25 01:15:21 PM PDT 24
Peak memory 202256 kb
Host smart-a4da87c5-fdb8-4141-bf8a-f6921ae0ab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875379737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3875379737
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3243667887
Short name T408
Test name
Test status
Simulation time 325585213423 ps
CPU time 102.59 seconds
Started Apr 25 01:13:11 PM PDT 24
Finished Apr 25 01:14:54 PM PDT 24
Peak memory 202344 kb
Host smart-849ac7a1-46f1-4ebf-b2ef-d308cad354fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243667887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3243667887
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3680756745
Short name T270
Test name
Test status
Simulation time 598014416837 ps
CPU time 1307.72 seconds
Started Apr 25 01:13:11 PM PDT 24
Finished Apr 25 01:35:00 PM PDT 24
Peak memory 202268 kb
Host smart-63c2d83f-6cd5-4b9c-8767-465bddd4b03d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680756745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3680756745
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1716464826
Short name T735
Test name
Test status
Simulation time 406068340337 ps
CPU time 272.01 seconds
Started Apr 25 01:13:24 PM PDT 24
Finished Apr 25 01:17:56 PM PDT 24
Peak memory 202284 kb
Host smart-4b892b3c-a61b-438a-a836-c07d11652466
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716464826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1716464826
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.163131631
Short name T561
Test name
Test status
Simulation time 66667518946 ps
CPU time 278.02 seconds
Started Apr 25 01:13:14 PM PDT 24
Finished Apr 25 01:17:52 PM PDT 24
Peak memory 202664 kb
Host smart-6580ea4e-bf00-4816-a6ca-c5ec8d09b56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163131631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.163131631
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.552874566
Short name T697
Test name
Test status
Simulation time 45619152246 ps
CPU time 23.89 seconds
Started Apr 25 01:13:17 PM PDT 24
Finished Apr 25 01:13:41 PM PDT 24
Peak memory 202116 kb
Host smart-fbbfaf53-4584-43d6-974d-90e06d2efe90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552874566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.552874566
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.207527424
Short name T663
Test name
Test status
Simulation time 3252191457 ps
CPU time 1.23 seconds
Started Apr 25 01:13:14 PM PDT 24
Finished Apr 25 01:13:15 PM PDT 24
Peak memory 202024 kb
Host smart-cf758b9d-2fc7-4740-80a9-9d25cee44574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207527424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.207527424
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3771512324
Short name T689
Test name
Test status
Simulation time 5818454720 ps
CPU time 12.94 seconds
Started Apr 25 01:13:11 PM PDT 24
Finished Apr 25 01:13:25 PM PDT 24
Peak memory 202124 kb
Host smart-31bb5f8c-df0d-4139-a377-6eb0d19bb74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771512324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3771512324
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3028582043
Short name T424
Test name
Test status
Simulation time 162612037824 ps
CPU time 112.32 seconds
Started Apr 25 01:13:18 PM PDT 24
Finished Apr 25 01:15:10 PM PDT 24
Peak memory 202276 kb
Host smart-d3fe41d1-6354-4251-bee2-010deb7548fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028582043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3028582043
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2070071044
Short name T684
Test name
Test status
Simulation time 491863955 ps
CPU time 1.7 seconds
Started Apr 25 01:13:24 PM PDT 24
Finished Apr 25 01:13:26 PM PDT 24
Peak memory 202016 kb
Host smart-a62f13dc-7cf3-4177-a38e-973c91ab2f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070071044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2070071044
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.297398536
Short name T788
Test name
Test status
Simulation time 358864373343 ps
CPU time 212 seconds
Started Apr 25 01:13:23 PM PDT 24
Finished Apr 25 01:16:55 PM PDT 24
Peak memory 202300 kb
Host smart-85ba0c56-cbfe-40cc-8ad0-29d523c487cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297398536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.297398536
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.460156914
Short name T524
Test name
Test status
Simulation time 353329344955 ps
CPU time 691.19 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:24:51 PM PDT 24
Peak memory 202400 kb
Host smart-229ebdb4-658d-41a1-b2f9-17baf42d92a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460156914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.460156914
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2247756748
Short name T179
Test name
Test status
Simulation time 495024588400 ps
CPU time 272.62 seconds
Started Apr 25 01:13:17 PM PDT 24
Finished Apr 25 01:17:50 PM PDT 24
Peak memory 202324 kb
Host smart-099b7bd2-f246-42bb-a8e2-b36188445d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247756748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2247756748
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2656981772
Short name T410
Test name
Test status
Simulation time 483752576218 ps
CPU time 1082.53 seconds
Started Apr 25 01:13:20 PM PDT 24
Finished Apr 25 01:31:24 PM PDT 24
Peak memory 202280 kb
Host smart-216061fe-aa5b-458e-865d-f22b2a004777
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656981772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2656981772
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2223402266
Short name T643
Test name
Test status
Simulation time 498167170781 ps
CPU time 1160.86 seconds
Started Apr 25 01:13:17 PM PDT 24
Finished Apr 25 01:32:38 PM PDT 24
Peak memory 202320 kb
Host smart-9705c268-3dd0-4384-a6db-79d99c90918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223402266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2223402266
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2254776690
Short name T414
Test name
Test status
Simulation time 486366293497 ps
CPU time 1114.19 seconds
Started Apr 25 01:13:17 PM PDT 24
Finished Apr 25 01:31:52 PM PDT 24
Peak memory 202268 kb
Host smart-24bd8e9b-bb7c-4cd5-bcff-26ffd0596b18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254776690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2254776690
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1149859604
Short name T782
Test name
Test status
Simulation time 196579642017 ps
CPU time 140.23 seconds
Started Apr 25 01:13:16 PM PDT 24
Finished Apr 25 01:15:37 PM PDT 24
Peak memory 202344 kb
Host smart-76d86e23-e9ef-4a09-8923-981506da6940
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149859604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1149859604
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.663975665
Short name T585
Test name
Test status
Simulation time 597736251584 ps
CPU time 1402.56 seconds
Started Apr 25 01:13:16 PM PDT 24
Finished Apr 25 01:36:39 PM PDT 24
Peak memory 202368 kb
Host smart-97e02000-88b0-4711-a832-f84d87ee136f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663975665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.663975665
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1440432374
Short name T734
Test name
Test status
Simulation time 96112446202 ps
CPU time 303.06 seconds
Started Apr 25 01:13:21 PM PDT 24
Finished Apr 25 01:18:24 PM PDT 24
Peak memory 202608 kb
Host smart-69b1a926-bf59-4e22-8418-86500e9932d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440432374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1440432374
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.4157313524
Short name T174
Test name
Test status
Simulation time 39170006055 ps
CPU time 22.17 seconds
Started Apr 25 01:13:15 PM PDT 24
Finished Apr 25 01:13:37 PM PDT 24
Peak memory 202068 kb
Host smart-798c8774-3921-446d-b925-0de705b8580e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157313524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.4157313524
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3761380278
Short name T344
Test name
Test status
Simulation time 4004126660 ps
CPU time 3.2 seconds
Started Apr 25 01:13:17 PM PDT 24
Finished Apr 25 01:13:21 PM PDT 24
Peak memory 202084 kb
Host smart-17e09107-1676-44c8-a830-04571eab37bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761380278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3761380278
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.337797396
Short name T744
Test name
Test status
Simulation time 5769367393 ps
CPU time 7.69 seconds
Started Apr 25 01:13:17 PM PDT 24
Finished Apr 25 01:13:25 PM PDT 24
Peak memory 202088 kb
Host smart-924c3dbc-d7cb-4a61-be04-c1da4639d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337797396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.337797396
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1294953936
Short name T713
Test name
Test status
Simulation time 461341257 ps
CPU time 0.82 seconds
Started Apr 25 01:13:21 PM PDT 24
Finished Apr 25 01:13:22 PM PDT 24
Peak memory 201980 kb
Host smart-6f0ee9c8-459f-4914-b8af-192384587f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294953936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1294953936
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2815245380
Short name T272
Test name
Test status
Simulation time 322664363865 ps
CPU time 96.78 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:14:57 PM PDT 24
Peak memory 202284 kb
Host smart-ffde4e8f-0e6f-47ef-8a70-a46bdd757913
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815245380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2815245380
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3274940293
Short name T1
Test name
Test status
Simulation time 168467268599 ps
CPU time 199.1 seconds
Started Apr 25 01:13:23 PM PDT 24
Finished Apr 25 01:16:43 PM PDT 24
Peak memory 202328 kb
Host smart-86b982ee-b722-4252-93e3-a623620f4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274940293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3274940293
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3821741699
Short name T247
Test name
Test status
Simulation time 328918745810 ps
CPU time 392.08 seconds
Started Apr 25 01:13:24 PM PDT 24
Finished Apr 25 01:19:57 PM PDT 24
Peak memory 202320 kb
Host smart-857a84c0-1093-4c2d-9821-c0c6b87c9126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821741699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3821741699
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2543499246
Short name T391
Test name
Test status
Simulation time 329265858593 ps
CPU time 196.02 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:16:36 PM PDT 24
Peak memory 202272 kb
Host smart-fee1dd46-f342-48ee-9f64-64a8e206b8e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543499246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2543499246
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2882942120
Short name T654
Test name
Test status
Simulation time 169507440044 ps
CPU time 329.2 seconds
Started Apr 25 01:13:21 PM PDT 24
Finished Apr 25 01:18:51 PM PDT 24
Peak memory 202408 kb
Host smart-7321060a-a795-4222-97e0-1381d83a8ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882942120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2882942120
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.64798072
Short name T514
Test name
Test status
Simulation time 319149231571 ps
CPU time 172.03 seconds
Started Apr 25 01:13:21 PM PDT 24
Finished Apr 25 01:16:13 PM PDT 24
Peak memory 202376 kb
Host smart-d7f941f4-db78-4366-8c5d-0f1aa8cb5246
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=64798072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.64798072
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2393615415
Short name T38
Test name
Test status
Simulation time 589700836213 ps
CPU time 1491.7 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:38:12 PM PDT 24
Peak memory 202348 kb
Host smart-b0542b24-0b85-46a6-be20-5bb938695b61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393615415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2393615415
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1342218785
Short name T77
Test name
Test status
Simulation time 90895400702 ps
CPU time 533.56 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:22:13 PM PDT 24
Peak memory 202732 kb
Host smart-594fe4e4-5283-4ba6-9d47-ecff1937c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342218785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1342218785
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1815800026
Short name T592
Test name
Test status
Simulation time 25353239917 ps
CPU time 57.64 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:14:18 PM PDT 24
Peak memory 202092 kb
Host smart-fcf6f737-7e1b-4c4a-823b-59e028e00bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815800026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1815800026
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.833139433
Short name T150
Test name
Test status
Simulation time 2967102712 ps
CPU time 2.74 seconds
Started Apr 25 01:13:23 PM PDT 24
Finished Apr 25 01:13:27 PM PDT 24
Peak memory 202144 kb
Host smart-785e8834-14ef-47aa-b30a-a911c29d29b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833139433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.833139433
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2648569929
Short name T349
Test name
Test status
Simulation time 5755931673 ps
CPU time 13.58 seconds
Started Apr 25 01:13:19 PM PDT 24
Finished Apr 25 01:13:33 PM PDT 24
Peak memory 202108 kb
Host smart-37e4c580-e3fd-42f8-8496-e93d3261348d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648569929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2648569929
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4269098974
Short name T327
Test name
Test status
Simulation time 496815005159 ps
CPU time 1009.41 seconds
Started Apr 25 01:13:25 PM PDT 24
Finished Apr 25 01:30:15 PM PDT 24
Peak memory 202392 kb
Host smart-efb073aa-a965-487a-b9f9-c94822a5efd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269098974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4269098974
Directory /workspace/9.adc_ctrl_stress_all/latest
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