Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6571	1			T6	26		T9	11		T13	53
testmodes[AdcCtrlTestmodeNormal]	4986	1			T2	1		T3	3		T6	22
testmodes[AdcCtrlTestmodeLowpower]	5205	1			T1	20		T2	1		T4	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3694	1			T6	10		T9	7		T13	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1606	1			T6	7		T9	4		T13	8
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1167	1			T6	9		T13	26		T32	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1575	1			T6	5		T9	3		T13	11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1831	1			T3	2		T6	8		T8	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1243	1			T2	1		T6	8		T13	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1182	1			T6	11		T13	24		T32	9
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1231	1			T6	6		T13	26		T14	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2534	1			T1	19		T4	1		T5	2