Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21907

1

T1

20

T2

19

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3473

1

T3

12

T11

14

T14

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19004

1

T1

20

T3

16

T6

69

auto[1]

6376

1

T2

19

T3

3

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	406	1			T6	11		T13	7		T32	1
values[0]	96	1			T204	17		T143	1		T205	1
values[1]	781	1			T6	15		T163	3		T15	3
values[2]	3155	1			T2	10		T4	23		T5	36
values[3]	598	1			T3	4		T133	18		T134	1
values[4]	642	1			T133	12		T15	26		T130	39
values[5]	784	1			T26	1		T31	1		T51	2
values[6]	649	1			T3	3		T11	14		T51	22
values[7]	804	1			T3	12		T28	16		T134	1
values[8]	874	1			T14	6		T31	1		T134	1
values[9]	1167	1			T2	9		T11	10		T24	13
minimum	15424	1			T1	20		T6	69		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1090	1			T6	15		T163	3		T15	8
values[1]	2926	1			T2	10		T3	4		T4	23
values[2]	802	1			T133	18		T134	1		T15	26
values[3]	657	1			T133	12		T15	26		T137	1
values[4]	699	1			T11	14		T31	1		T51	2
values[5]	801	1			T3	15		T26	1		T51	22
values[6]	733	1			T14	6		T28	16		T134	1
values[7]	937	1			T133	27		T134	1		T136	1
values[8]	754	1			T2	9		T11	10		T24	13
values[9]	151	1			T156	1		T140	7		T205	1
minimum	15830	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	9		T163	3		T15	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T15	2		T206	1		T152	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T2	10		T3	1		T4	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T28	11		T31	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T133	9		T15	16		T139	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T134	1		T130	12		T140	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T15	14		T137	1		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T133	12		T130	1		T141	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T31	1		T138	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	14		T51	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	1		T51	8		T142	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T26	1		T207	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T28	16		T134	1		T51	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	4		T135	1		T142	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T133	16		T134	1		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T136	1		T37	3		T208	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	4		T11	10		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T24	1		T135	1		T167	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T156	1		T205	1		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T140	7		T210	10		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15686	1			T1	20		T6	79		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T6	6		T15	1		T39	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T15	3		T204	16		T212	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T3	3		T29	29		T213	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T214	1		T215	9		T216	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T133	9		T15	10		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T130	11		T204	8		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	12		T145	10		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T130	12		T80	5		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T138	8		T217	11		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T51	1		T38	7		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	2		T51	14		T142	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	11		T43	1		T91	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	12		T16	1		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	2		T135	13		T142	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T133	11		T38	9		T165	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	1		T33	15		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	5		T155	1		T218	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T24	12		T135	8		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T219	9		T220	9		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T210	14		T222	3		T223	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	406	1			T6	11		T13	7		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T143	1		T205	1		T90	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T204	1		T89	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	9		T163	3		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T206	1		T152	6		T143	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1767	1			T2	10		T4	23		T5	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	11		T31	1		T15	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T133	9		T15	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T134	1		T136	1		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	14		T130	13		T147	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T133	12		T130	1		T140	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T31	1		T137	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	1		T51	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	1		T51	8		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	14		T167	10		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T28	16		T134	1		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T135	1		T208	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T31	1		T134	1		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	4		T142	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T2	4		T11	10		T133	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T24	1		T135	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15280	1			T1	20		T6	68		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T224	1		T225	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T204	16		T89	13		T169	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	6		T15	1		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T212	7		T145	20		T226	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T29	29		T213	13		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	3		T227	1		T34	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	3		T133	9		T15	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T130	11		T204	8		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	12		T130	13		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T130	12		T17	1		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T138	8		T145	10		T41	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T51	1		T38	7		T165	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	2		T51	14		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	1		T91	14		T105	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T228	7		T149	10		T159	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	11		T135	13		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T51	12		T38	9		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	2		T142	11		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	5		T133	11		T155	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T24	12		T135	8		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T6	9		T163	1		T15	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T15	5		T206	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T2	1		T3	4		T4	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T28	1		T31	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T133	10		T15	13		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T134	1		T130	12		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	13		T137	1		T145	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T133	1		T130	13		T141	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T31	1		T138	9		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T51	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	3		T51	15		T142	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	12		T26	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T28	1		T134	1		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	5		T135	14		T142	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T133	12		T134	1		T38	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T136	1		T37	3		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	6		T11	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T24	13		T135	9		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T156	1		T205	1		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T140	1		T210	15		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15830	1			T1	20		T6	80		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	6		T163	2		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T152	5		T143	6		T212	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T2	9		T4	21		T5	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T28	10		T147	12		T214	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T133	8		T15	13		T139	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T130	11		T140	13		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	13		T145	11		T147	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T133	11		T17	3		T230	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T146	11		T217	12		T186	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	13		T167	9		T164	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T51	7		T142	12		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T207	3		T148	13		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	15		T51	10		T152	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	1		T142	11		T208	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T133	15		T38	6		T165	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T37	1		T208	6		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	3		T11	9		T155	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T167	12		T140	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T219	11		T220	13		T88	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T140	6		T210	9		T222	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	406	1			T6	11		T13	7		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T143	1		T205	1		T90	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T204	17		T89	14		T169	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	9		T163	1		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T206	1		T152	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T2	1		T4	2		T5	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T28	1		T31	1		T15	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	4		T133	10		T15	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T134	1		T136	1		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	13		T130	14		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T133	1		T130	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T31	1		T137	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	1		T51	2		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	3		T51	15		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T167	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T28	1		T134	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	12		T135	14		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T31	1		T134	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	5		T142	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T2	6		T11	1		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T24	13		T135	9		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15424	1			T1	20		T6	69		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T225	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T187	9		T232	8		T233	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	6		T163	2		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T152	5		T143	6		T212	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T2	9		T4	21		T5	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	10		T158	13		T215	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T133	8		T15	13		T234	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	11		T147	12		T235	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T15	13		T130	12		T147	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T133	11		T140	13		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T145	16		T146	11		T41	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T164	7		T38	8		T165	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	7		T142	12		T231	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	13		T167	9		T207	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T28	15		T152	4		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T208	7		T148	13		T104	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T51	10		T38	6		T165	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T142	11		T208	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	3		T11	9		T133	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T167	12		T37	1		T140	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21884

1

T1

20

T2

9

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3496

1

T2

10

T3

12

T11

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19280

1

T1

20

T2

19

T3

4

auto[1]

6100

1

T3

15

T4

23

T5

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	47	1			T236	33		T237	1		T238	13
values[0]	91	1			T157	1		T218	28		T239	13
values[1]	537	1			T2	10		T28	13		T51	23
values[2]	3117	1			T4	23		T5	36		T7	39
values[3]	619	1			T3	12		T6	15		T11	14
values[4]	716	1			T2	9		T134	1		T163	3
values[5]	815	1			T3	3		T31	1		T134	1
values[6]	673	1			T24	13		T136	1		T164	8
values[7]	685	1			T14	6		T28	11		T133	45
values[8]	987	1			T134	1		T15	26		T136	1
values[9]	1264	1			T3	4		T26	1		T28	16
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	839	1			T2	10		T28	13		T15	5
values[1]	3082	1			T4	23		T5	36		T6	15
values[2]	489	1			T3	12		T51	2		T136	1
values[3]	883	1			T2	9		T31	1		T133	12
values[4]	848	1			T3	3		T134	1		T15	3
values[5]	587	1			T14	6		T24	13		T136	1
values[6]	686	1			T28	11		T133	27		T51	22
values[7]	967	1			T31	2		T133	18		T134	1
values[8]	830	1			T3	4		T26	1		T28	16
values[9]	340	1			T15	26		T155	17		T231	12
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T28	13		T15	2		T140	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	10		T51	11		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1711	1			T4	23		T5	36		T6	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	24		T38	9		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T51	1		T37	3		T228	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	1		T136	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T2	4		T31	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T134	1		T138	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T3	1		T134	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	2		T231	12		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	1		T165	16		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	4		T136	1		T167	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T133	16		T137	1		T152	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T28	11		T51	8		T207	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T156	2		T15	14		T167	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T31	2		T133	9		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	1		T26	1		T28	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T135	1		T143	7		T144	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T155	16		T41	10		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T15	16		T231	12		T91	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	3		T16	1		T218	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T51	12		T144	9		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T6	6		T29	29		T213	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	7		T17	1		T242	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T51	1		T37	1		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	11		T165	14		T243	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	5		T38	9		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	8		T227	1		T78	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	2		T226	11		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	1		T228	10		T245	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	12		T165	10		T204	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	2		T138	10		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T133	11		T204	16		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T51	14		T243	12		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	12		T130	12		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T133	9		T130	24		T145	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	3		T139	11		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T135	13		T144	2		T246	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T155	1		T41	10		T96	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T15	10		T91	14		T247	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T236	17		T237	1		T238	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T218	14		T239	1		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T157	1		T249	10		T250	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T28	13		T140	7		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	10		T51	11		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T4	23		T5	36		T7	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	10		T38	9		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	9		T133	12		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	1		T11	14		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	4		T163	3		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T134	1		T15	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T3	1		T31	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T251	3		T245	11		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T24	1		T204	1		T192	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T136	1		T164	8		T231	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T133	16		T137	1		T165	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	4		T28	11		T133	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T15	14		T130	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T134	1		T136	1		T130	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T3	1		T26	1		T28	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	412	1			T31	2		T15	16		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T236	16		T238	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T218	14		T239	12		T248	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T250	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T16	1		T219	9		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T51	12		T144	9		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T29	29		T15	3		T213	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T38	7		T243	4		T253	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	6		T51	1		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	11		T165	14		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	5		T37	1		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	1		T138	8		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	2		T229	11		T243	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T251	3		T245	8		T83	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T24	12		T204	8		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T254	9		T159	17		T255	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T133	11		T165	10		T204	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	2		T133	9		T51	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	12		T130	12		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T130	13		T145	20		T246	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	3		T155	1		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T15	10		T135	13		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3