Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21892

1

T1

20

T2

9

T3

7

auto[ADC_CTRL_FILTER_COND_OUT]

3488

1

T2

10

T3

12

T11

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19267

1

T1

20

T2

19

T3

4

auto[1]

6113

1

T3

15

T4

23

T5

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T152	5		T143	7		T158	14
values[0]	24	1			T319	11		T248	13		-	-
values[1]	597	1			T2	10		T28	13		T51	23
values[2]	3086	1			T4	23		T5	36		T7	39
values[3]	664	1			T3	12		T6	15		T11	14
values[4]	746	1			T2	9		T134	1		T163	3
values[5]	726	1			T3	3		T31	1		T134	1
values[6]	710	1			T136	1		T164	8		T138	11
values[7]	703	1			T14	6		T24	13		T28	11
values[8]	941	1			T134	1		T156	1		T15	26
values[9]	1088	1			T3	4		T26	1		T28	16
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	682	1			T2	10		T15	5		T51	23
values[1]	3027	1			T4	23		T5	36		T7	39
values[2]	526	1			T3	12		T6	15		T133	12
values[3]	939	1			T2	9		T31	1		T134	1
values[4]	707	1			T3	3		T134	1		T208	7
values[5]	635	1			T14	6		T24	13		T136	1
values[6]	719	1			T28	11		T133	45		T51	22
values[7]	1009	1			T31	1		T134	1		T156	2
values[8]	853	1			T3	4		T26	1		T28	16
values[9]	261	1			T15	26		T155	17		T231	12
minimum	16022	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	2		T38	1		T140	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	10		T51	11		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T4	23		T5	36		T7	39
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	24		T38	9		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	9		T133	12		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	1		T136	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T2	4		T31	1		T163	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T134	1		T15	2		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T3	1		T134	1		T208	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T231	12		T240	1		T319	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T24	1		T204	1		T212	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	4		T136	1		T167	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T133	16		T137	1		T152	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T28	11		T133	9		T51	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T156	2		T15	14		T167	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T31	1		T134	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T26	1		T28	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T31	1		T135	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T155	16		T41	10		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T15	16		T231	12		T143	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15740	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T42	2		T319	11		T215	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T15	3		T16	1		T78	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	12		T144	9		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T29	29		T213	13		T135	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	7		T243	4		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	6		T51	1		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	11		T165	14		T34	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	5		T38	9		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	1		T138	8		T228	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	2		T226	11		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T242	19		T263	5		T188	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T24	12		T204	8		T212	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	2		T138	10		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T133	11		T165	10		T204	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T133	9		T51	14		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	12		T130	12		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T130	24		T145	20		T80	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	3		T139	11		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T135	13		T144	2		T246	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T155	1		T41	10		T330	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T15	10		T247	2		T331	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T215	17		T327	1		T289	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T152	5		T186	6		T98	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T143	7		T158	14		T81	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T248	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T319	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T28	13		T140	7		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	10		T51	11		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T4	23		T5	36		T7	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	10		T38	9		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	9		T133	12		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	1		T11	14		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T2	4		T163	3		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T134	1		T15	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	1		T31	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T245	11		T83	1		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T204	1		T192	11		T212	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T136	1		T164	8		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T24	1		T133	16		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	4		T28	11		T133	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T156	1		T15	14		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T134	1		T51	8		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T26	1		T28	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T31	2		T15	16		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T186	12		T98	1		T236	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T43	1		T247	2		T323	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T248	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T16	1		T218	14		T239	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T51	12		T144	9		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T29	29		T15	3		T213	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T38	7		T253	11		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	6		T51	1		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	11		T165	14		T243	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	5		T37	1		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	1		T138	8		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	2		T229	11		T243	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T245	8		T83	9		T214	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T204	8		T212	7		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T138	10		T251	3		T254	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T24	12		T133	11		T165	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T14	2		T133	9		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	12		T38	1		T210	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T51	14		T130	13		T145	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	3		T155	1		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T15	10		T135	13		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	5		T38	1		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T51	13		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T4	2		T5	3		T7	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	2		T38	8		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	9		T133	1		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	12		T136	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	6		T31	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T134	1		T15	2		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	3		T134	1		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T231	1		T240	1		T319	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	13		T204	9		T212	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	5		T136	1		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T133	12		T137	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	1		T133	10		T51	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T156	2		T15	13		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T31	1		T134	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	4		T26	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T31	1		T135	14		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T155	2		T41	16		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T15	13		T231	1		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15883	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T42	2		T319	1		T215	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T140	6		T208	7		T302	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	9		T51	10		T140	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T4	21		T5	33		T7	36
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	22		T38	8		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T6	6		T133	11		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T165	14		T192	16		T256	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T2	3		T163	2		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	1		T228	11		T245	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T208	6		T192	10		T207	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T231	11		T319	2		T263	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T212	9		T148	11		T168	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	1		T167	9		T164	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	15		T152	5		T165	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T28	10		T133	8		T51	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	13		T167	12		T218	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T130	23		T143	15		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T28	15		T139	10		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T144	8		T246	8		T158	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T155	15		T41	4		T332	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T15	13		T231	11		T143	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T28	12		T218	13		T219	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T319	10		T215	9		T22	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T152	1		T186	13		T98	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T143	1		T158	1		T81	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T248	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T319	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T28	1		T140	1		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	1		T51	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T4	2		T5	3		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	1		T38	8		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	9		T133	1		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	12		T11	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	6		T163	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T134	1		T15	2		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	3		T31	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T245	9		T83	10		T84	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T204	9		T192	1		T212	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T136	1		T164	1		T138	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T24	13		T133	12		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T14	5		T28	1		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T156	1		T15	13		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T134	1		T51	15		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T3	4		T26	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T31	2		T15	13		T135	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T152	4		T186	5		T98	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T143	6		T158	13		T43	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T319	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T28	12		T140	6		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	9		T51	10		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T4	21		T5	33		T7	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	9		T38	8		T231	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	6		T133	11		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T11	13		T165	14		T192	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	3		T163	2		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	1		T228	11		T78	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T208	6		T207	3		T148	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T245	10		T214	1		T274	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T192	10		T212	9		T148	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T164	7		T231	11		T251	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T133	15		T165	15		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	1		T28	10		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	13		T152	5		T218	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T51	7		T130	12		T207	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	15		T167	12		T155	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T15	13		T130	11		T231	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33