Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21561

1

T1

20

T2

10

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

3819

1

T2

9

T6

15

T11

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18508

1

T1

20

T2

9

T3

4

auto[1]

6872

1

T2

10

T3

15

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	572	1			T6	11		T13	7		T32	1
values[0]	42	1			T269	1		T205	1		T224	2
values[1]	840	1			T6	15		T163	3		T15	3
values[2]	3110	1			T2	10		T4	23		T5	36
values[3]	572	1			T3	4		T134	1		T136	1
values[4]	691	1			T133	18		T15	52		T130	39
values[5]	803	1			T26	1		T31	1		T133	12
values[6]	697	1			T3	3		T11	14		T51	22
values[7]	709	1			T3	12		T28	16		T134	1
values[8]	952	1			T14	6		T31	1		T134	1
values[9]	968	1			T2	9		T11	10		T24	13
minimum	15424	1			T1	20		T6	69		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	908	1			T6	15		T163	3		T15	5
values[1]	2937	1			T2	10		T3	4		T4	23
values[2]	720	1			T133	18		T134	1		T15	26
values[3]	594	1			T133	12		T15	26		T137	1
values[4]	830	1			T11	14		T26	1		T31	1
values[5]	735	1			T3	15		T51	22		T142	25
values[6]	751	1			T14	6		T28	16		T134	1
values[7]	950	1			T133	27		T134	1		T136	1
values[8]	827	1			T2	9		T11	10		T24	13
values[9]	87	1			T156	1		T140	7		T210	24
minimum	16041	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T163	3		T206	1		T321	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	9		T15	2		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T2	10		T3	1		T4	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T31	1		T156	1		T192	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T133	9		T15	16		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T134	1		T136	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	14		T137	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T133	12		T141	2		T228	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T31	1		T138	1		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	14		T26	1		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	2		T51	8		T142	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T231	12		T207	4		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	4		T28	16		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T134	1		T142	12		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T133	16		T37	3		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T134	1		T136	1		T208	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T31	1		T155	16		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	4		T11	10		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T156	1		T222	13		T219	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T140	7		T210	10		T333	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15747	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T152	6		T146	17		T302	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T227	1		T242	32		T89	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	6		T15	3		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T3	3		T29	29		T213	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T255	2		T214	1		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T133	9		T15	10		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	10		T130	24		T204	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T15	12		T130	12		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T228	10		T17	1		T43	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T138	8		T38	7		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T51	1		T41	10		T78	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	13		T51	14		T142	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T91	14		T306	12		T314	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	2		T135	13		T51	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T142	11		T16	1		T229	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T133	11		T37	1		T38	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T144	9		T147	8		T243	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T155	1		T218	14		T254	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	5		T24	12		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T222	3		T219	9		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T210	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T14	1		T15	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T96	5		T105	10		T257	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T6	11		T13	7		T32	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T140	12		T165	10		T228	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T269	1		T224	1		T187	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T205	1		T233	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T163	3		T15	2		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	9		T152	6		T39	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1680	1			T2	10		T4	23		T5	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T31	1		T156	1		T15	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T139	11		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	1		T136	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T133	9		T15	30		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T130	13		T141	2		T228	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T31	1		T137	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T26	1		T133	12		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	1		T51	8		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	14		T167	10		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T28	16		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T134	1		T152	5		T208	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	4		T31	1		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T134	1		T142	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T133	16		T156	1		T155	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	4		T11	10		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15280	1			T1	20		T6	68		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T243	4		T322	3		T221	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T165	13		T228	6		T312	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T224	1		T187	9		T225	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	1		T227	1		T242	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	6		T39	2		T204	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T29	29		T213	13		T334	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	3		T253	11		T255	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	3		T139	11		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T138	10		T130	11		T204	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T133	9		T15	22		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T130	13		T228	10		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T138	8		T38	7		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T51	1		T41	10		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	2		T51	14		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T78	14		T91	14		T105	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	11		T135	13		T149	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T229	11		T306	12		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	2		T51	12		T38	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T142	11		T16	1		T147	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T133	11		T155	1		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	5		T24	12		T135	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T163	1		T206	1		T321	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T6	9		T15	5		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T2	1		T3	4		T4	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T31	1		T156	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T133	10		T15	13		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T134	1		T136	1		T138	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	13		T137	1		T130	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	1		T141	2		T228	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T31	1		T138	9		T38	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T26	1		T51	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	15		T51	15		T142	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T231	1		T207	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	5		T28	1		T135	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T134	1		T142	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T133	12		T37	3		T38	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T134	1		T136	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T31	1		T155	2		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	6		T11	1		T24	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T156	1		T222	4		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T140	1		T210	15		T333	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15881	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T152	1		T146	1		T302	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T163	2		T104	14		T247	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	6		T39	1		T212	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T2	9		T4	21		T5	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T192	16		T147	12		T255	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T133	8		T15	13		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T130	23		T158	13		T235	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T15	13		T145	11		T147	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	11		T228	11		T298	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	8		T165	15		T145	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	13		T167	9		T164	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	7		T142	12		T192	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T231	11		T207	3		T148	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	1		T28	15		T51	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T142	11		T152	4		T208	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T133	15		T37	1		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T208	6		T231	6		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T155	15		T207	15		T218	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	3		T11	9		T167	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T222	12		T219	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T140	6		T210	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T15	1		T143	6		T158	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T152	5		T146	16		T302	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T6	11		T13	7		T32	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T140	1		T165	14		T228	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T269	1		T224	2		T187	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	1		T233	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T163	1		T15	2		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	9		T152	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T2	1		T4	2		T5	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T31	1		T156	1		T15	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	4		T139	12		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T134	1		T136	1		T138	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T133	10		T15	26		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	14		T141	2		T228	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T31	1		T137	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	1		T133	1		T51	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	3		T51	15		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T167	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	12		T28	1		T135	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T134	1		T152	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	5		T31	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T134	1		T142	12		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T133	12		T156	1		T155	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	6		T11	1		T24	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15424	1			T1	20		T6	69		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T335	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T140	11		T165	9		T228	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T187	9		T225	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T233	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T163	2		T15	1		T143	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	6		T152	5		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T2	9		T4	21		T5	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T192	16		T255	4		T215	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T139	10		T140	13		T261	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T130	11		T147	12		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T133	8		T15	26		T246	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T130	12		T228	11		T298	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	8		T165	15		T145	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T133	11		T164	7		T231	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T51	7		T142	12		T192	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	13		T167	9		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T28	15		T244	6		T98	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T152	4		T208	7		T148	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	1		T51	10		T38	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T142	11		T208	6		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T133	15		T155	15		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	3		T11	9		T167	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33