Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21609

1

T1

20

T2

19

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3771

1

T3

16

T11

14

T28

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18857

1

T1

20

T2

9

T3

19

auto[1]

6523

1

T2

10

T4

23

T5

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	307	1			T3	4		T156	1		T15	26
values[0]	31	1			T158	14		T34	5		T336	12
values[1]	757	1			T31	1		T134	2		T15	26
values[2]	815	1			T11	14		T14	6		T28	29
values[3]	711	1			T3	12		T6	15		T133	18
values[4]	889	1			T3	3		T31	1		T15	3
values[5]	579	1			T28	11		T133	27		T51	2
values[6]	747	1			T2	10		T11	10		T26	1
values[7]	615	1			T143	16		T207	4		T269	1
values[8]	3198	1			T4	23		T5	36		T7	39
values[9]	902	1			T2	9		T31	1		T133	12
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	739	1			T14	6		T28	13		T31	1
values[1]	818	1			T3	12		T11	14		T28	16
values[2]	833	1			T6	15		T133	18		T134	1
values[3]	801	1			T3	3		T28	11		T31	1
values[4]	622	1			T133	27		T136	1		T38	3
values[5]	682	1			T2	10		T11	10		T26	1
values[6]	3020	1			T4	23		T5	36		T7	39
values[7]	840	1			T2	9		T24	13		T15	5
values[8]	845	1			T3	4		T31	1		T133	12
values[9]	166	1			T15	26		T38	16		T157	1
minimum	16014	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	4		T31	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T28	13		T134	1		T15	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T28	16		T156	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T11	14		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	9		T133	9		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	4		T246	9		T228	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T28	11		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	2		T51	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	2		T142	13		T145	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	16		T136	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	10		T11	10		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T51	8		T167	10		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T4	23		T5	36		T7	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T130	13		T143	16		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	4		T24	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T15	2		T157	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T163	3		T136	1		T152	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	1		T31	1		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T157	1		T40	1		T218	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T15	16		T38	9		T208	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15745	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T302	2		T34	1		T188	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	2		T135	8		T142	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	12		T155	1		T130	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T138	10		T38	9		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	11		T16	1		T228	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	6		T133	9		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	1		T246	9		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	2		T51	12		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	1		T51	1		T138	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	1		T142	12		T145	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T133	11		T144	9		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T145	10		T43	1		T337	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T51	14		T37	1		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T29	29		T213	13		T334	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T130	13		T104	10		T105	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	5		T24	12		T243	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T15	3		T165	14		T251	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T165	10		T254	9		T159	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	3		T204	16		T218	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T267	4		T338	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T15	10		T38	7		T80	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T34	4		T188	5		T336	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T157	1		T40	1		T218	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T3	1		T156	1		T15	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T158	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T34	1		T336	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T31	1		T134	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T134	1		T15	14		T155	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	4		T28	16		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	14		T28	13		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T6	9		T133	9		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	1		T16	4		T228	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T31	1		T51	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	2		T138	1		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	11		T38	1		T212	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	16		T51	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	10		T11	10		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T51	8		T136	1		T167	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T207	4		T269	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T143	16		T148	6		T226	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1692	1			T4	23		T5	36		T7	39
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	2		T130	13		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	4		T163	3		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T31	1		T133	12		T206	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T254	9		T96	5		T267	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T3	3		T15	10		T38	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T34	4		T336	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T135	8		T142	11		T78	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	12		T155	1		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	2		T204	8		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T130	12		T16	1		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	6		T133	9		T135	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	11		T16	1		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	2		T51	12		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	1		T138	8		T165	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T212	7		T147	9		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T133	11		T51	1		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T38	1		T142	12		T145	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	14		T144	12		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T253	6		T17	1		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T226	10		T214	1		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T24	12		T29	29		T213	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T15	3		T130	13		T165	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	5		T165	10		T159	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T218	14		T229	11		T168	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	5		T31	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T28	1		T134	1		T15	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T28	1		T156	1		T138	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	12		T11	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	9		T133	10		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	4		T246	10		T228	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	3		T28	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T15	2		T51	2		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T38	3		T142	13		T145	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	12		T136	1		T144	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	1		T11	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T51	15		T167	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T4	2		T5	3		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T130	14		T143	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	6		T24	13		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T15	5		T157	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T163	1		T136	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T3	4		T31	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T157	1		T40	1		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T15	13		T38	8		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15874	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T302	1		T34	5		T188	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T142	11		T208	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T28	12		T15	13		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T28	15		T38	6		T140	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	13		T143	6		T145	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	6		T133	8		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T16	1		T246	8		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T28	10		T51	10		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	1		T165	9		T231	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T142	12		T145	12		T146	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T133	15		T244	11		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T2	9		T11	9		T140	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T51	7		T167	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T4	21		T5	33		T7	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T130	12		T143	15		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	3		T231	11		T207	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T165	14		T231	11		T251	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T163	2		T152	5		T165	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T133	11		T218	13		T255	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T218	7		T265	2		T267	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T15	13		T38	8		T208	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T158	13		T234	10		T274	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T302	1		T188	8		T336	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T157	1		T40	1		T218	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	4		T156	1		T15	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T158	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T34	5		T336	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	1		T134	1		T135	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T134	1		T15	13		T155	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	5		T28	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T28	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	9		T133	10		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	12		T16	4		T228	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	3		T31	1		T51	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	2		T138	9		T165	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T28	1		T38	1		T212	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T133	12		T51	2		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	1		T11	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T51	15		T136	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T207	1		T269	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T143	1		T148	1		T226	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T4	2		T5	3		T7	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T15	5		T130	14		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	6		T163	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T31	1		T133	1		T206	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T218	7		T254	13		T319	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T15	13		T38	8		T266	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T158	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T336	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T142	11		T208	7		T192	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	13		T155	15		T192	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T28	15		T140	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	13		T28	12		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	6		T133	8		T167	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T16	1		T228	7		T210	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T51	10		T139	10		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T165	9		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T28	10		T212	9		T146	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T133	15		T37	1		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	9		T11	9		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T51	7		T167	9		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T207	3		T146	11		T158	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T143	15		T148	5		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T4	21		T5	33		T7	36
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T130	12		T165	14		T251	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	3		T163	2		T152	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T133	11		T208	6		T231	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33