Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19457

1

T1

20

T3

15

T6

80

auto[ADC_CTRL_FILTER_COND_OUT]

5923

1

T2

19

T3

4

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19051

1

T1

20

T2

19

T6

80

auto[1]

6329

1

T3

19

T4

23

T5

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	256	1			T31	1		T142	23		T140	12
values[0]	54	1			T26	1		T327	11		T304	10
values[1]	848	1			T31	2		T133	27		T156	1
values[2]	638	1			T2	9		T3	4		T11	10
values[3]	626	1			T28	16		T134	1		T163	3
values[4]	740	1			T133	30		T136	1		T164	8
values[5]	733	1			T2	10		T28	24		T135	9
values[6]	783	1			T3	15		T51	2		T167	13
values[7]	709	1			T157	1		T165	29		T218	8
values[8]	794	1			T15	3		T138	9		T38	1
values[9]	3370	1			T4	23		T5	36		T6	15
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	904	1			T3	4		T31	2		T133	27
values[1]	2818	1			T2	9		T4	23		T5	36
values[2]	679	1			T28	16		T134	1		T156	1
values[3]	759	1			T28	13		T133	30		T135	9
values[4]	725	1			T2	10		T28	11		T136	1
values[5]	683	1			T3	15		T51	2		T167	13
values[6]	809	1			T157	1		T165	29		T208	7
values[7]	882	1			T6	15		T15	3		T138	9
values[8]	840	1			T11	14		T14	6		T24	13
values[9]	209	1			T31	1		T142	23		T141	1
minimum	16072	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T31	1		T133	16		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T3	1		T31	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T163	3		T15	2		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1609	1			T2	4		T4	23		T5	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T28	16		T134	1		T164	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T156	1		T152	11		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T133	21		T51	8		T142	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	13		T135	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T28	11		T136	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	10		T130	13		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	2		T167	13		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	1		T130	1		T192	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T208	7		T158	14		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T157	1		T165	15		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T15	2		T140	7		T231	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	9		T138	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	14		T14	4		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	14		T137	1		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T141	1		T165	16		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T31	1		T142	12		T192	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15715	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T26	1		T158	7		T148	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T133	11		T135	13		T16	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	3		T51	12		T159	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	3		T138	10		T92	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	987	1			T2	5		T29	29		T213	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T251	3		T228	10		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T228	6		T210	7		T86	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T133	9		T51	14		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T135	8		T145	30		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	1		T38	7		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T130	13		T204	16		T246	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	13		T38	9		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T51	1		T130	12		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T78	6		T83	8		T235	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T165	14		T17	1		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	1		T33	15		T78	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	6		T138	8		T218	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	2		T24	12		T15	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	12		T130	11		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T165	10		T149	2		T78	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T142	11		T80	5		T105	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T300	9		T259	10		T239	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T101	3		T274	3		T326	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T31	1		T142	12		T140	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T327	1		T304	1		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T26	1		T307	1		T260	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T31	1		T133	16		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T31	1		T156	1		T51	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T134	1		T138	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	4		T3	1		T11	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	16		T134	1		T163	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T156	1		T152	5		T146	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T133	21		T164	8		T142	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	1		T152	6		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	11		T51	8		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	10		T28	13		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	2		T167	13		T38	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T51	1		T130	1		T192	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T218	8		T158	14		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T157	1		T165	15		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T15	2		T140	7		T208	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T138	1		T38	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T11	14		T14	4		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1726	1			T4	23		T5	36		T6	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T101	1		T274	13		T326	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T142	11		T105	10		T316	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T327	10		T304	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T307	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T133	11		T135	13		T139	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T51	12		T159	17		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T138	10		T261	6		T92	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	5		T3	3		T226	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	3		T251	3		T227	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T228	6		T149	19		T210	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T133	9		T142	12		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T145	30		T243	12		T226	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T51	14		T37	1		T38	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T135	8		T130	13		T204	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	13		T38	9		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T51	1		T130	12		T212	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T245	8		T78	6		T83	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T165	14		T147	8		T210	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	1		T33	15		T78	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T138	8		T17	1		T43	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T14	2		T24	12		T15	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1039	1			T6	6		T29	29		T15	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T31	1		T133	12		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	4		T31	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T163	1		T15	5		T138	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1324	1			T2	6		T4	2		T5	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T28	1		T134	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	1		T152	2		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T133	11		T51	15		T142	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T28	1		T135	9		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T28	1		T136	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T130	14		T204	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	15		T167	1		T38	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T51	2		T130	13		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T208	1		T158	1		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T157	1		T165	15		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T15	2		T140	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	9		T138	9		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	1		T14	5		T24	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	13		T137	1		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T141	1		T165	11		T149	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T31	1		T142	12		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15886	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T26	1		T158	1		T148	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T133	15		T140	13		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T51	10		T192	8		T146	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T163	2		T190	2		T262	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1272	1			T2	3		T4	21		T5	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T28	15		T164	7		T251	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T152	9		T146	16		T228	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T133	19		T51	7		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T28	12		T167	9		T145	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T28	10		T37	1		T38	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	9		T130	12		T246	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T167	12		T38	6		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T192	16		T143	6		T212	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T208	6		T158	13		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T165	14		T17	3		T234	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	1		T140	6		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	6		T231	11		T207	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	13		T14	1		T15	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	13		T130	11		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T165	15		T78	12		T249	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T142	11		T192	10		T105	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T139	10		T41	4		T339	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T158	6		T148	13		T259	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T101	4		T274	14		T326	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T31	1		T142	12		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T327	11		T304	10		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T26	1		T307	15		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T31	1		T133	12		T135	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T31	1		T156	1		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T134	1		T138	11		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	6		T3	4		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T28	1		T134	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T156	1		T152	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T133	11		T164	1		T142	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T136	1		T152	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T28	1		T51	15		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	1		T28	1		T135	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	15		T167	1		T38	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T51	2		T130	13		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T218	1		T158	1		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T157	1		T165	15		T147	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	2		T140	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T138	9		T38	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T11	1		T14	5		T24	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1396	1			T4	2		T5	3		T6	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T274	2		T326	9		T18	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T142	11		T140	11		T105	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T260	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T133	15		T139	10		T140	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	10		T192	8		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T145	5		T261	12		T190	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	3		T11	9		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T28	15		T163	2		T251	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T152	4		T146	16		T228	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T133	19		T164	7		T142	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T152	5		T145	23		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T28	10		T51	7		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	9		T28	12		T167	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T167	12		T38	6		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T192	16		T143	6		T212	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T218	7		T158	13		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T165	14		T210	9		T264	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	1		T140	6		T208	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T231	11		T17	3		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	13		T14	1		T15	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1369	1			T4	21		T5	33		T6	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33