Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21896

1

T1

20

T2

19

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3484

1

T3

7

T14

6

T26

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19207

1

T1

20

T2

19

T6

95

auto[1]

6173

1

T3

19

T4

23

T5

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	66	1			T3	4		T145	33		T323	8
values[0]	25	1			T321	1		T340	1		T261	1
values[1]	586	1			T28	13		T135	9		T167	13
values[2]	693	1			T3	12		T31	1		T134	1
values[3]	732	1			T2	9		T133	12		T136	1
values[4]	788	1			T3	3		T31	1		T135	14
values[5]	3074	1			T4	23		T5	36		T7	39
values[6]	693	1			T11	10		T134	1		T163	3
values[7]	683	1			T26	1		T28	16		T133	27
values[8]	754	1			T6	15		T11	14		T15	3
values[9]	1457	1			T2	10		T14	6		T24	13
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T28	13		T31	1		T134	1
values[1]	759	1			T2	9		T3	12		T136	1
values[2]	636	1			T3	3		T133	12		T135	14
values[3]	3197	1			T4	23		T5	36		T7	39
values[4]	636	1			T133	18		T134	1		T136	1
values[5]	669	1			T11	10		T163	3		T156	1
values[6]	898	1			T6	15		T26	1		T28	16
values[7]	672	1			T15	3		T51	2		T38	2
values[8]	1125	1			T2	10		T3	4		T11	14
values[9]	172	1			T137	1		T157	1		T39	5
minimum	15868	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	13		T31	1		T167	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T134	1		T135	1		T38	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	4		T3	1		T167	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T136	1		T165	15		T218	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	1		T130	13		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	1		T133	12		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1740	1			T4	23		T5	36		T7	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T139	11		T152	5		T207	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T133	9		T134	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T164	8		T152	6		T192	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	10		T156	1		T15	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T163	3		T15	14		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T6	9		T28	16		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	1		T133	16		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	2		T251	3		T245	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	1		T38	1		T140	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	10		T11	14		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	1		T14	4		T28	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T137	1		T157	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T143	16		T169	1		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15702	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T274	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	9		T144	9		T243	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T135	8		T38	7		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	5		T3	11		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T165	14		T234	18		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T130	13		T217	11		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	2		T135	13		T80	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T29	29		T213	13		T155	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T139	11		T147	9		T149	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T133	9		T227	1		T89	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T246	9		T210	7		T92	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	10		T51	14		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	12		T37	1		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	6		T165	13		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	11		T138	10		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	1		T251	3		T245	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T51	1		T38	1		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T24	12		T15	3		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	3		T14	2		T51	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T39	2		T261	6		T316	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T169	11		T324	12		T220	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T274	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T145	13		T323	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T3	1		T341	15		T22	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T321	1		T340	1		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	13		T167	13		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	1		T38	9		T140	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	1		T31	1		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T134	1		T136	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T2	4		T136	1		T167	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T133	12		T157	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T31	1		T155	16		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T3	1		T135	1		T152	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T4	23		T5	36		T7	39
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T164	8		T139	11		T152	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	10		T134	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T163	3		T15	14		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T28	16		T165	10		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	1		T133	16		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T6	9		T11	14		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T206	1		T138	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	396	1			T2	10		T24	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T14	4		T28	11		T51	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T145	20		T323	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T3	3		T341	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T183	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T306	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T144	9		T243	12		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T135	8		T38	7		T228	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	11		T38	9		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T165	14		T80	5		T234	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	5		T130	13		T218	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T224	1		T342	1		T322	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T155	1		T144	12		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	2		T135	13		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T29	29		T133	9		T213	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T139	11		T246	9		T210	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	10		T165	10		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	12		T37	1		T142	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T165	13		T204	16		T226	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T133	11		T51	1		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	6		T15	1		T251	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T138	10		T38	1		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T24	12		T15	3		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T14	2		T51	12		T228	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T28	1		T31	1		T167	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	1		T135	9		T38	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	6		T3	12		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T136	1		T165	15		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T136	1		T130	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	3		T133	1		T135	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T4	2		T5	3		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T139	12		T152	1		T207	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T133	10		T134	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T164	1		T152	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	1		T156	1		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T163	1		T15	13		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T6	9		T28	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T26	1		T133	12		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	2		T251	4		T245	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T51	2		T38	2		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T2	1		T11	1		T24	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T3	4		T14	5		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T137	1		T157	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T143	1		T169	12		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15837	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T274	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	12		T167	12		T38	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T38	8		T140	19		T228	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	3		T167	9		T231	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T165	14		T218	7		T302	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T130	12		T231	6		T146	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T133	11		T322	14		T320	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T4	21		T5	33		T7	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T139	10		T152	4		T207	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T133	8		T208	7		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T164	7		T152	5		T192	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	9		T15	13		T51	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T163	2		T15	13		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	6		T28	15		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T133	15		T16	1		T244	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	1		T251	2		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T140	11		T168	3		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	9		T11	13		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	1		T28	10		T51	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T39	1		T261	12		T316	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T143	15		T324	16		T220	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T230	13		T183	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T274	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T145	21		T323	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T3	4		T341	3		T22	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T321	1		T340	1		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T306	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	1		T167	1		T144	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T135	9		T38	8		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	12		T31	1		T38	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T134	1		T136	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	6		T136	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T133	1		T157	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	1		T155	2		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	3		T135	14		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T4	2		T5	3		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T164	1		T139	12		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T134	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T163	1		T15	13		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	1		T165	14		T204	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T26	1		T133	12		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	9		T11	1		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T206	1		T138	11		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T2	1		T24	13		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T14	5		T28	1		T51	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T145	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T341	14		T22	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T183	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	12		T167	12		T210	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	8		T140	19		T302	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	6		T231	22		T158	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T165	14		T218	7		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	3		T167	9		T130	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T133	11		T322	14		T324	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T155	15		T144	12		T146	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T152	4		T207	18		T147	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T4	21		T5	33		T7	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T164	7		T139	10		T152	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	9		T15	13		T165	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T163	2		T15	13		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T28	15		T165	9		T226	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	15		T319	2		T235	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	6		T11	13		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T140	11		T16	1		T244	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T2	9		T130	11		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T14	1		T28	10		T51	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33