Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21737

1

T1

20

T2

9

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

3643

1

T2

10

T6

15

T11

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19261

1

T1

20

T2

9

T3

12

auto[1]

6119

1

T2

10

T3

7

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	369	1			T140	14		T165	23		T254	23
values[0]	25	1			T137	1		T272	1		T273	1
values[1]	645	1			T133	12		T135	14		T167	10
values[2]	589	1			T2	10		T136	1		T164	8
values[3]	740	1			T3	3		T26	1		T133	27
values[4]	774	1			T6	15		T28	16		T31	1
values[5]	3126	1			T3	12		T4	23		T5	36
values[6]	664	1			T14	6		T163	3		T138	9
values[7]	775	1			T24	13		T28	13		T134	1
values[8]	738	1			T11	14		T28	11		T134	1
values[9]	1106	1			T2	9		T3	4		T31	1
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	616	1			T135	14		T167	10		T139	22
values[1]	695	1			T2	10		T15	3		T136	1
values[2]	591	1			T3	3		T26	1		T28	16
values[3]	3174	1			T4	23		T5	36		T6	15
values[4]	742	1			T3	12		T11	10		T31	1
values[5]	723	1			T14	6		T24	13		T163	3
values[6]	790	1			T28	13		T134	2		T156	1
values[7]	712	1			T11	14		T28	11		T31	1
values[8]	1048	1			T2	9		T51	22		T136	1
values[9]	251	1			T3	4		T152	6		T165	23
minimum	16038	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T135	1		T37	3		T144	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T167	10		T139	11		T140	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	2		T136	1		T152	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	10		T164	8		T130	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	1		T133	16		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T26	1		T28	16		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1702	1			T4	23		T5	36		T7	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	9		T133	9		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	1		T156	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	10		T31	1		T15	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	4		T163	3		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T24	1		T136	1		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T28	13		T134	2		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T156	1		T192	17		T207	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	14		T28	11		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T38	1		T263	18		T230	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T2	4		T51	8		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T138	1		T130	1		T231	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T3	1		T165	10		T271	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T152	6		T147	13		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15746	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T137	1		T38	9		T143	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T135	13		T37	1		T144	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	11		T144	9		T147	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	1		T16	1		T147	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	13		T142	12		T217	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	2		T133	11		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T15	3		T51	12		T155	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T29	29		T213	13		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	6		T133	9		T135	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	11		T138	8		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	12		T142	11		T212	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	2		T39	2		T253	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T24	12		T130	11		T251	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T246	9		T34	4		T215	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	1		T216	10		T274	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	10		T51	1		T165	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T263	5		T262	8		T220	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	5		T51	14		T38	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T138	10		T130	12		T204	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T3	3		T165	13		T239	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T149	10		T17	1		T91	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T38	9		T105	10		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T140	14		T165	10		T254	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T147	13		T304	1		T280	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T272	1		T343	9		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T137	1		T273	1		T344	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T133	12		T135	1		T269	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T167	10		T139	11		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	1		T37	3		T152	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	10		T164	8		T130	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	1		T133	16		T15	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T26	1		T134	1		T15	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T141	1		T16	1		T204	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	9		T28	16		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1729	1			T3	1		T4	23		T5	36
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	10		T31	1		T15	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	4		T163	3		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T141	1		T204	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T28	13		T134	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T24	1		T136	1		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	14		T28	11		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	1		T38	1		T230	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T2	4		T3	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T138	1		T130	1		T152	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T165	13		T254	9		T104	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T304	4		T345	2		T346	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T343	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T277	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T135	13		T243	4		T210	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	11		T38	9		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T37	1		T16	1		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T130	13		T142	12		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	2		T133	11		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	3		T51	12		T155	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	1		T204	8		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	6		T133	9		T135	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T3	11		T29	29		T213	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	12		T142	11		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T14	2		T138	8		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T251	3		T243	4		T245	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T246	9		T78	4		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T24	12		T130	11		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T51	1		T145	20		T228	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T87	1		T262	8		T220	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	5		T3	3		T15	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T138	10		T130	12		T204	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T135	14		T37	3		T144	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T167	1		T139	12		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	2		T136	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T164	1		T130	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	3		T133	12		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T26	1		T28	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T4	2		T5	3		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T6	9		T133	10		T135	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	12		T156	1		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T31	1		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	5		T163	1		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T24	13		T136	1		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T28	1		T134	2		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T156	1		T192	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T28	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	1		T263	6		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T2	6		T51	15		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T138	11		T130	13		T231	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T3	4		T165	14		T271	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T152	1		T147	1		T149	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15884	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T137	1		T38	12		T143	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T37	1		T144	8		T145	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T167	9		T139	10		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	1		T152	4		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	9		T164	7		T130	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T133	15		T210	9		T298	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	15		T51	10		T155	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T4	21		T5	33		T7	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	6		T133	8		T159	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T208	13		T144	12		T218	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	9		T15	13		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T14	1		T163	2		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T130	11		T251	2		T245	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	12		T146	11		T246	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T192	16		T207	15		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	13		T28	10		T15	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T263	17		T230	15		T347	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T2	3		T51	7		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T231	22		T228	11		T348	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T165	9		T18	8		T349	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T152	5		T147	12		T17	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T133	11		T317	13		T108	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T38	6		T143	15		T105	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T140	1		T165	14		T254	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T147	1		T304	5		T280	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T272	1		T343	7		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T137	1		T273	1		T344	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T133	1		T135	14		T269	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T167	1		T139	12		T38	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T136	1		T37	3		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	1		T164	1		T130	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	3		T133	12		T15	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	1		T134	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T141	1		T16	2		T204	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	9		T28	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T3	12		T4	2		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	1		T31	1		T15	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	5		T163	1		T138	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T141	1		T204	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	1		T134	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T24	13		T136	1		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	1		T28	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T156	1		T38	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T2	6		T3	4		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T138	11		T130	13		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T140	13		T165	9		T254	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T147	12		T280	12		T350	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T343	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T133	11		T210	1		T263	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T167	9		T139	10		T38	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T37	1		T152	4		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	9		T164	7		T130	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T133	15		T15	1		T210	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T51	10		T155	15		T165	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T244	6		T235	12		T96	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	6		T28	15		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T4	21		T5	33		T7	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	9		T15	13		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T14	1		T163	2		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T251	2		T245	10		T234	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	12		T146	11		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	11		T192	16		T207	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	13		T28	10		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T230	15		T87	1		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T2	3		T15	13		T51	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T152	5		T231	22		T228	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33