Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21774

1

T1

20

T2

19

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3606

1

T3

16

T6

15

T11

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19068

1

T1

20

T2

10

T3

4

auto[1]

6312

1

T2

9

T3

15

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	381	1			T2	9		T31	1		T206	1
values[0]	124	1			T51	22		T300	10		T301	1
values[1]	723	1			T136	1		T139	22		T38	2
values[2]	665	1			T11	14		T28	29		T133	12
values[3]	747	1			T156	1		T15	3		T167	13
values[4]	2892	1			T3	12		T4	23		T5	36
values[5]	754	1			T3	3		T11	10		T134	1
values[6]	749	1			T2	10		T6	15		T133	27
values[7]	764	1			T31	1		T163	3		T138	11
values[8]	702	1			T24	13		T133	18		T135	14
values[9]	1050	1			T3	4		T28	11		T31	1
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T51	22		T136	1		T139	22
values[1]	660	1			T11	14		T28	29		T133	12
values[2]	752	1			T14	6		T134	1		T156	1
values[3]	3034	1			T3	12		T4	23		T5	36
values[4]	667	1			T3	3		T134	2		T37	4
values[5]	704	1			T2	10		T6	15		T133	27
values[6]	675	1			T31	1		T163	3		T138	11
values[7]	737	1			T24	13		T133	18		T135	14
values[8]	1166	1			T2	9		T3	4		T28	11
values[9]	141	1			T158	7		T215	27		T332	13
minimum	16096	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T51	8		T136	1		T130	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	11		T218	14		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	12		T164	8		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	14		T28	29		T51	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	1		T156	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	4		T167	13		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1696	1			T4	23		T5	36		T7	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T11	10		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T134	1		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T134	1		T37	3		T140	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	10		T133	16		T231	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	9		T39	3		T165	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T31	1		T163	3		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T157	1		T208	8		T302	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T133	9		T38	1		T142	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T24	1		T135	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T2	4		T31	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	1		T28	11		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T304	1		T220	15		T307	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T158	7		T215	10		T332	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15800	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T147	19		T301	1		T349	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T51	14		T130	11		T145	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T139	11		T218	14		T243	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T130	12		T217	11		T226	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T51	12		T155	1		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	1		T135	8		T38	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	2		T253	11		T210	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T29	29		T15	13		T213	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	11		T15	12		T165	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	2		T16	1		T251	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T37	1		T204	16		T246	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T133	11		T212	7		T186	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	6		T39	2		T165	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T138	10		T38	7		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T17	1		T306	5		T314	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T133	9		T142	12		T33	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	12		T135	13		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T2	5		T138	8		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	3		T204	8		T228	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T304	4		T220	13		T307	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T215	17		T221	12		T351	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T147	9		T349	3		T312	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	4		T31	1		T206	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T152	5		T204	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T51	8		T21	1		T310	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T300	1		T301	1		T201	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T136	1		T157	1		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T139	11		T38	1		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	12		T164	8		T130	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	14		T28	29		T51	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T156	1		T15	2		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T167	13		T141	1		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T4	23		T5	36		T7	39
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T14	4		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	1		T16	1		T208	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	10		T134	1		T15	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	10		T133	16		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	9		T37	3		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T31	1		T163	3		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T157	1		T143	7		T17	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T133	9		T38	1		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	1		T135	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T156	1		T167	10		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T3	1		T28	11		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	5		T168	3		T234	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T204	8		T78	14		T288	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T51	14		T310	9		T311	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T300	9		T313	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T145	10		T254	9		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	11		T38	1		T218	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T130	11		T217	11		T226	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T51	12		T155	1		T243	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	1		T130	12		T38	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T253	11		T105	10		T314	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T29	29		T15	13		T213	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	11		T14	2		T165	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	2		T16	1		T145	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	12		T204	16		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T133	11		T251	3		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	6		T37	1		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T138	10		T38	7		T33	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	1		T215	8		T306	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T133	9		T142	12		T91	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	12		T135	13		T51	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T138	8		T130	13		T165	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	3		T228	10		T245	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T51	15		T136	1		T130	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T139	12		T218	15		T243	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T133	1		T164	1		T130	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	1		T28	2		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T134	1		T156	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	5		T167	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T4	2		T5	3		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	12		T11	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	3		T134	1		T16	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	1		T37	3		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	1		T133	12		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	9		T39	4		T165	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T31	1		T163	1		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T157	1		T208	1		T302	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T133	10		T38	1		T142	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T24	13		T135	14		T51	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T2	6		T31	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T3	4		T28	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T304	5		T220	14		T307	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T158	1		T215	18		T332	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15909	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T147	11		T301	1		T349	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T51	7		T130	11		T145	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	10		T218	13		T159	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T133	11		T164	7		T217	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	13		T28	27		T51	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	1		T38	6		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	1		T167	12		T207	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T4	21		T5	33		T7	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	9		T15	13		T165	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T208	6		T251	2		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T37	1		T140	6		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	9		T133	15		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	6		T39	1		T165	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T163	2		T38	8		T192	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T208	7		T302	1		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	8		T142	12		T33	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T152	5		T144	12		T245	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	3		T167	9		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T28	10		T152	4		T207	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T220	14		T299	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T158	6		T215	9		T332	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T104	14		T316	14		T317	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T147	17		T349	1		T312	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	6		T31	1		T206	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T152	1		T204	9		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T51	15		T21	1		T310	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T300	10		T301	1		T201	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T136	1		T157	1		T145	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	12		T38	2		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T133	1		T164	1		T130	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T28	2		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T156	1		T15	2		T130	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T167	1		T141	1		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T4	2		T5	3		T7	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	12		T14	5		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	3		T16	2		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T134	1		T15	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T133	12		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	9		T37	3		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T31	1		T163	1		T138	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T157	1		T143	1		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	10		T38	1		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T24	13		T135	14		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T156	1		T167	1		T138	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	4		T28	1		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T2	3		T140	13		T168	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T152	4		T78	12		T288	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T51	7		T310	8		T311	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T313	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T145	11		T254	13		T104	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T139	10		T140	11		T218	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T133	11		T164	7		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	13		T28	27		T51	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	1		T38	6		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T167	12		T319	2		T105	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T4	21		T5	33		T7	36
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	1		T165	9		T207	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T208	6		T231	6		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	9		T15	13		T140	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	9		T133	15		T251	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	6		T37	1		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T163	2		T38	8		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T143	6		T17	3		T215	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T133	8		T142	12		T192	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T152	5		T208	7		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T167	9		T130	12		T165	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T28	10		T207	6		T228	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33