Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T28	1		T15	5		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T51	13		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T4	2		T5	3		T6	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	2		T38	8		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T51	2		T37	3		T228	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	12		T136	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	6		T31	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T134	1		T138	9		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	3		T134	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	2		T231	1		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T24	13		T165	11		T204	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	5		T136	1		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T133	12		T137	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T28	1		T51	15		T207	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T156	2		T15	13		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T31	2		T133	10		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	4		T26	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T135	14		T143	1		T144	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T155	2		T41	16		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T15	13		T231	1		T91	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T28	12		T140	6		T208	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	9		T51	10		T140	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T4	21		T5	33		T6	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	22		T38	8		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T37	1		T228	6		T186	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T165	14		T192	16		T256	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T2	3		T133	11		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T78	6		T215	10		T105	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T208	6		T192	10		T207	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	1		T231	11		T228	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T165	15		T212	9		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	1		T167	9		T164	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T133	15		T152	5		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	10		T51	7		T207	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	13		T167	12		T218	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T133	8		T130	23		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T28	15		T139	10		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T143	6		T144	8		T246	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T155	15		T41	4		T96	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T15	13		T231	11		T247	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T236	17		T237	1		T238	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T218	15		T239	13		T248	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T157	1		T249	1		T250	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T28	1		T140	1		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	1		T51	13		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T4	2		T5	3		T7	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	1		T38	8		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	9		T133	1		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	12		T11	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	6		T163	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T134	1		T15	2		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	3		T31	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T251	4		T245	9		T83	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T24	13		T204	9		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	1		T164	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T133	12		T137	1		T165	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	5		T28	1		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T15	13		T130	13		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T134	1		T136	1		T130	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T3	4		T26	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T31	2		T15	13		T135	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T236	16		T238	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T218	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T249	9		T250	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T28	12		T140	6		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	9		T51	10		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T4	21		T5	33		T7	36
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	9		T38	8		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	6		T133	11		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T11	13		T165	14		T192	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	3		T163	2		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	1		T228	11		T78	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T208	6		T207	3		T148	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T251	2		T245	10		T214	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T192	10		T212	9		T168	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T164	7		T231	11		T254	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	15		T165	15		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T28	10		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	13		T152	5		T218	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T130	12		T207	15		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	15		T167	12		T155	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T15	13		T130	11		T231	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33