Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21662

1

T1

20

T2

19

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3718

1

T3

16

T11

14

T28

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18955

1

T1

20

T2

9

T3

19

auto[1]

6425

1

T2

10

T4

23

T5

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T265	3		T266	22		-	-
values[0]	48	1			T158	14		T81	1		T241	1
values[1]	706	1			T28	13		T31	1		T134	2
values[2]	823	1			T11	14		T14	6		T28	16
values[3]	772	1			T3	12		T6	15		T133	18
values[4]	842	1			T3	3		T31	1		T15	3
values[5]	669	1			T28	11		T133	27		T51	2
values[6]	654	1			T2	10		T11	10		T26	1
values[7]	596	1			T157	1		T143	16		T207	4
values[8]	3262	1			T4	23		T5	36		T7	39
values[9]	1154	1			T2	9		T3	4		T31	1
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	962	1			T14	6		T28	13		T31	1
values[1]	753	1			T3	12		T11	14		T28	16
values[2]	885	1			T6	15		T133	18		T134	1
values[3]	745	1			T3	3		T28	11		T31	1
values[4]	612	1			T26	1		T133	27		T136	1
values[5]	674	1			T2	10		T11	10		T51	22
values[6]	3108	1			T4	23		T5	36		T7	39
values[7]	765	1			T2	9		T15	5		T157	1
values[8]	838	1			T3	4		T31	1		T133	12
values[9]	209	1			T15	26		T38	16		T157	1
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T14	4		T31	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T28	13		T134	1		T15	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T28	16		T156	1		T140	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T11	14		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T6	9		T133	9		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	4		T246	9		T186	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T28	11		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	2		T51	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	1		T38	2		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T133	16		T136	1		T253	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	10		T11	10		T142	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T51	8		T167	10		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T4	23		T5	36		T7	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T130	13		T165	15		T143	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	4		T141	1		T207	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	2		T157	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T163	3		T136	1		T152	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T3	1		T31	1		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T157	1		T40	1		T218	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T15	16		T38	9		T208	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	2		T135	8		T142	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	12		T155	1		T130	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T204	8		T228	6		T210	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	11		T16	1		T228	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	6		T133	9		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	1		T246	9		T186	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	2		T139	11		T130	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	1		T51	1		T138	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T38	1		T144	9		T145	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T133	11		T253	11		T41	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T142	12		T145	10		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	14		T37	1		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T24	12		T29	29		T213	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	13		T165	14		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	5		T243	4		T227	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T15	3		T251	3		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T165	10		T254	9		T159	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	3		T204	16		T218	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T96	5		T267	4		T268	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T15	10		T38	7		T80	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T265	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T266	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T158	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T81	1		T241	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T31	1		T134	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	13		T134	1		T15	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	4		T28	16		T140	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	14		T136	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	9		T133	9		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T16	4		T228	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T31	1		T139	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	2		T138	1		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T28	11		T38	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T133	16		T51	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	10		T11	10		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T51	8		T136	1		T167	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T269	1		T146	12		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T157	1		T143	16		T207	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1681	1			T4	23		T5	36		T7	39
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T15	2		T130	13		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T2	4		T163	3		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T3	1		T31	1		T133	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T266	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T34	4		T270	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T135	8		T142	11		T78	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	12		T155	1		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	2		T204	8		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T130	12		T16	1		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	6		T133	9		T135	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	11		T16	1		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	2		T139	11		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T15	1		T138	8		T165	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T144	9		T212	7		T145	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T133	11		T51	1		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	1		T142	12		T145	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T51	14		T144	12		T147	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T253	6		T17	1		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T226	10		T261	6		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T24	12		T29	29		T213	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T15	3		T130	13		T165	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	5		T165	10		T254	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T3	3		T15	10		T38	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	5		T31	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T28	1		T134	1		T15	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T28	1		T156	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	12		T11	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T6	9		T133	10		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	4		T246	10		T186	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	3		T28	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	2		T51	2		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	1		T38	3		T144	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T133	12		T136	1		T253	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	1		T11	1		T142	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	15		T167	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T4	2		T5	3		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T130	14		T165	15		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	6		T141	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T15	5		T157	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T163	1		T136	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T3	4		T31	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T157	1		T40	1		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T15	13		T38	8		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	1		T142	11		T208	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T28	12		T15	13		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	15		T140	6		T207	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	13		T143	6		T145	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	6		T133	8		T51	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	1		T246	8		T186	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	10		T139	10		T130	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	1		T165	9		T231	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T145	12		T146	16		T147	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T133	15		T41	4		T244	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	9		T11	9		T142	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T51	7		T167	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T4	21		T5	33		T7	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T130	12		T165	14		T143	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	3		T207	3		T168	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T231	11		T251	2		T217	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T163	2		T152	5		T165	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T133	11		T218	13		T255	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T218	7		T96	4		T267	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T15	13		T38	8		T208	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T265	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T266	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T158	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T81	1		T241	1		T34	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	1		T134	1		T135	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	1		T134	1		T15	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	5		T28	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	1		T136	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T6	9		T133	10		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	12		T16	4		T228	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	3		T31	1		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T15	2		T138	9		T165	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T28	1		T38	1		T144	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	12		T51	2		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	1		T11	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T51	15		T136	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T269	1		T146	1		T253	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T157	1		T143	1		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T4	2		T5	3		T7	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T15	5		T130	14		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	6		T163	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T3	4		T31	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T265	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T266	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T158	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T270	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T142	11		T208	7		T192	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T28	12		T15	13		T155	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	1		T28	15		T140	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	13		T39	1		T143	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	6		T133	8		T51	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T16	1		T228	7		T186	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T139	10		T130	11		T192	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	1		T165	9		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T28	10		T212	9		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T133	15		T37	1		T78	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	9		T11	9		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	7		T167	9		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T146	11		T158	6		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	15		T207	3		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T4	21		T5	33		T7	36
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T130	12		T165	14		T218	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	3		T163	2		T152	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T133	11		T15	13		T38	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33